From ed8b64e07c95391d792c1904d1da7c543ec13608 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 30 Dec 2022 10:39:01 +0800 Subject: [PATCH] arm64: dts: rockchip: Add RK3562 test1 and test2 board devicetree Signed-off-by: Finley Xiao Signed-off-by: Frank Wang Signed-off-by: David Wu Signed-off-by: Shawn Lin Signed-off-by: shengfei Xu Change-Id: I1884bb4385a739b212f924f9996fe250ca0e8ffd --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3562-test1-ddr3-v10.dts | 9 + .../dts/rockchip/rk3562-test1-ddr3-v10.dtsi | 209 ++++++++++++++++++ .../dts/rockchip/rk3562-test2-ddr4-v10.dts | 9 + .../dts/rockchip/rk3562-test2-ddr4-v10.dtsi | 91 ++++++++ 5 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 6e597457138a..9f163afcdefd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts new file mode 100644 index 000000000000..e8b79e3ff265 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test1-ddr3-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi new file mode 100644 index 000000000000..23601ec2e332 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST1 DDR3 V10 Board"; + compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x3f>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim + &rgmiim1_tx_bus2 + &rgmiim1_rx_bus2 + &rgmiim1_rgmii_clk + &rgmiim1_rgmii_bus + ðm1_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pinctrl { + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd &sdmmc1_det>; + /* Should disable gmac0 and fix hardware if enabling sdmmc1 */ + status = "disabled"; +}; + +&pwm6 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_usb_otg>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts new file mode 100644 index 000000000000..811628398e79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi new file mode 100644 index 000000000000..312abc96ca57 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST2 DDR4 V10 Board"; + compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_clk>; + + phy-handle = <&rmii_phy>; + status = "okay"; +}; + +&mdio0 { + rmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pwm6 { + status = "okay"; +};