From edf7edcdee29061c5dcbae80e9a71f9983c25f08 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 28 Nov 2021 11:52:14 +0800 Subject: [PATCH] drm/rockchip: vop2: Check PMU_BISR_STATUS register for pd status when bisr enabled We should check PMU_BISR_STATUS register for pd on/off status when bisr memory repair is enabled. Signed-off-by: Andy Yan Change-Id: If1d0927551ddea9757c70b3a948367132a83ed5c --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 23 +++++++++++++++++--- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 14 ++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + 4 files changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index f7409da0c5ae..d7e3ea899a12 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -702,6 +702,8 @@ struct vop2_video_port_regs { struct vop2_power_domain_regs { struct vop_reg pd; struct vop_reg status; + struct vop_reg bisr_en_status; + struct vop_reg pmu_status; }; struct vop2_dsc_regs { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index dbbe3f1151bf..567a06f8b90c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -668,7 +668,7 @@ struct vop2 { struct regmap *sys_grf; struct regmap *vo0_grf; struct regmap *vo1_grf; - struct regmap *pmu; + struct regmap *sys_pmu; /* physical map length of vop2 register */ uint32_t len; @@ -777,6 +777,15 @@ static inline void vop2_grf_writel(struct regmap *regmap, struct vop_reg reg, u3 } } +static inline uint32_t vop2_grf_readl(struct regmap *regmap, const struct vop_reg *reg) +{ + uint32_t v; + + regmap_read(regmap, reg->offset, &v); + + return v; +} + static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v) { writel(v, vop2->regs + offset); @@ -794,6 +803,11 @@ static inline uint32_t vop2_read_reg(struct vop2 *vop2, uint32_t base, return (vop2_readl(vop2, base + reg->offset) >> reg->shift) & reg->mask; } +static inline uint32_t vop2_read_grf_reg(struct regmap *regmap, const struct vop_reg *reg) +{ + return (vop2_grf_readl(regmap, reg) >> reg->shift) & reg->mask; +} + static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset, uint32_t mask, uint32_t shift, uint32_t v, bool write_mask, bool relaxed) @@ -1314,7 +1328,10 @@ static uint32_t vop2_power_domain_status(struct vop2_power_domain *pd) { struct vop2 *vop2 = pd->vop2; - return vop2_read_reg(vop2, 0, &pd->data->regs->status); + if (vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->bisr_en_status)) + return vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->pmu_status); + else + return vop2_read_reg(vop2, 0, &pd->data->regs->status); } static void vop2_wait_power_domain_off(struct vop2_power_domain *pd) @@ -8223,7 +8240,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); - vop2->pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); + vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop"); if (IS_ERR(vop2->hclk)) { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index b29979736ca2..5c706664c1a7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1939,36 +1939,50 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { const struct vop2_power_domain_regs rk3588_cluster0_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 0), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 8), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 9), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 9), }; const struct vop2_power_domain_regs rk3588_cluster1_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 1), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 9), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 10), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 10), }; const struct vop2_power_domain_regs rk3588_cluster2_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 2), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 10), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 11), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 11), }; const struct vop2_power_domain_regs rk3588_cluster3_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 3), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 11), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 12), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 12), }; const struct vop2_power_domain_regs rk3588_esmart_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 7), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 15), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 15), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 15), }; const struct vop2_power_domain_regs rk3588_dsc_8k_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 5), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 13), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 13), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 13), }; const struct vop2_power_domain_regs rk3588_dsc_4k_pd_regs = { .pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 6), .status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 14), + .pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 14), + .bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 14), }; /* diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 3e14f43057b4..117f0e992522 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1623,6 +1623,7 @@ #define RK3588_PMU_SUBMEM_PWR_GATE_CON1 0x1B4 #define RK3588_PMU_SUBMEM_PWR_GATE_CON2 0x1B8 #define RK3588_PMU_SUBMEM_PWR_GATE_STATUS 0x1BC +#define RK3588_PMU_BISR_CON3 0x20C #define RK3588_PMU_BISR_STATUS5 0x294 #endif /* _ROCKCHIP_VOP_REG_H */