From eedb02740c74be8f0d65c8e77385ce25a7a02163 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 15 Dec 2021 16:24:26 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add volt-mem-read-margin for cpub Signed-off-by: Finley Xiao Change-Id: Ieb99848f01503da84e1d79f1b1ff4dbdafb55aa1 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 31815195a920..4e51494c77dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -448,6 +448,14 @@ compatible = "operating-points-v2"; opp-shared; + rockchip,grf = <&bigcore0_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <750000 750000 950000>, @@ -509,6 +517,14 @@ compatible = "operating-points-v2"; opp-shared; + rockchip,grf = <&bigcore1_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <750000 750000 950000>, @@ -1165,6 +1181,16 @@ }; }; + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + }; + + bigcore1_grf: syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + }; + vop_grf: syscon@fd5a4000 { compatible = "rockchip,rk3588-vop-grf", "syscon"; reg = <0x0 0xfd5a4000 0x0 0x2000>;