From ef1778cd88354c83abb0e365412bc92a53d90a4e Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 28 Nov 2017 15:22:32 +0800 Subject: [PATCH] ARM: dts: rockchip: add the needed power domain node on rk3036 As the vpu needed handle the power domain for reset function, this patch supported the vpu domain for rk3036 Socs. Change-Id: I67ad6085e2eb9a213c364d58713f02cc78ce6849 Signed-off-by: Caesar Wang --- arch/arm/boot/dts/rk3036.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 30ff501e7f00..a812ce4a27e1 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include / { @@ -198,6 +199,7 @@ assigned-clocks = <&cru ACLK_VCODEC>; assigned-clock-rates = <297000000>; assigned-clock-parents = <&cru PLL_GPLL>; + power-domains = <&power RK3036_PD_VPU>; status = "disabled"; }; @@ -209,6 +211,7 @@ interrupt-names = "irq_dec"; iommus = <&vpu_mmu>; allocator = <1>; + power-domains = <&power RK3036_PD_VPU>; }; vpu_mmu: iommu@10108800 { @@ -217,6 +220,7 @@ interrupts = ; interrupt-names = "vpu_mmu"; #iommu-cells = <0>; + power-domains = <&power RK3036_PD_VPU>; status = "disabled"; }; @@ -228,6 +232,7 @@ interrupt-names = "irq_dec"; allocator = <1>; iommus = <&hevc_mmu>; + power-domains = <&power RK3036_PD_VPU>; }; hevc_mmu: iommu@1010c440 { @@ -236,6 +241,7 @@ interrupts = ; interrupt-names = "hevc_mmu"; #iommu-cells = <0>; + power-domains = <&power RK3036_PD_VPU>; status = "disabled"; }; @@ -256,6 +262,7 @@ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>; reset-names = "video_a", "video_h", "video"; + power-domains = <&power RK3036_PD_VPU>; status = "disabled"; }; @@ -442,6 +449,21 @@ mode-bootloader = ; mode-loader = ; }; + + power: power-controller { + compatible = "rockchip,rk3036-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu@RK3036_PD_VPU { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>, + <&cru ACLK_HEVC>; + }; + + }; }; acodec: acodec-ana@20030000 {