From ef1eedc720deeb1c1fa81db239f829e233b23bf6 Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Mon, 16 May 2016 18:33:49 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3399: quirk for extra long delay for dwc3 xHCI It has been reported that xHCI on this SoC really cannot sleep without extraordinary delay. This quirk can ensure the xHCI enter the Halted state after the Run/Stop (R/S) bit is cleared to '0'. Change-Id: Ibccf0c5c2da4533817b998b523e3a3a09ed7dcea Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index dcee8fb278ce..41691119928f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -464,6 +464,7 @@ snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-slow-suspend-quirk; power-domains = <&power RK3399_PD_USB3>; status = "disabled"; }; @@ -495,6 +496,7 @@ snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-slow-suspend-quirk; power-domains = <&power RK3399_PD_USB3>; status = "disabled"; };