From ef3def055b3ef3e41aa7a99e7b1ecb56aa88b895 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 12 Jan 2021 15:23:20 +0800 Subject: [PATCH] dt-bindings: sound: rockchip: pdm: Document property 'mclk-calibrate' Change-Id: I64f010b9876fdf736ac6778c7bac52c47e9d905f Signed-off-by: Sugar Zhang --- .../devicetree/bindings/sound/rockchip,pdm.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt index a3096ce33f4c..688b6c7c5453 100644 --- a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt +++ b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt @@ -44,6 +44,11 @@ Optional properties: path2 <-- sdi1 path3 <-- sdi0 +- rockchip,mclk-calibrate: This is a boolean value, if present, enable + clk calibrate and compenation. + + note: the corresponding property 'pdm_clk_root' should be assigned. + Example for rk3328 PDM controller: pdm: pdm@ff040000 { @@ -66,3 +71,12 @@ pdm: pdm@ff040000 { &pdmm0_sdi2_sleep &pdmm0_sdi3_sleep>; }; + +Example for RV1126 PDM controller with mclk-calibrate: + +&pdm { + status = "okay"; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru PLL_CPLL>; + clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_root"; + rockchip,mclk-calibrate; +};