diff --git a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
index bdf1e05780b7..10867ae19da5 100644
--- a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
@@ -18,7 +18,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/amlogic,axg-clkc.h>
 #include <dt-bindings/gpio/mesonaxg-gpio.h>
-
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
 / {
 	cpus:cpus {
 		#address-cells = <2>;
@@ -248,6 +249,7 @@
 		};
 	};
 
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -304,6 +306,32 @@
 		};/* end of hiubus*/
 	}; /* end of soc*/
 
+	pwm:meson-pwm {
+		compatible = "amlogic, meson-pwm";
+		status = "okay";
+		#pwm-cells = <2>;
+		pwm-outputs = <PWM_A>,<PWM_B>,<PWM_C>,<PWM_D>,
+		<PWM_AO_A>,<PWM_AO_B>,<PWM_AO_C>,<PWM_AO_D>,
+		<PWM_A2>,<PWM_B2>,<PWM_C2>,<PWM_D2>,<PWM_AO_A2>,
+		<PWM_AO_B2>,<PWM_AO_C2>,<PWM_AO_D2>;
+		reg = <0x0 0xffd1b000  0x0 0x20>,
+				<0x0 0xffd1a000  0x0 0x20>,
+				<0x0 0xff807000  0x0 0x20>,
+				<0x0 0xff802000  0x0 0x20>;
+		clocks = <&xtal>,
+				<&clkc CLKID_PLL_VID_NOT>,
+				<&clkc CLKID_FCLK_DIV4>,
+				<&clkc CLKID_FCLK_DIV3>;
+		clock-names = "xtal",
+					"vid_pll_clk",
+					"fclk_div4",
+					"fclk_div3";
+		clock-select = <XTAL>,<XTAL>,<XTAL>,<XTAL>,
+						<XTAL>,<XTAL>,<XTAL>,<XTAL>;
+		/*all channels use the default clock source XTAL_CLK*/
+		/*and you can shoose it in file dt-bindings/pwm/meson.h*/
+	};
+
 };/* end of / */
 
 &pinctrl_aobus {
diff --git a/drivers/amlogic/pwm/pwm_meson.c b/drivers/amlogic/pwm/pwm_meson.c
index 3d9272fb00aa..c5c0d0b42ca9 100644
--- a/drivers/amlogic/pwm/pwm_meson.c
+++ b/drivers/amlogic/pwm/pwm_meson.c
@@ -451,6 +451,7 @@ static int pwm_meson_config_ext(struct aml_pwm_chip *aml_chip,
 		clk_mask = (0x7f << 16)|(1 << 23);
 		clk_val = (our_chan->pwm_pre_div << 16)|(1 << 23);
 		duty_reg = &aml_reg->db2r;
+		break;
 	default:
 		dev_err(aml_chip->chip.dev,
 				"config_ext,index is not legal\n");
@@ -634,26 +635,52 @@ static int pwm_aml_parse_addr_txlx(struct aml_pwm_chip *chip)
 	return 0;
 }
 
+static int pwm_aml_parse_addr_axg(struct aml_pwm_chip *chip)
+{
+	struct device_node *np = chip->chip.dev->of_node;
+
+	chip->baseaddr.ab_base = of_iomap(np, 0);
+	if (IS_ERR(chip->baseaddr.ab_base))
+		return PTR_ERR(chip->baseaddr.ab_base);
+
+	chip->baseaddr.cd_base = of_iomap(np, 1);
+	if (IS_ERR(chip->baseaddr.cd_base))
+		return PTR_ERR(chip->baseaddr.cd_base);
+
+	chip->baseaddr.aoab_base = of_iomap(np, 3);
+	if (IS_ERR(chip->baseaddr.aoab_base))
+		return PTR_ERR(chip->baseaddr.aoab_base);
+
+	chip->baseaddr.aocd_base = of_iomap(np, 4);
+	if (IS_ERR(chip->baseaddr.aocd_base))
+		return PTR_ERR(chip->baseaddr.aocd_base);
+
+	return 0;
+}
+
 static int pwm_aml_parse_addr(struct aml_pwm_chip *chip)
 {
 	unsigned int soc_id = get_cpu_type();
 
 	switch (soc_id) {
-	case MESON_CPU_MAJOR_ID_M8B:
+	case MESON_CPU_MAJOR_ID_M8B:/*3 group pwms*/
 		pwm_aml_parse_addr_m8b(chip);
 	break;
 	case MESON_CPU_MAJOR_ID_GXBB:
 	case MESON_CPU_MAJOR_ID_GXTVBB:
 	case MESON_CPU_MAJOR_ID_GXL:
-	case MESON_CPU_MAJOR_ID_GXM:
+	case MESON_CPU_MAJOR_ID_GXM:/*4 group pwms*/
 		pwm_aml_parse_addr_gxbb(chip);
 	break;
-	case MESON_CPU_MAJOR_ID_TXL:
+	case MESON_CPU_MAJOR_ID_TXL:/*5 group pwms,ao blink reg special*/
 		pwm_aml_parse_addr_txl(chip);
 	break;
-	case MESON_CPU_MAJOR_ID_TXLX:
+	case MESON_CPU_MAJOR_ID_TXLX:/*5 group pwms*/
 		pwm_aml_parse_addr_txlx(chip);
 	break;
+	case MESON_CPU_MAJOR_ID_AXG:/*4 group pwms*/
+		pwm_aml_parse_addr_axg(chip);
+	break;
 	default:
 		dev_err(chip->chip.dev, "not support soc\n");
 	break;
@@ -725,6 +752,11 @@ static int pwm_aml_parse_dt(struct aml_pwm_chip *chip)
 			(clock_co > AML_PWM_TXLX_NUM)) {
 			goto err;
 		}
+	case MESON_CPU_MAJOR_ID_AXG:
+		if ((output_co > AML_PWM_AXG_NUM) ||
+			(clock_co > AML_PWM_AXG_NUM)) {
+			goto err;
+		}
 	break;
 	default:
 		dev_err(chip->chip.dev, "%s not support\n", __func__);
@@ -785,8 +817,6 @@ static int pwm_aml_probe(struct platform_device *pdev)
 	pr_info("npwm= %d\n", chip->chip.npwm);
 	switch (soc_id) {
 	case MESON_CPU_MAJOR_ID_M8B:
-		chip->inverter_mask = BIT(chip->chip.npwm) - 1;
-		break;
 	case MESON_CPU_MAJOR_ID_GXBB:
 		chip->inverter_mask = BIT(chip->chip.npwm) - 1;
 		break;
@@ -794,9 +824,8 @@ static int pwm_aml_probe(struct platform_device *pdev)
 	case MESON_CPU_MAJOR_ID_GXL:
 	case MESON_CPU_MAJOR_ID_GXM:
 	case MESON_CPU_MAJOR_ID_TXL:
-		chip->inverter_mask = BIT(chip->chip.npwm/2) - 1;
-		break;
 	case MESON_CPU_MAJOR_ID_TXLX:
+	case MESON_CPU_MAJOR_ID_AXG:
 		chip->inverter_mask = BIT(chip->chip.npwm/2) - 1;
 		break;
 	default:
diff --git a/include/dt-bindings/pwm/meson.h b/include/dt-bindings/pwm/meson.h
index 5e5ceb7afdbc..cbe98820eea1 100644
--- a/include/dt-bindings/pwm/meson.h
+++ b/include/dt-bindings/pwm/meson.h
@@ -28,6 +28,9 @@
 #define	PWM_AO_A		6
 #define	PWM_AO_B		7
 
+/*
+ * Addtional 8 channels for gxtvbb , gxl ,gxm and txl
+ */
 #define	PWM_A2			8
 #define	PWM_B2			9
 #define	PWM_C2			10
diff --git a/include/linux/amlogic/pwm_meson.h b/include/linux/amlogic/pwm_meson.h
index 0d4676ba2669..806aa97297f7 100644
--- a/include/linux/amlogic/pwm_meson.h
+++ b/include/linux/amlogic/pwm_meson.h
@@ -40,6 +40,7 @@
 #define AML_PWM_GXBB_NUM		8
 #define AML_PWM_GXTVBB_NUM		16
 #define AML_PWM_TXLX_NUM		20
+#define AML_PWM_AXG_NUM			16