From efc3fbda717b49dfdfad2c760a6745a9db2afbea Mon Sep 17 00:00:00 2001
From: Zhihuan He <huan.he@rock-chips.com>
Date: Wed, 6 Nov 2019 18:20:42 +0800
Subject: [PATCH] drivers: devfreq: rockchip_dmc: rk3368: enable ddr 2T mode

Change-Id: I425e9ddb7d5c1d8e789283f3c6ae56efd62c252a
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
---
 drivers/devfreq/rockchip_dmc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c
index 5589cf4d2041..193fff4c8412 100644
--- a/drivers/devfreq/rockchip_dmc.c
+++ b/drivers/devfreq/rockchip_dmc.c
@@ -1070,6 +1070,7 @@ struct rk3368_dram_timing {
 	u32 phy_cmd_drv;
 	u32 phy_dqs_drv;
 	u32 phy_odt;
+	u32 ddr_2t;
 };
 
 struct rk3399_dram_timing {
@@ -1831,6 +1832,8 @@ static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
 					    &timing->phy_dqs_drv);
 		ret |= of_property_read_u32(np_tim, "phy_odt",
 					    &timing->phy_odt);
+		ret |= of_property_read_u32(np_tim, "ddr_2t",
+					    &timing->ddr_2t);
 		if (ret) {
 			devm_kfree(dev, timing);
 			goto err;