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drm/rockchip: Add support for vop2

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Rockchip vop2 build on a unified architecture with
multi video output ports support.

For RK3568:
* 3 Video Port, every video port can drive a display timing independently.
* 6 graphic window: Cluster win x 2, Esmart win x 2, Smart wind x 2.
* 6 windows can be divided into 3 groups for independent overlay for
  3 Video Ports.
* RGB/eDP/HDMI/MIPI get display timing from 1 of the 3 Video Ports.

+----------+   +-------------+
|  Cluster |   | Sel 1 from 6|   +--------------------+
|  window0 |   |    Layer0   |   |n from 6|           |
+----------+   +-------------+   |        |Video Port0|
+----------+   +-------------+   |Overlay |           |
|  Cluster |   | Sel 1 from 6|   +--------+-----------+
|  window1 |   |    Layer1   |
+----------+   +-------------+
+----------+   +-------------+
|  Esmart  |   | Sel 1 from 6|
|  window0 |   |   Layer2    |   +--------------------+
+----------+   +-------------+   |n from 6|           |
+----------+   +-------------+   |        |Video Port1|
|  Esmart  |   | Sel 1 from 6|   |Overlay |           |
|  Window1 |   |   Layer3    |   +--------+-----------+
+----------+   +-------------+
+----------+   +-------------+
|  Smart   |   | Sel 1 from 6|
|  Window0 |   |    Layer4   |   +--------------------+
+----------+   +-------------+   |n from 6|           |
+----------+   +-------------+   |        |Video Port2|
|  Smart   |   | Sel 1 from 6|   |Overlay |           |
|  Window1 |   |    Layer5   |   +--------+-----------+
+----------+   +-------------+

Change-Id: I4c42d655f75903066888b6aea92e926192b000c2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2020-07-06 09:56:42 +08:00
committed by Tao Huang
parent 8d7cdbbea2
commit efe0578ec8
6 changed files with 5624 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/rockchip/Makefile
View File

@@ -5,7 +5,8 @@
rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchip_drm_gem.o rockchip_drm_psr.o \
rockchip_drm_vop.o rockchip_vop_reg.o
rockchip_drm_vop.o rockchip_vop_reg.o \
rockchip_drm_vop2.o rockchip_vop2_reg.o
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o

3
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -28,7 +28,8 @@
#define ROCKCHIP_MAX_FB_BUFFER 3
#define ROCKCHIP_MAX_CONNECTOR 2
#define ROCKCHIP_MAX_CRTC 2
#define ROCKCHIP_MAX_CRTC 4
#define ROCKCHIP_MAX_LAYER 16
struct drm_device;
struct drm_connector;

320
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -292,6 +292,26 @@ struct vop_scl_regs {
struct vop_reg scale_cbcr_y;
};
struct vop_afbc {
struct vop_reg enable;
struct vop_reg win_sel;
struct vop_reg format;
struct vop_reg rotate;
struct vop_reg block_split_en;
struct vop_reg pic_vir_width;
struct vop_reg tile_num;
struct vop_reg pic_offset;
struct vop_reg pic_size;
struct vop_reg dsp_offset;
struct vop_reg hdr_ptr;
struct vop_reg half_block_en;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rotate_270;
struct vop_reg rotate_90;
struct vop_reg rstn;
};
struct vop_csc_table {
const uint32_t *y2r_bt601;
const uint32_t *y2r_bt601_12_235;
@@ -411,6 +431,115 @@ struct vop_win_phy {
struct vop_reg key_en;
};
struct vop2_scl_regs {
struct vop_reg scale_yrgb_x;
struct vop_reg scale_yrgb_y;
struct vop_reg scale_cbcr_x;
struct vop_reg scale_cbcr_y;
struct vop_reg yrgb_hor_scl_mode;
struct vop_reg yrgb_hscl_filter_mode;
struct vop_reg yrgb_ver_scl_mode;
struct vop_reg yrgb_vscl_filter_mode;
struct vop_reg cbcr_ver_scl_mode;
struct vop_reg cbcr_hscl_filter_mode;
struct vop_reg cbcr_hor_scl_mode;
struct vop_reg cbcr_vscl_filter_mode;
struct vop_reg vsd_cbcr_gt2;
struct vop_reg vsd_cbcr_gt4;
struct vop_reg vsd_yrgb_gt2;
struct vop_reg vsd_yrgb_gt4;
struct vop_reg bic_coe_sel;
};
struct vop2_win_regs {
const struct vop2_scl_regs *scl;
const struct vop_afbc *afbc;
struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format;
struct vop_reg csc_mode;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rb_swap;
struct vop_reg act_info;
struct vop_reg dsp_info;
struct vop_reg dsp_st;
struct vop_reg yrgb_mst;
struct vop_reg uv_mst;
struct vop_reg yrgb_vir;
struct vop_reg uv_vir;
struct vop_reg lb_mode;
struct vop_reg y2r_en;
struct vop_reg r2y_en;
struct vop_reg channel;
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg global_alpha_val;
struct vop_reg key_color;
struct vop_reg key_en;
};
struct vop2_video_port_regs {
struct vop_reg cfg_done;
struct vop_reg overlay_mode;
struct vop_reg port_mux;
struct vop_reg out_mode;
struct vop_reg standby;
struct vop_reg dsp_interlace;
struct vop_reg pre_scan_htiming;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
struct vop_reg vtotal_pw;
struct vop_reg vact_st_end;
struct vop_reg vact_st_end_f1;
struct vop_reg vs_st_end_f1;
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
struct vop_reg vpost_st_end_f1;
struct vop_reg post_scl_factor;
struct vop_reg post_scl_ctrl;
struct vop_reg dither_down_sel;
struct vop_reg dither_down_mode;
struct vop_reg dither_down_en;
struct vop_reg pre_dither_down_en;
struct vop_reg dither_up_en;
struct vop_reg bg_dly;
struct vop_reg core_dclk_div;
struct vop_reg p2i_en;
struct vop_reg mipi_dual_en;
struct vop_reg mipi_dual_channel_swap;
struct vop_reg hdr_lut_update_en;
struct vop_reg hdr_lut_mode;
struct vop_reg hdr_lut_mst;
struct vop_reg sdr2hdr_eotf_en;
struct vop_reg sdr2hdr_r2r_en;
struct vop_reg sdr2hdr_r2r_mode;
struct vop_reg sdr2hdr_oetf_en;
struct vop_reg sdr2hdr_bypass_en;
struct vop_reg sdr2hdr_gating_en;
struct vop_reg hdr2sdr_en;
struct vop_reg hdr2sdr_src_min;
struct vop_reg hdr2sdr_src_max;
struct vop_reg hdr2sdr_normfaceetf;
struct vop_reg hdr2sdr_dst_min;
struct vop_reg hdr2sdr_dst_max;
struct vop_reg hdr2sdr_normfacgamma;
struct vop_reg hdr2sdr_eetf_oetf_y0_offset;
struct vop_reg hdr2sdr_sat_y0_offset;
struct vop_reg sdr2hdr_eotf_oetf_y0_offset;
struct vop_reg sdr2hdr_oetf_dx_pow1_offset;
struct vop_reg sdr2hdr_oetf_xn1_offset;
struct vop_reg hdr_src_color_ctrl;
struct vop_reg hdr_dst_color_ctrl;
struct vop_reg hdr_src_alpha_ctrl;
struct vop_reg hdr_dst_alpha_ctrl;
};
struct vop_win_data {
uint32_t base;
enum drm_plane_type type;
@@ -421,6 +550,81 @@ struct vop_win_data {
u64 feature;
};
struct vop2_win_data {
const char *name;
uint8_t phys_id;
uint32_t base;
enum drm_plane_type type;
uint32_t nformats;
const uint32_t *formats;
const unsigned int supported_rotations;
const struct vop2_win_regs *regs;
const struct vop2_win_regs **area;
unsigned int area_size;
/*
* vertical/horizontal scale up/down filter mode
*/
const u8 hsu_filter_mode;
const u8 hsd_filter_mode;
const u8 vsu_filter_mode;
const u8 vsd_filter_mode;
/**
* @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
*/
int layer_sel_id;
uint64_t feature;
unsigned int max_upscale_factor;
unsigned int max_downscale_factor;
};
struct vop2_video_port_data {
char id;
uint32_t feature;
uint64_t soc_id;
const u8 pre_scan_max_dly[4];
const struct vop_intr *intr;
const struct vop_hdr_table *hdr_table;
const struct vop2_video_port_regs *regs;
};
struct vop2_layer_regs {
struct vop_reg layer_sel;
};
/**
* struct vop2_layer_data - The logic graphic layer in vop2
*
* The zorder:
* LAYERn
* LAYERn-1
* .
* .
* .
* LAYER5
* LAYER4
* LAYER3
* LAYER2
* LAYER1
* LAYER0
*
* Each layer can select a unused window as input than feed to
* mixer for overlay.
*
* The pipeline in vop2:
*
* win-->layer-->mixer-->vp--->connector(RGB/LVDS/HDMI/MIPI)
*
*/
struct vop2_layer_data {
char id;
const struct vop2_layer_regs *regs;
};
struct vop_grf_ctrl {
struct vop_reg grf_dclk_inv;
};
@@ -433,6 +637,8 @@ struct vop_grf_ctrl {
#define WIN_FEATURE_SDR2HDR BIT(1)
#define WIN_FEATURE_PRE_OVERLAY BIT(2)
#define WIN_FEATURE_AFBDC BIT(3)
#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
#define WIN_FEATURE_CLUSTER_SUB BIT(5)
struct vop_rect {
int width;
@@ -455,6 +661,106 @@ struct vop_data {
u64 feature;
};
struct vop2_ctrl {
struct vop_reg cfg_done_en;
struct vop_reg ovl_cfg_done_port;
struct vop_reg ovl_port_mux_cfg_done_imd;
struct vop_reg if_ctrl_cfg_done_imd;
struct vop_reg version;
struct vop_reg standby;
struct vop_reg dma_stop;
struct vop_reg axi_outstanding_max_num;
struct vop_reg axi_max_outstanding_en;
struct vop_reg hdmi_dclk_out_en;
struct vop_reg rgb_en;
struct vop_reg hdmi0_en;
struct vop_reg hdmi1_en;
struct vop_reg dp0_en;
struct vop_reg dp1_en;
struct vop_reg edp0_en;
struct vop_reg edp1_en;
struct vop_reg mipi0_en;
struct vop_reg mipi1_en;
struct vop_reg lvds0_en;
struct vop_reg lvds1_en;
struct vop_reg bt656_en;
struct vop_reg bt1120_en;
struct vop_reg dclk_pol;
struct vop_reg pin_pol;
struct vop_reg rgb_dclk_pol;
struct vop_reg rgb_pin_pol;
struct vop_reg lvds_dclk_pol;
struct vop_reg lvds_pin_pol;
struct vop_reg hdmi_dclk_pol;
struct vop_reg hdmi_pin_pol;
struct vop_reg edp_dclk_pol;
struct vop_reg edp_pin_pol;
struct vop_reg mipi_dclk_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg dp_dclk_pol;
struct vop_reg dp_pin_pol;
struct vop_reg win_vp_id[8];
/* connector mux */
struct vop_reg rgb_mux;
struct vop_reg hdmi0_mux;
struct vop_reg hdmi1_mux;
struct vop_reg dp0_mux;
struct vop_reg dp1_mux;
struct vop_reg edp0_mux;
struct vop_reg edp1_mux;
struct vop_reg mipi0_mux;
struct vop_reg mipi1_mux;
struct vop_reg lvds0_mux;
struct vop_reg lvds1_mux;
struct vop_reg lvds_dual_en;
struct vop_reg lvds_dual_mode;
struct vop_reg lvds_dual_channel_swap;
struct vop_reg cluster0_src_color_ctrl;
struct vop_reg cluster0_dst_color_ctrl;
struct vop_reg cluster0_src_alpha_ctrl;
struct vop_reg cluster0_dst_alpha_ctrl;
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
struct vop_reg src_alpha_ctrl;
struct vop_reg dst_alpha_ctrl;
struct vop_reg bt1120_yc_swap;
struct vop_reg reg_done_frm;
struct vop_reg cfg_done;
};
/**
* VOP2 data structe
*
* @version: VOP IP version
* @win_size: hardware win number
*/
struct vop2_data {
uint32_t version;
uint32_t feature;
uint8_t nr_vps;
uint8_t nr_mixers;
uint8_t nr_layers;
uint8_t nr_axi_intr;
const struct vop_intr *axi_intr;
const struct vop2_ctrl *ctrl;
const struct vop2_win_data *win;
const struct vop2_video_port_data *vp;
const struct vop2_layer_data *layer;
const struct vop_csc_table *csc_table;
const struct vop_hdr_table *hdr_table;
const struct vop_grf_ctrl *grf_ctrl;
struct vop_rect max_input;
struct vop_rect max_output;
unsigned int win_size;
};
#define CVBS_PAL_VDISPLAY 288
/* interrupt define */
@@ -559,6 +865,7 @@ enum factor_mode {
ALPHA_SRC,
ALPHA_SRC_INVERSE,
ALPHA_SRC_GLOBAL,
ALPHA_DST_GLOBAL,
};
enum scale_mode {
@@ -586,6 +893,18 @@ enum scale_down_mode {
SCALE_DOWN_AVG = 0x1
};
enum vop2_scale_up_mode {
VOP2_SCALE_UP_NRST_NBOR,
VOP2_SCALE_UP_BIL,
VOP2_SCALE_UP_BIC,
};
enum vop2_scale_down_mode {
VOP2_SCALE_DOWN_NRST_NBOR,
VOP2_SCALE_DOWN_BIL,
VOP2_SCALE_DOWN_AVG,
};
enum dither_down_mode {
RGB888_TO_RGB565 = 0x0,
RGB888_TO_RGB666 = 0x1
@@ -688,4 +1007,5 @@ static inline int interpolate(int x1, int y1, int x2, int y2, int x)
}
extern const struct component_ops vop_component_ops;
extern const struct component_ops vop2_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */

3971
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c Normal file
View File

File diff suppressed because it is too large Load Diff

950
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c Normal file
View File

@@ -0,0 +1,950 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) Rockchip Electronics Co.Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
*/
#include <drm/drmP.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include "rockchip_drm_vop.h"
#include "rockchip_vop_reg.h"
#define _VOP_REG(off, _mask, _shift, _write_mask) \
{ \
.offset = off, \
.mask = _mask, \
.shift = _shift, \
.write_mask = _write_mask, \
}
#define VOP_REG(off, _mask, _shift) \
_VOP_REG(off, _mask, _shift, false)
#define VOP_REG_MASK(off, _mask, s) \
_VOP_REG(off, _mask, s, true)
static const uint32_t formats_win_full_10bit[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
DRM_FORMAT_NV12,
DRM_FORMAT_NV16,
DRM_FORMAT_NV24,
DRM_FORMAT_NV12_10,
DRM_FORMAT_NV16_10,
DRM_FORMAT_NV24_10,
};
static const uint32_t formats_win_lite[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
};
static const u32 sdr2hdr_bt1886eotf_yn_for_hlg_hdr[65] = {
0,
1, 7, 17, 35,
60, 92, 134, 184,
244, 315, 396, 487,
591, 706, 833, 915,
1129, 1392, 1717, 2118,
2352, 2612, 2900, 3221,
3577, 3972, 4411, 4899,
5441, 6042, 6710, 7452,
7853, 8276, 8721, 9191,
9685, 10207, 10756, 11335,
11945, 12588, 13266, 13980,
14732, 15525, 16361, 17241,
17699, 18169, 18652, 19147,
19656, 20178, 20714, 21264,
21829, 22408, 23004, 23615,
24242, 24886, 25547, 26214,
};
static const u32 sdr2hdr_bt1886eotf_yn_for_bt2020[65] = {
0,
1820, 3640, 5498, 7674,
10256, 13253, 16678, 20539,
24847, 29609, 34833, 40527,
46699, 53354, 60499, 68141,
76285, 84937, 94103, 103787,
108825, 113995, 119296, 124731,
130299, 136001, 141837, 147808,
153915, 160158, 166538, 173055,
176365, 179709, 183089, 186502,
189951, 193434, 196952, 200505,
204093, 207715, 211373, 215066,
218795, 222558, 226357, 230191,
232121, 234060, 236008, 237965,
239931, 241906, 243889, 245882,
247883, 249894, 251913, 253941,
255978, 258024, 260079, 262143,
};
static u32 sdr2hdr_bt1886eotf_yn_for_hdr[65] = {
/* dst_range 425int */
0,
5, 21, 49, 91,
150, 225, 320, 434,
569, 726, 905, 1108,
1336, 1588, 1866, 2171,
2502, 2862, 3250, 3667,
3887, 4114, 4349, 4591,
4841, 5099, 5364, 5638,
5920, 6209, 6507, 6812,
6968, 7126, 7287, 7449,
7613, 7779, 7948, 8118,
8291, 8466, 8643, 8822,
9003, 9187, 9372, 9560,
9655, 9750, 9846, 9942,
10039, 10136, 10234, 10333,
10432, 10531, 10631, 10732,
10833, 10935, 11038, 11141,
};
static const u32 sdr2hdr_st2084oetf_yn_for_hlg_hdr[65] = {
0,
668, 910, 1217, 1600,
2068, 2384, 2627, 3282,
3710, 4033, 4879, 5416,
5815, 6135, 6401, 6631,
6833, 7176, 7462, 7707,
7921, 8113, 8285, 8442,
8586, 8843, 9068, 9268,
9447, 9760, 10027, 10259,
10465, 10650, 10817, 10971,
11243, 11480, 11689, 11877,
12047, 12202, 12345, 12477,
12601, 12716, 12926, 13115,
13285, 13441, 13583, 13716,
13839, 13953, 14163, 14350,
14519, 14673, 14945, 15180,
15570, 15887, 16153, 16383,
};
static const u32 sdr2hdr_st2084oetf_yn_for_bt2020[65] = {
0,
0, 0, 1, 2,
4, 6, 9, 18,
27, 36, 72, 108,
144, 180, 216, 252,
288, 360, 432, 504,
576, 648, 720, 792,
864, 1008, 1152, 1296,
1444, 1706, 1945, 2166,
2372, 2566, 2750, 2924,
3251, 3553, 3834, 4099,
4350, 4588, 4816, 5035,
5245, 5447, 5832, 6194,
6536, 6862, 7173, 7471,
7758, 8035, 8560, 9055,
9523, 9968, 10800, 11569,
12963, 14210, 15347, 16383,
};
static u32 sdr2hdr_st2084oetf_yn_for_hdr[65] = {
0,
281, 418, 610, 871,
1217, 1464, 1662, 2218,
2599, 2896, 3699, 4228,
4628, 4953, 5227, 5466,
5676, 6038, 6341, 6602,
6833, 7039, 7226, 7396,
7554, 7835, 8082, 8302,
8501, 8848, 9145, 9405,
9635, 9842, 10031, 10204,
10512, 10779, 11017, 11230,
11423, 11599, 11762, 11913,
12054, 12185, 12426, 12641,
12835, 13013, 13177, 13328,
13469, 13600, 13840, 14055,
14248, 14425, 14737, 15006,
15453, 15816, 16121, 16383,
};
static const u32 sdr2hdr_st2084oetf_dxn_pow2[64] = {
0, 0, 1, 2,
3, 3, 3, 5,
5, 5, 7, 7,
7, 7, 7, 7,
7, 8, 8, 8,
8, 8, 8, 8,
8, 9, 9, 9,
9, 10, 10, 10,
10, 10, 10, 10,
11, 11, 11, 11,
11, 11, 11, 11,
11, 11, 12, 12,
12, 12, 12, 12,
12, 12, 13, 13,
13, 13, 14, 14,
15, 15, 15, 15,
};
static const u32 sdr2hdr_st2084oetf_dxn[64] = {
1, 1, 2, 4,
8, 8, 8, 32,
32, 32, 128, 128,
128, 128, 128, 128,
128, 256, 256, 256,
256, 256, 256, 256,
256, 512, 512, 512,
512, 1024, 1024, 1024,
1024, 1024, 1024, 1024,
2048, 2048, 2048, 2048,
2048, 2048, 2048, 2048,
2048, 2048, 4096, 4096,
4096, 4096, 4096, 4096,
4096, 4096, 8192, 8192,
8192, 8192, 16384, 16384,
32768, 32768, 32768, 32768,
};
static const u32 sdr2hdr_st2084oetf_xn[63] = {
1, 2, 4, 8,
16, 24, 32, 64,
96, 128, 256, 384,
512, 640, 768, 896,
1024, 1280, 1536, 1792,
2048, 2304, 2560, 2816,
3072, 3584, 4096, 4608,
5120, 6144, 7168, 8192,
9216, 10240, 11264, 12288,
14336, 16384, 18432, 20480,
22528, 24576, 26624, 28672,
30720, 32768, 36864, 40960,
45056, 49152, 53248, 57344,
61440, 65536, 73728, 81920,
90112, 98304, 114688, 131072,
163840, 196608, 229376,
};
static u32 hdr2sdr_eetf_yn[33] = {
1716,
1880, 2067, 2277, 2508,
2758, 3026, 3310, 3609,
3921, 4246, 4581, 4925,
5279, 5640, 6007, 6380,
6758, 7140, 7526, 7914,
8304, 8694, 9074, 9438,
9779, 10093, 10373, 10615,
10812, 10960, 11053, 11084,
};
static u32 hdr2sdr_bt1886oetf_yn[33] = {
0,
0, 0, 0, 0,
0, 0, 0, 314,
746, 1323, 2093, 2657,
3120, 3519, 3874, 4196,
4492, 5024, 5498, 5928,
6323, 7034, 7666, 8239,
8766, 9716, 10560, 11325,
12029, 13296, 14422, 16383,
};
static const u32 hdr2sdr_sat_yn[9] = {
0,
1792, 3584, 3472, 2778,
2083, 1389, 694, 0,
};
static const struct vop_hdr_table rk3568_vop_hdr_table = {
.hdr2sdr_eetf_yn = hdr2sdr_eetf_yn,
.hdr2sdr_bt1886oetf_yn = hdr2sdr_bt1886oetf_yn,
.hdr2sdr_sat_yn = hdr2sdr_sat_yn,
.hdr2sdr_src_range_min = 494,
.hdr2sdr_src_range_max = 12642,
.hdr2sdr_normfaceetf = 1327,
.hdr2sdr_dst_range_min = 4,
.hdr2sdr_dst_range_max = 3276,
.hdr2sdr_normfacgamma = 5120,
.sdr2hdr_bt1886eotf_yn_for_hlg_hdr = sdr2hdr_bt1886eotf_yn_for_hlg_hdr,
.sdr2hdr_bt1886eotf_yn_for_bt2020 = sdr2hdr_bt1886eotf_yn_for_bt2020,
.sdr2hdr_bt1886eotf_yn_for_hdr = sdr2hdr_bt1886eotf_yn_for_hdr,
.sdr2hdr_st2084oetf_yn_for_hlg_hdr = sdr2hdr_st2084oetf_yn_for_hlg_hdr,
.sdr2hdr_st2084oetf_yn_for_bt2020 = sdr2hdr_st2084oetf_yn_for_bt2020,
.sdr2hdr_st2084oetf_yn_for_hdr = sdr2hdr_st2084oetf_yn_for_hdr,
.sdr2hdr_st2084oetf_dxn_pow2 = sdr2hdr_st2084oetf_dxn_pow2,
.sdr2hdr_st2084oetf_dxn = sdr2hdr_st2084oetf_dxn,
.sdr2hdr_st2084oetf_xn = sdr2hdr_st2084oetf_xn,
};
static const int rk3568_vop_axi_intrs[] = {
0,
BUS_ERROR_INTR,
};
static const struct vop_intr rk3568_vop_axi_intr[] = {
{
.intrs = rk3568_vop_axi_intrs,
.nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
.status = VOP_REG(RK3568_SYS0_INT_STATUS, 0xfe, 0),
.enable = VOP_REG_MASK(RK3568_SYS0_INT_EN, 0xfe, 0),
.clear = VOP_REG_MASK(RK3568_SYS0_INT_CLR, 0xfe, 0),
},
{
.intrs = rk3568_vop_axi_intrs,
.nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
.status = VOP_REG(RK3568_SYS1_INT_STATUS, 0xfe, 0),
.enable = VOP_REG_MASK(RK3568_SYS1_INT_EN, 0xfe, 0),
.clear = VOP_REG_MASK(RK3568_SYS1_INT_CLR, 0xfe, 0),
},
};
static const int rk3568_vop_intrs[] = {
FS_INTR,
FS_NEW_INTR,
LINE_FLAG_INTR,
LINE_FLAG1_INTR,
POST_BUF_EMPTY_INTR,
FS_FIELD_INTR,
DSP_HOLD_VALID_INTR,
};
static const struct vop_intr rk3568_vp0_intr = {
.intrs = rk3568_vop_intrs,
.nintrs = ARRAY_SIZE(rk3568_vop_intrs),
.line_flag_num[0] = VOP_REG(RK3568_VP0_LINE_FLAG, 0x1fff, 0),
.line_flag_num[1] = VOP_REG(RK3568_VP0_LINE_FLAG, 0x1fff, 16),
.status = VOP_REG(RK3568_VP0_INT_STATUS, 0xffff, 0),
.enable = VOP_REG_MASK(RK3568_VP0_INT_EN, 0xffff, 0),
.clear = VOP_REG_MASK(RK3568_VP0_INT_CLR, 0xffff, 0),
};
static const struct vop_intr rk3568_vp1_intr = {
.intrs = rk3568_vop_intrs,
.nintrs = ARRAY_SIZE(rk3568_vop_intrs),
.line_flag_num[0] = VOP_REG(RK3568_VP1_LINE_FLAG, 0x1fff, 0),
.line_flag_num[1] = VOP_REG(RK3568_VP1_LINE_FLAG, 0x1fff, 16),
.status = VOP_REG(RK3568_VP1_INT_STATUS, 0xffff, 0),
.enable = VOP_REG_MASK(RK3568_VP1_INT_EN, 0xffff, 0),
.clear = VOP_REG_MASK(RK3568_VP1_INT_CLR, 0xffff, 0),
};
static const struct vop_intr rk3568_vp2_intr = {
.intrs = rk3568_vop_intrs,
.nintrs = ARRAY_SIZE(rk3568_vop_intrs),
.line_flag_num[0] = VOP_REG(RK3568_VP2_LINE_FLAG, 0x1fff, 0),
.line_flag_num[1] = VOP_REG(RK3568_VP2_LINE_FLAG, 0x1fff, 16),
.status = VOP_REG(RK3568_VP2_INT_STATUS, 0xffff, 0),
.enable = VOP_REG_MASK(RK3568_VP2_INT_EN, 0xffff, 0),
.clear = VOP_REG_MASK(RK3568_VP2_INT_CLR, 0xffff, 0),
};
static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
.mipi_dual_en = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 20),
.mipi_dual_channel_swap = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 21),
.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
.sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
.sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
.sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
.sdr2hdr_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
.hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
.hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
.hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
.hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
.hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
.hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
.hdr2sdr_eetf_oetf_y0_offset = VOP_REG(RK3568_HDR_EETF_OETF_Y0, 0xffffffff, 0),
.hdr2sdr_sat_y0_offset = VOP_REG(RK3568_HDR_SAT_Y0, 0xffffffff, 0),
.sdr2hdr_eotf_oetf_y0_offset = VOP_REG(RK3568_HDR_EOTF_OETF_Y0, 0xffffffff, 0),
.sdr2hdr_oetf_dx_pow1_offset = VOP_REG(RK3568_HDR_OETF_DX_POW1, 0xffffffff, 0),
.sdr2hdr_oetf_xn1_offset = VOP_REG(RK3568_HDR_OETF_XN1, 0xffffffff, 0),
.hdr_src_color_ctrl = VOP_REG(RK3568_HDR0_SRC_COLOR_CTRL, 0xffffffff, 0),
.hdr_dst_color_ctrl = VOP_REG(RK3568_HDR0_DST_COLOR_CTRL, 0xffffffff, 0),
.hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR0_SRC_ALPHA_CTRL, 0xffffffff, 0),
.hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR0_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
.mipi_dual_en = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 20),
.mipi_dual_channel_swap = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 21),
};
static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.post_scl_factor = VOP_REG(RK3568_VP2_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.pre_dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
.mipi_dual_en = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 20),
.mipi_dual_channel_swap = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 21),
};
static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
{
.id = 0,
.soc_id = 0x3568,
.pre_scan_max_dly = { 40, 49, 33, 42 },
.intr = &rk3568_vp0_intr,
.hdr_table = &rk3568_vop_hdr_table,
.regs = &rk3568_vop_vp0_regs,
},
{
.id = 1,
.soc_id = 0x3568,
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp1_intr,
.regs = &rk3568_vop_vp1_regs,
},
{
.id = 2,
.soc_id = 0x3568,
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp2_intr,
.regs = &rk3568_vop_vp2_regs,
},
};
const struct vop2_layer_regs rk3568_vop_layer0_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 0)
};
const struct vop2_layer_regs rk3568_vop_layer1_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 4)
};
const struct vop2_layer_regs rk3568_vop_layer2_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 8)
};
const struct vop2_layer_regs rk3568_vop_layer3_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 12)
};
const struct vop2_layer_regs rk3568_vop_layer4_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 16)
};
const struct vop2_layer_regs rk3568_vop_layer5_regs = {
.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 20)
};
static const struct vop2_layer_data rk3568_vop_layers[] = {
{
.id = 0,
.regs = &rk3568_vop_layer0_regs,
},
{
.id = 1,
.regs = &rk3568_vop_layer1_regs,
},
{
.id = 2,
.regs = &rk3568_vop_layer2_regs,
},
{
.id = 3,
.regs = &rk3568_vop_layer3_regs,
},
{
.id = 4,
.regs = &rk3568_vop_layer4_regs,
},
{
.id = 5,
.regs = &rk3568_vop_layer5_regs,
},
};
static const struct vop_afbc rk3568_vop_afbc = {
.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
.format = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1f, 2),
.half_block_en = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 7),
.block_split_en = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 8),
.hdr_ptr = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
.pic_size = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
.pic_vir_width = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
.tile_num = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
.pic_offset = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
.dsp_offset = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
.rotate_90 = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
.rotate_270 = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
.xmirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
.ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
};
static const struct vop2_scl_regs rk3568_cluster_win_scl = {
.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
.yrgb_ver_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 14),
.yrgb_hor_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 12),
.bic_coe_sel = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 2),
};
static const struct vop2_scl_regs rk3568_esmart_win_scl = {
.scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 0x0),
.scale_yrgb_y = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 16),
.scale_cbcr_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_CBR, 0xffff, 0x0),
.scale_cbcr_y = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_CBR, 0xffff, 16),
.yrgb_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 0),
.yrgb_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 2),
.yrgb_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 4),
.yrgb_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 6),
.cbcr_hor_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 8),
.cbcr_hscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 10),
.cbcr_ver_scl_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 12),
.cbcr_vscl_filter_mode = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 14),
.bic_coe_sel = VOP_REG(RK3568_ESMART0_REGION0_SCL_CTRL, 0x3, 16),
.vsd_yrgb_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 8),
.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 9),
.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 10),
.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 11),
};
static const struct vop2_win_regs rk3568_area1_data = {
.enable = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 0),
.format = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1f, 1),
.rb_swap = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 14),
.act_info = VOP_REG(RK3568_ESMART0_REGION1_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3568_ESMART0_REGION1_DSP_INFO, 0x1fff1fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION1_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION1_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3568_ESMART0_REGION1_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 16),
};
static const struct vop2_win_regs rk3568_area2_data = {
.enable = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 0),
.format = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1f, 1),
.rb_swap = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 14),
.act_info = VOP_REG(RK3568_ESMART0_REGION2_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3568_ESMART0_REGION2_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION2_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION2_YRGB_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 16),
};
static const struct vop2_win_regs rk3568_area3_data = {
.enable = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 0),
.format = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1f, 1),
.rb_swap = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 14),
.act_info = VOP_REG(RK3568_ESMART0_REGION3_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3568_ESMART0_REGION3_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION3_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION3_YRGB_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 16),
};
static const struct vop2_win_regs *rk3568_area_data[] = {
&rk3568_area1_data,
&rk3568_area2_data,
&rk3568_area3_data
};
static const struct vop2_win_regs rk3568_cluster_win_data = {
.scl = &rk3568_cluster_win_scl,
.afbc = &rk3568_vop_afbc,
.gate = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
.enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1f, 1),
.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10),
};
static const struct vop2_win_regs rk3568_esmart_win_data = {
.scl = &rk3568_esmart_win_scl,
.enable = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0),
.format = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1f, 1),
.rb_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 14),
.act_info = VOP_REG(RK3568_ESMART0_REGION0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3568_ESMART0_REGION0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 16),
.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
.r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 10),
};
/*
* rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
* Every cluster can work as 4K win or split into two win.
* All win in cluster support AFBCD.
*
* Every esmart win and smart win support 4 Multi-region.
*
* Scale filter mode:
*
* * Cluster: bicubic for horizontal scale up, others use bilinear
* * ESmart:
* * nearest-neighbor/bilinear/bicubic for scale up
* * nearest-neighbor/bilinear/average for scale down
*
*
* @TODO describe the wind like cpu-map dt nodes;
*/
static const struct vop2_win_data rk3568_vop_win_data[] = {
{
.name = "Cluster0-win0",
.phys_id = 0,
.base = 0x00,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.layer_sel_id = 0,
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster_win_data,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.type = DRM_PLANE_TYPE_OVERLAY,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
},
{
.name = "Cluster0-win1",
.phys_id = 0,
.base = 0x80,
.layer_sel_id = -1,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster_win_data,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.type = DRM_PLANE_TYPE_OVERLAY,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
},
{
.name = "Cluster1-win0",
.phys_id = 1,
.base = 0x200,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.layer_sel_id = 1,
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
},
{
.name = "Cluster1-win1",
.phys_id = 1,
.layer_sel_id = -1,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.base = 0x280,
.supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
},
{
.name = "Esmart0-win0",
.phys_id = 2,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.base = 0x0,
.layer_sel_id = 2,
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_esmart_win_data,
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
{
.name = "Esmart1-win0",
.phys_id = 3,
.formats = formats_win_full_10bit,
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.base = 0x200,
.layer_sel_id = 6,
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_esmart_win_data,
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
{
.name = "Smart0-win0",
.phys_id = 4,
.base = 0x400,
.formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.layer_sel_id = 3,
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_esmart_win_data,
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
{
.name = "Smart1-win0",
.phys_id = 5,
.formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.base = 0x600,
.layer_sel_id = 7,
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_esmart_win_data,
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
};
static const struct vop_grf_ctrl rk3568_grf_ctrl = {
.grf_dclk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 3),
};
static const struct vop2_ctrl rk3568_vop_ctrl = {
.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
.ovl_cfg_done_port = VOP_REG(RK3568_OVL_LAYER_SEL, 0x3, 30),
.ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
.cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctrl = VOP_REG(RK3568_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
.edp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 3),
.mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
.mipi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 20),
.lvds0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
.lvds1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 24),
.bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 10),
.edp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 14),
.mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
.mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21),
.lvds0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
.lvds1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 25),
.lvds_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 0),
.lvds_dual_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
.lvds_dual_channel_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 2),
.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
.hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7),
.edp_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x3, 12),
.edp_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15),
.mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 16),
.mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 19),
.win_vp_id[0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
.win_vp_id[1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
.win_vp_id[2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),
.win_vp_id[3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
.win_vp_id[4] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
.win_vp_id[5] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
};
static const struct vop2_data rk3568_vop = {
.version = VOP_VERSION(0x40, 0x15),
.nr_vps = 3,
.nr_mixers = 5,
.max_input = { 4096, 2304 },
.max_output = { 4096, 2304 },
.ctrl = &rk3568_vop_ctrl,
.grf_ctrl = &rk3568_grf_ctrl,
.axi_intr = rk3568_vop_axi_intr,
.nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
.vp = rk3568_vop_video_ports,
.layer = rk3568_vop_layers,
.nr_layers = ARRAY_SIZE(rk3568_vop_layers),
.win = rk3568_vop_win_data,
.win_size = ARRAY_SIZE(rk3568_vop_win_data),
};
static const struct of_device_id vop2_dt_match[] = {
{ .compatible = "rockchip,rk3568-vop",
.data = &rk3568_vop },
{},
};
MODULE_DEVICE_TABLE(of, vop2_dt_match);
static int vop2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
if (!dev->of_node) {
DRM_DEV_ERROR(dev, "can't find vop2 devices\n");
return -ENODEV;
}
return component_add(dev, &vop2_component_ops);
}
static int vop2_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &vop2_component_ops);
return 0;
}
struct platform_driver vop2_platform_driver = {
.probe = vop2_probe,
.remove = vop2_remove,
.driver = {
.name = "rockchip-vop2",
.of_match_table = of_match_ptr(vop2_dt_match),
},
};

379
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1045,4 +1045,383 @@
#define RV1126_GRF_IOFUNC_CON3 0x1026c
/* rk3568 vop registers definition */
#define RK3568_GRF_VO_CON1 0x0364
/* System registers definition */
#define RK3568_REG_CFG_DONE 0x000
#define RK3568_VERSION_INFO 0x004
#define RK3568_DSP_IF_EN 0x028
#define RK3568_DSP_IF_CTRL 0x02c
#define RK3568_DSP_IF_POL 0x030
#define RK3568_VP0_LINE_FLAG 0x70
#define RK3568_VP1_LINE_FLAG 0x74
#define RK3568_VP2_LINE_FLAG 0x78
#define RK3568_SYS0_INT_EN 0x80
#define RK3568_SYS0_INT_CLR 0x84
#define RK3568_SYS0_INT_STATUS 0x88
#define RK3568_SYS1_INT_EN 0x90
#define RK3568_SYS1_INT_CLR 0x94
#define RK3568_SYS1_INT_STATUS 0x98
#define RK3568_VP0_INT_EN 0xA0
#define RK3568_VP0_INT_CLR 0xA4
#define RK3568_VP0_INT_STATUS 0xA8
#define RK3568_VP1_INT_EN 0xB0
#define RK3568_VP1_INT_CLR 0xB4
#define RK3568_VP1_INT_STATUS 0xB8
#define RK3568_VP2_INT_EN 0xC0
#define RK3568_VP2_INT_CLR 0xC4
#define RK3568_VP2_INT_STATUS 0xC8
/* Video Port registers definition */
#define RK3568_VP0_DSP_CTRL 0xC00
#define RK3568_VP0_MIPI_CTRL 0xC04
#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
#define RK3568_VP0_PRE_SCAN_HTIMING 0xC30
#define RK3568_VP0_POST_DSP_HACT_INFO 0xC34
#define RK3568_VP0_POST_DSP_VACT_INFO 0xC38
#define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C
#define RK3568_VP0_POST_SCL_CTRL 0xC40
#define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44
#define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48
#define RK3568_VP0_DSP_HACT_ST_END 0xC4C
#define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50
#define RK3568_VP0_DSP_VACT_ST_END 0xC54
#define RK3568_VP0_DSP_VS_ST_END_F1 0xC58
#define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C
#define RK3568_VP1_DSP_CTRL 0xD00
#define RK3568_VP1_MIPI_CTRL 0xD04
#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30
#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34
#define RK3568_VP1_POST_DSP_VACT_INFO 0xD38
#define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C
#define RK3568_VP1_POST_SCL_CTRL 0xD40
#define RK3568_VP1_DSP_HACT_INFO 0xD34
#define RK3568_VP1_DSP_VACT_INFO 0xD38
#define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44
#define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48
#define RK3568_VP1_DSP_HACT_ST_END 0xD4C
#define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50
#define RK3568_VP1_DSP_VACT_ST_END 0xD54
#define RK3568_VP1_DSP_VS_ST_END_F1 0xD58
#define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C
#define RK3568_VP2_DSP_CTRL 0xE00
#define RK3568_VP2_MIPI_CTRL 0xE04
#define RK3568_VP2_COLOR_BAR_CTRL 0xE08
#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30
#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34
#define RK3568_VP2_POST_DSP_VACT_INFO 0xE38
#define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C
#define RK3568_VP2_POST_SCL_CTRL 0xE40
#define RK3568_VP2_DSP_HACT_INFO 0xE34
#define RK3568_VP2_DSP_VACT_INFO 0xE38
#define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44
#define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48
#define RK3568_VP2_DSP_HACT_ST_END 0xE4C
#define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50
#define RK3568_VP2_DSP_VACT_ST_END 0xE54
#define RK3568_VP2_DSP_VS_ST_END_F1 0xE58
#define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C
/* Overlay registers definition */
#define RK3568_OVL_CTRL 0x600
#define RK3568_OVL_LAYER_SEL 0x604
#define RK3568_OVL_PORT_SEL 0x608
#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
#define RK3568_MIX0_DST_COLOR_CTRL 0x654
#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
#define RK3568_VP0_BG_MIX_CTRL 0x6E0
#define RK3568_VP1_BG_MIX_CTRL 0x6E4
#define RK3568_VP2_BG_MIX_CTRL 0x6E8
#define RK3568_CLUSTER_DLY_NUM 0x6F0
#define RK3568_SMART_DLY_NUM 0x6F8
/* Cluster0 register definition */
#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000
#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010
#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014
#define RK3568_CLUSTER0_WIN0_VIR 0x1018
#define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020
#define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024
#define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028
#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030
#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054
#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058
#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
#define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090
#define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094
#define RK3568_CLUSTER0_WIN1_VIR 0x1098
#define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0
#define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4
#define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8
#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0
#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4
#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8
#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC
#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0
#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4
#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8
#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC
#define RK3568_CLUSTER0_CTRL 0x1100
#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200
#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204
#define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210
#define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214
#define RK3568_CLUSTER1_WIN0_VIR 0x1218
#define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220
#define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224
#define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228
#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230
#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254
#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258
#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C
#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260
#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264
#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268
#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C
#define RK3568_CLUSTER1_WIN1_CTRL0 0x1280
#define RK3568_CLUSTER1_WIN1_CTRL1 0x1284
#define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290
#define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294
#define RK3568_CLUSTER1_WIN1_VIR 0x1298
#define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0
#define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4
#define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8
#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0
#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4
#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8
#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC
#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0
#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4
#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8
#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC
#define RK3568_CLUSTER1_CTRL 0x1300
/* Esmart register definition */
#define RK3568_ESMART0_CTRL0 0x1800
#define RK3568_ESMART0_CTRL1 0x1804
#define RK3568_ESMART0_REGION0_CTRL 0x1810
#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
#define RK3568_ESMART0_REGION0_CBR_MST 0x1818
#define RK3568_ESMART0_REGION0_VIR 0x181C
#define RK3568_ESMART0_REGION0_ACT_INFO 0x1820
#define RK3568_ESMART0_REGION0_DSP_INFO 0x1824
#define RK3568_ESMART0_REGION0_DSP_ST 0x1828
#define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830
#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834
#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838
#define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C
#define RK3568_ESMART0_REGION1_CTRL 0x1840
#define RK3568_ESMART0_REGION1_YRGB_MST 0x1844
#define RK3568_ESMART0_REGION1_CBR_MST 0x1848
#define RK3568_ESMART0_REGION1_VIR 0x184C
#define RK3568_ESMART0_REGION1_ACT_INFO 0x1850
#define RK3568_ESMART0_REGION1_DSP_INFO 0x1854
#define RK3568_ESMART0_REGION1_DSP_ST 0x1858
#define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860
#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864
#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868
#define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C
#define RK3568_ESMART0_REGION2_CTRL 0x1870
#define RK3568_ESMART0_REGION2_YRGB_MST 0x1874
#define RK3568_ESMART0_REGION2_CBR_MST 0x1878
#define RK3568_ESMART0_REGION2_VIR 0x187C
#define RK3568_ESMART0_REGION2_ACT_INFO 0x1880
#define RK3568_ESMART0_REGION2_DSP_INFO 0x1884
#define RK3568_ESMART0_REGION2_DSP_ST 0x1888
#define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890
#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894
#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898
#define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C
#define RK3568_ESMART0_REGION3_CTRL 0x18A0
#define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4
#define RK3568_ESMART0_REGION3_CBR_MST 0x18A8
#define RK3568_ESMART0_REGION3_VIR 0x18AC
#define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0
#define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4
#define RK3568_ESMART0_REGION3_DSP_ST 0x18B8
#define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0
#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4
#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8
#define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC
#define RK3568_ESMART1_CTRL0 0x1A00
#define RK3568_ESMART1_CTRL1 0x1A04
#define RK3568_ESMART1_REGION0_CTRL 0x1A10
#define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14
#define RK3568_ESMART1_REGION0_CBR_MST 0x1A18
#define RK3568_ESMART1_REGION0_VIR 0x1A1C
#define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20
#define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24
#define RK3568_ESMART1_REGION0_DSP_ST 0x1A28
#define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30
#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34
#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38
#define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C
#define RK3568_ESMART1_REGION1_CTRL 0x1A40
#define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44
#define RK3568_ESMART1_REGION1_CBR_MST 0x1A48
#define RK3568_ESMART1_REGION1_VIR 0x1A4C
#define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50
#define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54
#define RK3568_ESMART1_REGION1_DSP_ST 0x1A58
#define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60
#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64
#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68
#define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C
#define RK3568_ESMART1_REGION2_CTRL 0x1A70
#define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74
#define RK3568_ESMART1_REGION2_CBR_MST 0x1A78
#define RK3568_ESMART1_REGION2_VIR 0x1A7C
#define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80
#define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84
#define RK3568_ESMART1_REGION2_DSP_ST 0x1A88
#define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90
#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94
#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98
#define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C
#define RK3568_ESMART1_REGION3_CTRL 0x1AA0
#define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4
#define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8
#define RK3568_ESMART1_REGION3_VIR 0x1AAC
#define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0
#define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4
#define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8
#define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0
#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4
#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8
#define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC
#define RK3568_SMART0_CTRL0 0x1C00
#define RK3568_SMART0_CTRL1 0x1C04
#define RK3568_SMART0_REGION0_CTRL 0x1C10
#define RK3568_SMART0_REGION0_YRGB_MST 0x1C14
#define RK3568_SMART0_REGION0_CBR_MST 0x1C18
#define RK3568_SMART0_REGION0_VIR 0x1C1C
#define RK3568_SMART0_REGION0_ACT_INFO 0x1C20
#define RK3568_SMART0_REGION0_DSP_INFO 0x1C24
#define RK3568_SMART0_REGION0_DSP_ST 0x1C28
#define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30
#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34
#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38
#define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C
#define RK3568_SMART0_REGION1_CTRL 0x1C40
#define RK3568_SMART0_REGION1_YRGB_MST 0x1C44
#define RK3568_SMART0_REGION1_CBR_MST 0x1C48
#define RK3568_SMART0_REGION1_VIR 0x1C4C
#define RK3568_SMART0_REGION1_ACT_INFO 0x1C50
#define RK3568_SMART0_REGION1_DSP_INFO 0x1C54
#define RK3568_SMART0_REGION1_DSP_ST 0x1C58
#define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60
#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64
#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68
#define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C
#define RK3568_SMART0_REGION2_CTRL 0x1C70
#define RK3568_SMART0_REGION2_YRGB_MST 0x1C74
#define RK3568_SMART0_REGION2_CBR_MST 0x1C78
#define RK3568_SMART0_REGION2_VIR 0x1C7C
#define RK3568_SMART0_REGION2_ACT_INFO 0x1C80
#define RK3568_SMART0_REGION2_DSP_INFO 0x1C84
#define RK3568_SMART0_REGION2_DSP_ST 0x1C88
#define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90
#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94
#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98
#define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C
#define RK3568_SMART0_REGION3_CTRL 0x1CA0
#define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4
#define RK3568_SMART0_REGION3_CBR_MST 0x1CA8
#define RK3568_SMART0_REGION3_VIR 0x1CAC
#define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0
#define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4
#define RK3568_SMART0_REGION3_DSP_ST 0x1CB8
#define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0
#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4
#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8
#define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC
#define RK3568_SMART1_CTRL0 0x1E00
#define RK3568_SMART1_CTRL1 0x1E04
#define RK3568_SMART1_REGION0_CTRL 0x1E10
#define RK3568_SMART1_REGION0_YRGB_MST 0x1E14
#define RK3568_SMART1_REGION0_CBR_MST 0x1E18
#define RK3568_SMART1_REGION0_VIR 0x1E1C
#define RK3568_SMART1_REGION0_ACT_INFO 0x1E20
#define RK3568_SMART1_REGION0_DSP_INFO 0x1E24
#define RK3568_SMART1_REGION0_DSP_ST 0x1E28
#define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30
#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34
#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38
#define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C
#define RK3568_SMART1_REGION1_CTRL 0x1E40
#define RK3568_SMART1_REGION1_YRGB_MST 0x1E44
#define RK3568_SMART1_REGION1_CBR_MST 0x1E48
#define RK3568_SMART1_REGION1_VIR 0x1E4C
#define RK3568_SMART1_REGION1_ACT_INFO 0x1E50
#define RK3568_SMART1_REGION1_DSP_INFO 0x1E54
#define RK3568_SMART1_REGION1_DSP_ST 0x1E58
#define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60
#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64
#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68
#define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C
#define RK3568_SMART1_REGION2_CTRL 0x1E70
#define RK3568_SMART1_REGION2_YRGB_MST 0x1E74
#define RK3568_SMART1_REGION2_CBR_MST 0x1E78
#define RK3568_SMART1_REGION2_VIR 0x1E7C
#define RK3568_SMART1_REGION2_ACT_INFO 0x1E80
#define RK3568_SMART1_REGION2_DSP_INFO 0x1E84
#define RK3568_SMART1_REGION2_DSP_ST 0x1E88
#define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90
#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94
#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98
#define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C
#define RK3568_SMART1_REGION3_CTRL 0x1EA0
#define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4
#define RK3568_SMART1_REGION3_CBR_MST 0x1EA8
#define RK3568_SMART1_REGION3_VIR 0x1EAC
#define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0
#define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4
#define RK3568_SMART1_REGION3_DSP_ST 0x1EB8
#define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0
#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4
#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
/* HDR register definition */
#define RK3568_HDR_LUT_CTRL 0x2000
#define RK3568_HDR_LUT_MST 0x2004
#define RK3568_SDR2HDR_CTRL 0x2010
#define RK3568_HDR2SDR_CTRL 0x2020
#define RK3568_HDR2SDR_SRC_RANGE 0x2024
#define RK3568_HDR2SDR_NORMFACEETF 0x2028
#define RK3568_HDR2SDR_DST_RANGE 0x202C
#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
#define RK3568_HDR_EETF_OETF_Y0 0x203C
#define RK3568_HDR_SAT_Y0 0x20C0
#define RK3568_HDR_EOTF_OETF_Y0 0x20F0
#define RK3568_HDR_OETF_DX_POW1 0x2200
#define RK3568_HDR_OETF_XN1 0x2300
#endif /* _ROCKCHIP_VOP_REG_H */