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it66121 hdmi support

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This commit is contained in:
yzq
2013-01-26 15:54:28 +08:00
parent c216a73bf8
commit f02f265142
26 changed files with 8290 additions and 0 deletions
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8
arch/arm/mach-rk30/board-rk3066b-sdk.c
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@@ -1573,6 +1573,14 @@ static struct i2c_board_info __initdata i2c1_info[] = {
.platform_data = &tps65910_data,
},
#endif
#if defined(CONFIG_HDMI_CAT66121)
{
.type = "cat66121_hdmi",
.addr = 0x4c,
.flags = 0,
.irq = RK30_PIN1_PB7,
},
#endif
};
#endif

9
drivers/video/rockchip/hdmi/chips/Kconfig
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@@ -18,6 +18,15 @@ if HDMI_RK2928
source "drivers/video/rockchip/hdmi/chips/rk2928/Kconfig"
endif
config HDMI_CAT66121
bool "CAT66121 HDMI support"
help
Support cat66121 hdmi if you say y here
if HDMI_CAT66121
source "drivers/video/rockchip/hdmi/chips/cat66121/Kconfig"
endif
config HDMI_RK610
bool "RK610 HDMI support"
depends on MFD_RK610

1
drivers/video/rockchip/hdmi/chips/Makefile
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@@ -7,3 +7,4 @@ ccflags-$(CONFIG_HDMI_RK30_DEBUG) = -DDEBUG -DHDMI_DEBUG
obj-$(CONFIG_HDMI_RK30) += rk30/
obj-$(CONFIG_HDMI_RK2928) += rk2928/
obj-$(CONFIG_HDMI_RK610) += rk610/
obj-$(CONFIG_HDMI_CAT66121) += cat66121/

1
drivers/video/rockchip/hdmi/chips/cat66121/Kconfig Executable file
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@@ -0,0 +1 @@

7
drivers/video/rockchip/hdmi/chips/cat66121/Makefile Executable file
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@@ -0,0 +1,7 @@
obj-$(CONFIG_HDMI_CAT66121) += cat66121_hdmi.o \
cat66121_hdmi_hw.o \
hdmitx_sys.o \
hdmitx_hdcp.o \
hdmitx_input.o \
hdmitx_drv.o

340
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_hdmi.c Executable file
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@@ -0,0 +1,340 @@
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <linux/i2c.h>
#include "cat66121_hdmi.h"
struct cat66121_hdmi_pdata *cat66121_hdmi = NULL;
struct hdmi *hdmi=NULL;
extern struct rk_lcdc_device_driver * rk_get_lcdc_drv(char *name);
extern void hdmi_register_display_sysfs(struct hdmi *hdmi, struct device *parent);
extern void hdmi_unregister_display_sysfs(struct hdmi *hdmi);
int cat66121_hdmi_register_hdcp_callbacks(void (*hdcp_cb)(void),
void (*hdcp_irq_cb)(int status),
int (*hdcp_power_on_cb)(void),
void (*hdcp_power_off_cb)(void))
{
hdmi->hdcp_cb = hdcp_cb;
hdmi->hdcp_irq_cb = hdcp_irq_cb;
hdmi->hdcp_power_on_cb = hdcp_power_on_cb;
hdmi->hdcp_power_off_cb = hdcp_power_off_cb;
return HDMI_ERROR_SUCESS;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
static void hdmi_early_suspend(struct early_suspend *h)
{
hdmi_dbg(hdmi->dev, "hdmi enter early suspend pwr %d state %d\n", hdmi->pwr_mode, hdmi->state);
flush_delayed_work(&hdmi->delay_work);
mutex_lock(&hdmi->enable_mutex);
hdmi->suspend = 1;
if(!hdmi->enable) {
mutex_unlock(&hdmi->enable_mutex);
return;
}
#ifdef HDMI_USE_IRQ
if(hdmi->irq)
disable_irq(hdmi->irq);
#endif
mutex_unlock(&hdmi->enable_mutex);
hdmi->command = HDMI_CONFIG_ENABLE;
init_completion(&hdmi->complete);
hdmi->wait = 1;
queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, 0);
wait_for_completion_interruptible_timeout(&hdmi->complete,
msecs_to_jiffies(5000));
flush_delayed_work(&hdmi->delay_work);
return;
}
static void hdmi_early_resume(struct early_suspend *h)
{
hdmi_dbg(hdmi->dev, "hdmi exit early resume\n");
mutex_lock(&hdmi->enable_mutex);
hdmi->suspend = 0;
#ifdef HDMI_USE_IRQ
if(hdmi->enable && hdmi->irq) {
enable_irq(hdmi->irq);
}
#else
queue_delayed_work(cat66121_hdmi->workqueue, &cat66121_hdmi->delay_work, 100);
#endif
queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10));
mutex_unlock(&hdmi->enable_mutex);
return;
}
#endif
static void cat66121_irq_work_func(struct work_struct *work)
{
if(hdmi->suspend == 0) {
if(hdmi->enable == 1) {
cat66121_hdmi_interrupt();
if(hdmi->hdcp_irq_cb)
hdmi->hdcp_irq_cb(0);
}
#ifndef HDMI_USE_IRQ
queue_delayed_work(cat66121_hdmi->workqueue, &cat66121_hdmi->delay_work, 50);
#endif
}
}
#ifdef HDMI_USE_IRQ
static irqreturn_t cat66121_irq(int irq, void *dev_id)
{
printk(KERN_INFO "cat66121 irq triggered.\n");
schedule_work(&cat66121_hdmi->irq_work);
return IRQ_HANDLED;
}
#endif
static int rk610_read_p0_reg(struct i2c_client *client, char reg, char *val)
{
return i2c_master_reg8_recv(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;
}
static int rk610_write_p0_reg(struct i2c_client *client, char reg, char *val)
{
return i2c_master_reg8_send(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;
}
static ssize_t rk610_show_reg_attrs(struct device *dev,
struct device_attribute *attr,
char *buf)
{
int i,size=0;
char val;
struct i2c_client *client=cat66121_hdmi->client;
for(i=0;i<256;i++)
{
rk610_read_p0_reg(client, i, &val);
if(i%16==0)
size += sprintf(buf+size,"\n>>>rk610_hdmi %x:",i);
size += sprintf(buf+size," %2x",val);
}
return size;
}
static ssize_t rk610_store_reg_attrs(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct i2c_client *client=NULL;
static char val=0,reg=0;
client = cat66121_hdmi->client;
printk("/**********rk610 reg config******/");
sscanf(buf, "%x%x", &val,&reg);
printk("reg=%x val=%x\n",reg,val);
rk610_write_p0_reg(client, reg, &val);
printk("val=%x\n",val);
return size;
}
static struct device_attribute rk610_attrs[] = {
__ATTR(reg_ctl, 0777,rk610_show_reg_attrs,rk610_store_reg_attrs),
};
static int cat66121_hdmi_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
{
int rc = 0;
cat66121_hdmi = kzalloc(sizeof(struct cat66121_hdmi_pdata), GFP_KERNEL);
if(!cat66121_hdmi)
{
dev_err(&client->dev, "no memory for state\n");
return -ENOMEM;
}
cat66121_hdmi->client = client;
i2c_set_clientdata(client, cat66121_hdmi);
hdmi = kmalloc(sizeof(struct hdmi), GFP_KERNEL);
if(!hdmi)
{
dev_err(&client->dev, "cat66121 hdmi kmalloc fail!");
goto err_kzalloc_hdmi;
}
memset(hdmi, 0, sizeof(struct hdmi));
hdmi->dev = &client->dev;
if(HDMI_SOURCE_DEFAULT == HDMI_SOURCE_LCDC0)
hdmi->lcdc = rk_get_lcdc_drv("lcdc0");
else
hdmi->lcdc = rk_get_lcdc_drv("lcdc1");
if(hdmi->lcdc == NULL)
{
dev_err(hdmi->dev, "can not connect to video source lcdc\n");
rc = -ENXIO;
goto err_request_lcdc;
}
hdmi->xscale = 100;
hdmi->yscale = 100;
hdmi->insert = cat66121_hdmi_sys_insert;
hdmi->remove = cat66121_hdmi_sys_remove;
hdmi->control_output = cat66121_hdmi_sys_enalbe_output;
hdmi->config_video = cat66121_hdmi_sys_config_video;
hdmi->config_audio = cat66121_hdmi_sys_config_audio;
hdmi->detect_hotplug = cat66121_hdmi_sys_detect_hpd;
hdmi->read_edid = cat66121_hdmi_sys_read_edid;
hdmi_sys_init();
hdmi->workqueue = create_singlethread_workqueue("hdmi");
INIT_DELAYED_WORK(&(hdmi->delay_work), hdmi_work);
#ifdef CONFIG_HAS_EARLYSUSPEND
hdmi->early_suspend.suspend = hdmi_early_suspend;
hdmi->early_suspend.resume = hdmi_early_resume;
hdmi->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 10;
register_early_suspend(&hdmi->early_suspend);
#endif
hdmi_register_display_sysfs(hdmi, NULL);
#ifdef CONFIG_SWITCH
hdmi->switch_hdmi.name="hdmi";
switch_dev_register(&(hdmi->switch_hdmi));
#endif
spin_lock_init(&hdmi->irq_lock);
mutex_init(&hdmi->enable_mutex);
cat66121_hdmi_sys_init();
rc = gpio_request(client->irq, "cat66121 rst");
if (rc != 0) {
gpio_free(client->irq);
printk("goodix power error\n");
return -EIO;
}
gpio_direction_output(client->irq, GPIO_HIGH);
gpio_set_value(client->irq, GPIO_HIGH);
msleep(10);
gpio_set_value(client->irq, GPIO_LOW);
msleep(200);
gpio_set_value(client->irq, GPIO_HIGH);
#ifdef HDMI_USE_IRQ
if(client->irq != INVALID_GPIO) {
INIT_WORK(&cat66121_hdmi->irq_work, cat66121_irq_work_func);
schedule_work(&cat66121_hdmi->irq_work);
if((rc = gpio_request(client->irq, "hdmi gpio")) < 0)
{
dev_err(&client->dev, "fail to request gpio %d\n", client->irq);
goto err_request_lcdc;
}
hdmi->irq = gpio_to_irq(client->irq);
cat66121_hdmi->gpio = client->irq;
gpio_pull_updown(client->irq, GPIOPullUp);
gpio_direction_input(client->irq);
if((rc = request_irq(hdmi->irq, cat66121_irq, IRQF_TRIGGER_RISING, NULL, hdmi)) < 0)
{
dev_err(&client->dev, "fail to request hdmi irq\n");
goto err_request_irq;
}
}
else
#else
{
cat66121_hdmi->workqueue = create_singlethread_workqueue("cat66121 irq");
INIT_DELAYED_WORK(&(cat66121_hdmi->delay_work), cat66121_irq_work_func);
cat66121_irq_work_func(NULL);
}
#endif
device_create_file(&(client->dev), &rk610_attrs[0]);
dev_info(&client->dev, "cat66121 hdmi i2c probe ok\n");
return 0;
err_request_irq:
gpio_free(client->irq);
err_request_lcdc:
kfree(hdmi);
hdmi = NULL;
err_kzalloc_hdmi:
kfree(cat66121_hdmi);
cat66121_hdmi = NULL;
dev_err(&client->dev, "cat66121 hdmi probe error\n");
return rc;
}
static int __devexit cat66121_hdmi_i2c_remove(struct i2c_client *client)
{
hdmi_dbg(hdmi->dev, "%s\n", __func__);
if(hdmi) {
mutex_lock(&hdmi->enable_mutex);
if(!hdmi->suspend && hdmi->enable && hdmi->irq)
disable_irq(hdmi->irq);
mutex_unlock(&hdmi->enable_mutex);
if(hdmi->irq)
free_irq(hdmi->irq, NULL);
flush_workqueue(hdmi->workqueue);
destroy_workqueue(hdmi->workqueue);
#ifdef CONFIG_SWITCH
switch_dev_unregister(&(hdmi->switch_hdmi));
#endif
hdmi_unregister_display_sysfs(hdmi);
#ifdef CONFIG_HAS_EARLYSUSPEND
unregister_early_suspend(&hdmi->early_suspend);
#endif
fb_destroy_modelist(&hdmi->edid.modelist);
if(hdmi->edid.audio)
kfree(hdmi->edid.audio);
if(hdmi->edid.specs)
{
if(hdmi->edid.specs->modedb)
kfree(hdmi->edid.specs->modedb);
kfree(hdmi->edid.specs);
}
kfree(hdmi);
hdmi = NULL;
}
return 0;
}
static void cat66121_hdmi_i2c_shutdown(struct i2c_client *client)
{
if(hdmi) {
#ifdef CONFIG_HAS_EARLYSUSPEND
unregister_early_suspend(&hdmi->early_suspend);
#endif
}
printk(KERN_INFO "cat66121 hdmi shut down.\n");
}
static const struct i2c_device_id cat66121_hdmi_id[] = {
{ "cat66121_hdmi", 0 },
{ }
};
static struct i2c_driver cat66121_hdmi_i2c_driver = {
.driver = {
.name = "cat66121_hdmi",
.owner = THIS_MODULE,
},
.probe = cat66121_hdmi_i2c_probe,
.remove = cat66121_hdmi_i2c_remove,
.shutdown = cat66121_hdmi_i2c_shutdown,
.id_table = cat66121_hdmi_id,
};
static int __init cat66121_hdmi_init(void)
{
return i2c_add_driver(&cat66121_hdmi_i2c_driver);
}
static void __exit cat66121_hdmi_exit(void)
{
i2c_del_driver(&cat66121_hdmi_i2c_driver);
}
module_init(cat66121_hdmi_init);
//fs_initcall(cat66121_init);
module_exit(cat66121_hdmi_exit);

34
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_hdmi.h Executable file
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@@ -0,0 +1,34 @@
#ifndef __cat66121_HDMI_H__
#define __cat66121_HDMI_H__
#include "../../rk_hdmi.h"
#define HDMI_SOURCE_DEFAULT HDMI_SOURCE_LCDC0
//#define HDMI_USE_IRQ
struct cat66121_hdmi_pdata {
int gpio;
struct i2c_client *client;
struct delayed_work delay_work;
#ifdef HDMI_USE_IRQ
struct work_struct irq_work;
#else
struct workqueue_struct *workqueue;
#endif
};
extern struct cat66121_hdmi_pdata *cat66121_hdmi;
extern int cat66121_hdmi_sys_init(void);
extern void cat66121_hdmi_interrupt(void);
extern int cat66121_hdmi_sys_detect_hpd(void);
extern int cat66121_hdmi_sys_insert(void);
extern int cat66121_hdmi_sys_remove(void);
extern int cat66121_hdmi_sys_read_edid(int block, unsigned char *buff);
extern int cat66121_hdmi_sys_config_video(struct hdmi_video_para *vpara);
extern int cat66121_hdmi_sys_config_audio(struct hdmi_audio *audio);
extern void cat66121_hdmi_sys_enalbe_output(int enable);
extern int cat66121_hdmi_register_hdcp_callbacks(void (*hdcp_cb)(void),
void (*hdcp_irq_cb)(int status),
int (*hdcp_power_on_cb)(void),
void (*hdcp_power_off_cb)(void));
#endif

236
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_hdmi_hw.c Executable file
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@@ -0,0 +1,236 @@
#include <linux/delay.h>
#include "cat66121_hdmi.h"
#include "cat66121_hdmi_hw.h"
#include <asm/atomic.h>
#include <mach/io.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#define HDMITX_INPUT_SIGNAL_TYPE 0 // for default(Sync Sep Mode)
#define INPUT_SPDIF_ENABLE 0
extern int CAT66121_Interrupt_Process(void);
/*******************************
* Global Data
******************************/
static _XDATA AVI_InfoFrame AviInfo;
static _XDATA Audio_InfoFrame AudioInfo;
static unsigned long VideoPixelClock;
static unsigned int pixelrep;
/* I2C read/write funcs */
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr)
{
struct i2c_msg msgs[2];
SYS_STATUS ret = -1;
BYTE buf[1];
buf[0] = RegAddr;
/* Write device addr fisrt */
msgs[0].addr = cat66121_hdmi->client->addr;
msgs[0].flags = !I2C_M_RD;
msgs[0].len = 1;
msgs[0].buf = &buf[0];
msgs[0].scl_rate= 100*1000;
/* Then, begin to read data */
msgs[1].addr = cat66121_hdmi->client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 1;
msgs[1].buf = &buf[0];
msgs[1].scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);
if(ret != 2)
printk("I2C transfer Error! ret = %d\n", ret);
//ErrorF("Reg%02xH: 0x%02x\n", RegAddr, buf[0]);
return buf[0];
}
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr, BYTE data)
{
struct i2c_msg msg;
SYS_STATUS ret = -1;
BYTE buf[2];
buf[0] = RegAddr;
buf[1] = data;
msg.addr = cat66121_hdmi->client->addr;
msg.flags = !I2C_M_RD;
msg.len = 2;
msg.buf = buf;
msg.scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);
if(ret != 1)
printk("I2C transfer Error!\n");
return ret;
}
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)
{
struct i2c_msg msgs[2];
SYS_STATUS ret = -1;
pData[0] = RegAddr;
msgs[0].addr = cat66121_hdmi->client->addr;
msgs[0].flags = !I2C_M_RD;
msgs[0].len = 1;
msgs[0].buf = &pData[0];
msgs[0].scl_rate= 100*1000;
msgs[1].addr = cat66121_hdmi->client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = N;
msgs[1].buf = pData;
msgs[1].scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);
if(ret != 2)
printk("I2C transfer Error! ret = %d\n", ret);
return ret;
}
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)
{
struct i2c_msg msg;
SYS_STATUS ret = -1;
BYTE buf[N + 1];
buf[0] = RegAddr;
memcpy(&buf[1], pData, N);
msg.addr = cat66121_hdmi->client->addr;
msg.flags = !I2C_M_RD;
msg.len = N + 1;
msg.buf = buf; // gModify.Exp."Include RegAddr"
msg.scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);
if(ret != 1)
printk("I2C transfer Error! ret = %d\n", ret);
return ret;
}
SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value)
{
BYTE Temp;
if( Mask != 0xFF )
{
Temp=HDMITX_ReadI2C_Byte(Reg);
Temp&=(~Mask);
Temp|=Value&Mask;
}
else
{
Temp=Value;
}
return HDMITX_WriteI2C_Byte(Reg,Temp);
}
int cat66121_hdmi_sys_init(void)
{
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME, GPIO0C_GPIO0C1);
if (gpio_request(RK30_PIN0_PC1, NULL)) {
printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
return -1;
}
gpio_direction_output(RK30_PIN0_PC1, GPIO_LOW);
gpio_set_value(RK30_PIN0_PC1, GPIO_LOW);
msleep(200);
gpio_set_value(RK30_PIN0_PC1, GPIO_HIGH);
msleep(200);
mdelay(5);
VideoPixelClock = 0;
pixelrep = 0;
InitHDMITX_Variable();
InitHDMITX();
msleep(100);
return HDMI_ERROR_SUCESS;
}
void cat66121_hdmi_interrupt()
{
char interrupt = 0;
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
if(hdmi->state == HDMI_SLEEP)
hdmi->state = WAIT_HOTPLUG;
queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10));
}
int cat66121_hdmi_sys_detect_hpd(void)
{
char hdmi_status = 0;
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
// BYTE sysstat;
//sysstat = HDMITX_ReadI2C_Byte(REG_SYS_STATUS) ;
//*hpdstatus = ((sysstat & B_HPDETECT) == B_HPDETECT)?TRUE:FALSE ;
hdmi_status = HDMITX_DevLoopProc();
;
return HDMI_HPD_ACTIVED;
if(hdmi_status)
return HDMI_HPD_ACTIVED;
else
return HDMI_HPD_REMOVED;
}
int cat66121_hdmi_sys_read_edid(int block, unsigned char *buff)
{
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
return (getHDMITX_EDIDBlock(block, buff) == TRUE)?HDMI_ERROR_SUCESS:HDMI_ERROR_FALSE;
}
static void cat66121_sys_config_avi(int VIC, int bOutputColorMode, int aspec, int Colorimetry, int pixelrep)
{
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
// AVI_InfoFrame AviInfo;
}
int cat66121_hdmi_sys_config_video(struct hdmi_video_para *vpara)
{
printk( "[%s]\n", __FUNCTION__);
printk( "[%s]\n", __FUNCTION__);
HDMITX_ChangeDisplayOption(vpara->vic,HDMI_RGB444) ;
return HDMI_ERROR_SUCESS;
}
static void cat66121_hdmi_config_aai(void)
{
printk( "[%s]\n", __FUNCTION__);
}
int cat66121_hdmi_sys_config_audio(struct hdmi_audio *audio)
{
printk( "[%s]\n", __FUNCTION__);
return HDMI_ERROR_SUCESS;
}
void cat66121_hdmi_sys_enalbe_output(int enable)
{
printk( "[%s]\n", __FUNCTION__);
}
int cat66121_hdmi_sys_insert(void)
{
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
printk( "[%s]\n", __FUNCTION__);
return 0;
}
int cat66121_hdmi_sys_remove(void)
{
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
// printk( "[%s]\n", __FUNCTION__);
return 0;
}

260
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_hdmi_hw.h Executable file
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@@ -0,0 +1,260 @@
#ifndef _CAT6611_HDMI_HW_H
#define _CAT6611_HDMI_HW_H
#include "typedef.h"
#include "hdmitx_drv.h"
#include "hdmitx_sys.h"
#define CAT6611_SCL_RATE 100 * 1000
#define I2S 0
#define SPDIF 1
#ifndef I2S_FORMAT
#define I2S_FORMAT 0x01 // 32bit audio
#endif
#ifndef INPUT_SAMPLE_FREQ
#define INPUT_SAMPLE_FREQ AUDFS_48KHz
#endif //INPUT_SAMPLE_FREQ
#ifndef INPUT_SAMPLE_FREQ_HZ
#define INPUT_SAMPLE_FREQ_HZ 48000L
#endif //INPUT_SAMPLE_FREQ_HZ
#ifndef OUTPUT_CHANNEL
#define OUTPUT_CHANNEL 2
#endif //OUTPUT_CHANNEL
#ifndef CNOFIG_INPUT_AUDIO_TYPE
#define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM
// #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM
// #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR
#endif //CNOFIG_INPUT_AUDIO_TYPE
#ifndef CONFIG_INPUT_AUDIO_SPDIF
#define CONFIG_INPUT_AUDIO_SPDIF I2S
// #define CONFIG_INPUT_AUDIO_SPDIF SPDIF
#endif //CONFIG_INPUT_AUDIO_SPDIF
#ifndef INPUT_SIGNAL_TYPE
#define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate
#endif
////////////////////////////////////////////////////////////////////////////////
// Internal Data Type
////////////////////////////////////////////////////////////////////////////////
typedef enum tagHDMI_Video_Type {
HDMI_Unkown = 0 ,
HDMI_640x480p60 = 1 ,
HDMI_480p60,
HDMI_480p60_16x9,
HDMI_720p60,
HDMI_1080i60,
HDMI_480i60,
HDMI_480i60_16x9,
HDMI_1080p60 = 16,
HDMI_576p50,
HDMI_576p50_16x9,
HDMI_720p50,
HDMI_1080i50,
HDMI_576i50,
HDMI_576i50_16x9,
HDMI_1080p50 = 31,
HDMI_1080p24,
HDMI_1080p25,
HDMI_1080p30,
HDMI_720p30 = 61,
} HDMI_Video_Type ;
typedef enum tagHDMI_Aspec {
HDMI_4x3 ,
HDMI_16x9
} HDMI_Aspec;
typedef enum tagHDMI_OutputColorMode {
HDMI_RGB444,
HDMI_YUV444,
HDMI_YUV422
} HDMI_OutputColorMode ;
typedef enum tagHDMI_Colorimetry {
HDMI_ITU601,
HDMI_ITU709
} HDMI_Colorimetry ;
struct VideoTiming {
ULONG VideoPixelClock ;
BYTE VIC ;
BYTE pixelrep ;
BYTE outputVideoMode ;
} ;
typedef enum _TXVideo_State_Type {
TXVSTATE_Unplug = 0,
TXVSTATE_HPD,
TXVSTATE_WaitForMode,
TXVSTATE_WaitForVStable,
TXVSTATE_VideoInit,
TXVSTATE_VideoSetup,
TXVSTATE_VideoOn,
TXVSTATE_Reserved
} TXVideo_State_Type ;
typedef enum _TXAudio_State_Type {
TXASTATE_AudioOff = 0,
TXASTATE_AudioPrepare,
TXASTATE_AudioOn,
TXASTATE_AudioFIFOFail,
TXASTATE_Reserved
} TXAudio_State_Type ;
/////////////////////////////////////////
// RX Capability.
/////////////////////////////////////////
typedef struct {
BYTE b16bit:1 ;
BYTE b20bit:1 ;
BYTE b24bit:1 ;
BYTE Rsrv:5 ;
} LPCM_BitWidth ;
typedef enum {
AUD_RESERVED_0 = 0 ,
AUD_LPCM,
AUD_AC3,
AUD_MPEG1,
AUD_MP3,
AUD_MPEG2,
AUD_AAC,
AUD_DTS,
AUD_ATRAC,
AUD_ONE_BIT_AUDIO,
AUD_DOLBY_DIGITAL_PLUS,
AUD_DTS_HD,
AUD_MAT_MLP,
AUD_DST,
AUD_WMA_PRO,
AUD_RESERVED_15
} AUDIO_FORMAT_CODE ;
typedef union {
struct {
BYTE channel:3 ;
BYTE AudioFormatCode:4 ;
BYTE Rsrv1:1 ;
BYTE b32KHz:1 ;
BYTE b44_1KHz:1 ;
BYTE b48KHz:1 ;
BYTE b88_2KHz:1 ;
BYTE b96KHz:1 ;
BYTE b176_4KHz:1 ;
BYTE b192KHz:1 ;
BYTE Rsrv2:1 ;
BYTE ucCode ;
} s ;
BYTE uc[3] ;
} AUDDESCRIPTOR ;
typedef union {
struct {
BYTE FL_FR:1 ;
BYTE LFE:1 ;
BYTE FC:1 ;
BYTE RL_RR:1 ;
BYTE RC:1 ;
BYTE FLC_FRC:1 ;
BYTE RLC_RRC:1 ;
BYTE Reserve:1 ;
BYTE Unuse[2] ;
} s ;
BYTE uc[3] ;
} SPK_ALLOC ;
#define CEA_SUPPORT_UNDERSCAN (1<<7)
#define CEA_SUPPORT_AUDIO (1<<6)
#define CEA_SUPPORT_YUV444 (1<<5)
#define CEA_SUPPORT_YUV422 (1<<4)
#define CEA_NATIVE_MASK 0xF
#define HDMI_DC_SUPPORT_AI (1<<7)
#define HDMI_DC_SUPPORT_48 (1<<6)
#define HDMI_DC_SUPPORT_36 (1<<5)
#define HDMI_DC_SUPPORT_30 (1<<4)
#define HDMI_DC_SUPPORT_Y444 (1<<3)
#define HDMI_DC_SUPPORT_DVI_DUAL 1
typedef union _tag_DCSUPPORT {
struct {
BYTE DVI_Dual:1 ;
BYTE Rsvd:2 ;
BYTE DC_Y444:1 ;
BYTE DC_30Bit:1 ;
BYTE DC_36Bit:1 ;
BYTE DC_48Bit:1 ;
BYTE SUPPORT_AI:1 ;
} info ;
BYTE uc ;
} DCSUPPORT ;
typedef union _LATENCY_SUPPORT{
struct {
BYTE Rsvd:6 ;
BYTE I_Latency_Present:1 ;
BYTE Latency_Present:1 ;
} info ;
BYTE uc ;
} LATENCY_SUPPORT ;
#define HDMI_IEEEOUI 0x0c03
#define MAX_VODMODE_COUNT 32
#define MAX_AUDDES_COUNT 4
typedef struct _RX_CAP{
BYTE VideoMode ;
BYTE NativeVDOMode ;
BYTE VDOMode[8] ;
BYTE AUDDesCount ;
AUDDESCRIPTOR AUDDes[MAX_AUDDES_COUNT] ;
BYTE PA[2] ;
ULONG IEEEOUI ;
DCSUPPORT dc ;
BYTE MaxTMDSClock ;
LATENCY_SUPPORT lsupport ;
SPK_ALLOC SpeakerAllocBlk ;
BYTE ValidCEA:1 ;
BYTE ValidHDMI:1 ;
BYTE Valid3D:1 ;
} RX_CAP ;
///////////////////////////////////////////////////////////////////////
// Output Mode Type
///////////////////////////////////////////////////////////////////////
#define RES_ASPEC_4x3 0
#define RES_ASPEC_16x9 1
#define F_MODE_REPT_NO 0
#define F_MODE_REPT_TWICE 1
#define F_MODE_REPT_QUATRO 3
#define F_MODE_CSC_ITU601 0
#define F_MODE_CSC_ITU709 1
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);
void InitHDMITX_Variable();
void HDMITX_ChangeDisplayOption(HDMI_Video_Type VideoMode, HDMI_OutputColorMode OutputColorMode);
void HDMITX_SetOutput();
int HDMITX_DevLoopProc();
void ConfigfHdmiVendorSpecificInfoFrame(BYTE _3D_Stru);
void HDMITX_ChangeAudioOption(BYTE Option, BYTE channelNum, BYTE AudioFs);
void HDMITX_SetAudioOutput();
void HDMITX_ChangeColorDepth(BYTE colorDepth);
#endif

217
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_sys.c Normal file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file >cat66121_sys.c<
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2009/08/24
// @fileversion: cat66121_SAMPLEINTERFACE_1.12
//******************************************/
///////////////////////////////////////////////////////////////////////////////
// This is the sample program for cat66121 driver usage.
///////////////////////////////////////////////////////////////////////////////
#include "hdmitx.h"
#include "hdmitx_sys.h"
#include "cat66121_hdmi.h"
#if 0
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);
#endif
/* I2C read/write funcs */
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr)
{
struct i2c_msg msgs[2];
SYS_STATUS ret = -1;
BYTE buf[1];
buf[0] = RegAddr;
/* Write device addr fisrt */
msgs[0].addr = cat66121_hdmi->client->addr;
msgs[0].flags = !I2C_M_RD;
msgs[0].len = 1;
msgs[0].buf = &buf[0];
msgs[0].scl_rate= 100*1000;
/* Then, begin to read data */
msgs[1].addr = cat66121_hdmi->client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 1;
msgs[1].buf = &buf[0];
msgs[1].scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);
if(ret != 2)
printk("I2C transfer Error! ret = %d\n", ret);
//ErrorF("Reg%02xH: 0x%02x\n", RegAddr, buf[0]);
return buf[0];
}
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr, BYTE data)
{
struct i2c_msg msg;
SYS_STATUS ret = -1;
BYTE buf[2];
buf[0] = RegAddr;
buf[1] = data;
msg.addr = cat66121_hdmi->client->addr;
msg.flags = !I2C_M_RD;
msg.len = 2;
msg.buf = buf;
msg.scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);
if(ret != 1)
printk("I2C transfer Error!\n");
return ret;
}
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)
{
struct i2c_msg msgs[2];
SYS_STATUS ret = -1;
pData[0] = RegAddr;
msgs[0].addr = cat66121_hdmi->client->addr;
msgs[0].flags = !I2C_M_RD;
msgs[0].len = 1;
msgs[0].buf = &pData[0];
msgs[0].scl_rate= 100*1000;
msgs[1].addr = cat66121_hdmi->client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = N;
msgs[1].buf = pData;
msgs[1].scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, msgs, 2);
if(ret != 2)
printk("I2C transfer Error! ret = %d\n", ret);
return ret;
}
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr, BYTE *pData, int N)
{
struct i2c_msg msg;
SYS_STATUS ret = -1;
BYTE buf[N + 1];
buf[0] = RegAddr;
memcpy(&buf[1], pData, N);
msg.addr = cat66121_hdmi->client->addr;
msg.flags = !I2C_M_RD;
msg.len = N + 1;
msg.buf = buf; // gModify.Exp."Include RegAddr"
msg.scl_rate= 100*1000;
ret = i2c_transfer(cat66121_hdmi->client->adapter, &msg, 1);
if(ret != 1)
printk("I2C transfer Error! ret = %d\n", ret);
return ret;
}
static int cat66121_hdmi_i2c_read_reg(char reg, char *val)
{
if(i2c_master_reg8_recv(cat66121_hdmi->client, reg, val, 1, 100*1000) > 0)
return 0;
else {
printk("[%s] reg %02x error\n", __FUNCTION__, reg);
return -EINVAL;
}
}
/*******************************
* Global Data
******************************/
/*******************************
* Functions
******************************/
int cat66121_detect_device(void)
{
printk(">>>%s \n",__func__);
return 0;
}
int cat66121_sys_init(struct hdmi *hdmi)
{
printk(">>>%s \n",__func__);
InitHDMITX_Variable();
InitHDMITX();
HDMITX_ChangeDisplayOption(HDMI_720p60,HDMI_RGB444) ;
HDMITX_DevLoopProc();
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_unplug(struct hdmi *hdmi)
{
printk(">>>%s \n",__func__);
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_detect_hpd(struct hdmi *hdmi, int *hpdstatus)
{
printk(">>>%s \n",__func__);
*hpdstatus = TRUE;
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_detect_sink(struct hdmi *hdmi, int *sink_status)
{
printk(">>>%s \n",__func__);
*sink_status = TRUE;
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
{
printk(">>>%s \n",__func__);
return HDMI_ERROR_SUCESS;
}
static void cat66121_sys_config_avi(int VIC, int bOutputColorMode, int aspec, int Colorimetry, int pixelrep)
{
}
int cat66121_sys_config_video(struct hdmi *hdmi, int vic, int input_color, int output_color)
{
printk(">>>%s \n",__func__);
HDMITX_DevLoopProc();
return HDMI_ERROR_SUCESS ;
}
static void cat66121_sys_config_aai(void)
{
printk(">>>%s \n",__func__);
}
int cat66121_sys_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
{
printk(">>>%s \n",__func__);
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_config_hdcp(struct hdmi *hdmi, int enable)
{
printk(">>>%s \n",__func__);
return HDMI_ERROR_SUCESS;
}
int cat66121_sys_enalbe_output(struct hdmi *hdmi, int enable)
{
printk(">>>%s \n",__func__);
return HDMI_ERROR_SUCESS;
}

164
drivers/video/rockchip/hdmi/chips/cat66121/cat66121_sys.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file >cat66121_sys.h<
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2009/08/24
// @fileversion: cat66121_SAMPLEINTERFACE_1.12
//******************************************/
#ifndef _CAT66121_SYS_H_
#define _CAT66121_SYS_H_
////////////////////////////////////////////////////////////////////////////////
// Internal Data Type
////////////////////////////////////////////////////////////////////////////////
typedef enum tagHDMI_Video_Type {
HDMI_Unkown = 0 ,
HDMI_640x480p60 = 1 ,
HDMI_480p60,
HDMI_480p60_16x9,
HDMI_720p60,
HDMI_1080i60,
HDMI_480i60,
HDMI_480i60_16x9,
HDMI_1080p60 = 16,
HDMI_576p50,
HDMI_576p50_16x9,
HDMI_720p50,
HDMI_1080i50,
HDMI_576i50,
HDMI_576i50_16x9,
HDMI_1080p50 = 31,
HDMI_1080p24,
HDMI_1080p25,
HDMI_1080p30,
} HDMI_Video_Type ;
typedef enum tagHDMI_Aspec {
HDMI_4x3 ,
HDMI_16x9
} HDMI_Aspec;
typedef enum tagHDMI_OutputColorMode {
HDMI_RGB444,
HDMI_YUV444,
HDMI_YUV422
} HDMI_OutputColorMode ;
typedef enum tagHDMI_Colorimetry {
HDMI_ITU601,
HDMI_ITU709
} HDMI_Colorimetry ;
typedef enum tagMODE_ID{
CEA_640x480p60,
CEA_720x480p60,
CEA_1280x720p60,
CEA_1920x1080i60,
CEA_720x480i60,
CEA_720x240p60,
CEA_1440x480i60,
CEA_1440x240p60,
CEA_2880x480i60,
CEA_2880x240p60,
CEA_1440x480p60,
CEA_1920x1080p60,
CEA_720x576p50,
CEA_1280x720p50,
CEA_1920x1080i50,
CEA_720x576i50,
CEA_1440x576i50,
CEA_720x288p50,
CEA_1440x288p50,
CEA_2880x576i50,
CEA_2880x288p50,
CEA_1440x576p50,
CEA_1920x1080p50,
CEA_1920x1080p24,
CEA_1920x1080p25,
CEA_1920x1080p30,
VESA_640x350p85,
VESA_640x400p85,
VESA_720x400p85,
VESA_640x480p60,
VESA_640x480p72,
VESA_640x480p75,
VESA_640x480p85,
VESA_800x600p56,
VESA_800x600p60,
VESA_800x600p72,
VESA_800x600p75,
VESA_800X600p85,
VESA_840X480p60,
VESA_1024x768p60,
VESA_1024x768p70,
VESA_1024x768p75,
VESA_1024x768p85,
VESA_1152x864p75,
VESA_1280x768p60R,
VESA_1280x768p60,
VESA_1280x768p75,
VESA_1280x768p85,
VESA_1280x960p60,
VESA_1280x960p85,
VESA_1280x1024p60,
VESA_1280x1024p75,
VESA_1280X1024p85,
VESA_1360X768p60,
VESA_1400x768p60R,
VESA_1400x768p60,
VESA_1400x1050p75,
VESA_1400x1050p85,
VESA_1440x900p60R,
VESA_1440x900p60,
VESA_1440x900p75,
VESA_1440x900p85,
VESA_1600x1200p60,
VESA_1600x1200p65,
VESA_1600x1200p70,
VESA_1600x1200p75,
VESA_1600x1200p85,
VESA_1680x1050p60R,
VESA_1680x1050p60,
VESA_1680x1050p75,
VESA_1680x1050p85,
VESA_1792x1344p60,
VESA_1792x1344p75,
VESA_1856x1392p60,
VESA_1856x1392p75,
VESA_1920x1200p60R,
VESA_1920x1200p60,
VESA_1920x1200p75,
VESA_1920x1200p85,
VESA_1920x1440p60,
VESA_1920x1440p75,
UNKNOWN_MODE
} MODE_ID;
///////////////////////////////////////////////////////////////////////
// Output Mode Type
///////////////////////////////////////////////////////////////////////
#define RES_ASPEC_4x3 0
#define RES_ASPEC_16x9 1
#define F_MODE_REPT_NO 0
#define F_MODE_REPT_TWICE 1
#define F_MODE_REPT_QUATRO 3
#define F_MODE_CSC_ITU601 0
#define F_MODE_CSC_ITU709 1
/* Follow prototypes need accomplish by ourself */
int cat66121_detect_device(void);
int cat66121_sys_init(struct hdmi *hdmi);
int cat66121_sys_unplug(struct hdmi *hdmi);
int cat66121_sys_detect_hpd(struct hdmi *hdmi, int *hpdstatus);
int cat66121_sys_detect_sink(struct hdmi *hdmi, int *sink_status);
int cat66121_sys_read_edid(struct hdmi *hdmi, int block, unsigned char *buff);
int cat66121_sys_config_video(struct hdmi *hdmi, int vic, int input_color, int output_color);
int cat66121_sys_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio);
int cat66121_sys_config_hdcp(struct hdmi *hdmi, int enable);
int cat66121_sys_enalbe_output(struct hdmi *hdmi, int enable);
int cat66121_sys_check_status(struct hdmi *hdmi);
#endif // _cat66121_SYS_H_

138
drivers/video/rockchip/hdmi/chips/cat66121/config.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <config.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _CONFIG_H_
#define _CONFIG_H_
#pragma message("config.h")
#ifdef EXTERN_HDCPROM
#pragma message("Defined EXTERN_HDCPROM")
#endif // EXTERN_HDCPROM
#define SUPPORT_EDID
#define SUPPORT_HDCP
//#define SUPPORT_SHA
//#define SUPPORT_AUDIO_MONITOR
#define AudioOutDelayCnt 250
//////////////////////////////////////////////////////////////////////////////////////////
// Video Configuration
//////////////////////////////////////////////////////////////////////////////////////////
// 2010/01/26 added a option to disable HDCP.
#define SUPPORT_OUTPUTYUV
#define SUPPORT_OUTPUTRGB
// #define DISABLE_HDMITX_CSC
#define SUPPORT_INPUTRGB
#define SUPPORT_INPUTYUV444
#define SUPPORT_INPUTYUV422
// #define SUPPORT_SYNCEMBEDDED
// #define SUPPORT_DEGEN
#define NON_SEQUENTIAL_YCBCR422
#define INPUT_COLOR_MODE F_MODE_RGB444
//#define INPUT_COLOR_MODE F_MODE_YUV422
//#define INPUT_COLOR_MODE F_MODE_YUV444
#define INPUT_COLOR_DEPTH 24
// #define INPUT_COLOR_DEPTH 30
// #define INPUT_COLOR_DEPTH 36
//#define OUTPUT_COLOR_MODE F_MODE_YUV422
//#define OUTPUT_COLOR_MODE F_MODE_YUV444
#define OUTPUT_COLOR_MODE F_MODE_RGB444
//#define OUTPUT_3D_MODE Frame_Pcaking
//#define OUTPUT_3D_MODE Top_and_Botton
//#define OUTPUT_3D_MODE Side_by_Side
// #define INV_INPUT_ACLK
#define INV_INPUT_PCLK
#ifdef SUPPORT_SYNCEMBEDDED
// #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB) // 16 bit sync embedded
// #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded
#define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR|T_MODE_PCLKDIV2) // 16 bit sync embedded DDR
// #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR) // 8 bit sync embedded DDR
#define SUPPORT_INPUTYUV422
#ifdef INPUT_COLOR_MODE
#undef INPUT_COLOR_MODE
#endif // INPUT_COLOR_MODE
#define INPUT_COLOR_MODE F_MODE_YUV422
#else
#pragma message ("Defined seperated sync.")
#define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate
//#define INPUT_SIGNAL_TYPE ( T_MODE_DEGEN )
//#define INPUT_SIGNAL_TYPE ( T_MODE_INDDR)
//#define INPUT_SIGNAL_TYPE ( T_MODE_SYNCEMB)
//#define INPUT_SIGNAL_TYPE ( T_MODE_CCIR656 | T_MODE_SYNCEMB )
#endif
#if defined(SUPPORT_INPUTYUV444) || defined(SUPPORT_INPUTYUV422)
#define SUPPORT_INPUTYUV
#endif
#ifdef SUPPORT_SYNCEMBEDDED
#pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.")
#endif
//////////////////////////////////////////////////////////////////////////////////////////
// Audio Configuration
//////////////////////////////////////////////////////////////////////////////////////////
// #define SUPPORT_HBR_AUDIO
#define USE_SPDIF_CHSTAT
#ifndef SUPPORT_HBR_AUDIO
#define INPUT_SAMPLE_FREQ AUDFS_48KHz
#define INPUT_SAMPLE_FREQ_HZ 48000L
#define OUTPUT_CHANNEL 2 // 3 // 4 // 5//6 //7 //8
#define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM
// #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM
#define CONFIG_INPUT_AUDIO_SPDIF FALSE // I2S
// #define CONFIG_INPUT_AUDIO_SPDIF TRUE // SPDIF
// #define I2S_FORMAT 0x00 // 24bit I2S audio
#define I2S_FORMAT 0x01 // 32bit I2S audio
// #define I2S_FORMAT 0x02 // 24bit I2S audio, right justify
// #define I2S_FORMAT 0x03 // 32bit I2S audio, right justify
#else // SUPPORT_HBR_AUDIO
#define INPUT_SAMPLE_FREQ AUDFS_768KHz
#define INPUT_SAMPLE_FREQ_HZ 768000L
#define OUTPUT_CHANNEL 8
#define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR
#define CONFIG_INPUT_AUDIO_SPDIF FALSE // I2S
// #define CONFIG_INPUT_AUDIO_SPDIF TRUE // SPDIF
#define I2S_FORMAT 0x47 // 32bit audio
#endif
//////////////////////////////////////////////////////////////////////////////////////////
// Audio Monitor Configuration
//////////////////////////////////////////////////////////////////////////////////////////
// #define HDMITX_AUTO_MONITOR_INPUT
// #define HDMITX_INPUT_INFO
#ifdef HDMITX_AUTO_MONITOR_INPUT
#define HDMITX_INPUT_INFO
#endif
#endif

83
drivers/video/rockchip/hdmi/chips/cat66121/csc.c Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <csc.c>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/01/06
// @fileversion: COMMON_2.00
//******************************************/
#include "config.h"
#include "typedef.h"
#if (defined (SUPPORT_OUTPUTYUV)) && (defined (SUPPORT_INPUTRGB))
BYTE _CODE bCSCMtx_RGB2YUV_ITU601_16_235[] =
{
0x00,0x80,0x00,
0xB2,0x04,0x65,0x02,0xE9,0x00,
0x93,0x3C,0x18,0x04,0x55,0x3F,
0x49,0x3D,0x9F,0x3E,0x18,0x04
} ;
BYTE _CODE bCSCMtx_RGB2YUV_ITU601_0_255[] =
{
0x10,0x80,0x10,
0x09,0x04,0x0E,0x02,0xC9,0x00,
0x0F,0x3D,0x84,0x03,0x6D,0x3F,
0xAB,0x3D,0xD1,0x3E,0x84,0x03
} ;
BYTE _CODE bCSCMtx_RGB2YUV_ITU709_16_235[] =
{
0x00,0x80,0x00,
0xB8,0x05,0xB4,0x01,0x94,0x00,
0x4a,0x3C,0x17,0x04,0x9F,0x3F,
0xD9,0x3C,0x10,0x3F,0x17,0x04
} ;
BYTE _CODE bCSCMtx_RGB2YUV_ITU709_0_255[] =
{
0x10,0x80,0x10,
0xEa,0x04,0x77,0x01,0x7F,0x00,
0xD0,0x3C,0x83,0x03,0xAD,0x3F,
0x4B,0x3D,0x32,0x3F,0x83,0x03
} ;
#endif
#if (defined (SUPPORT_OUTPUTRGB)) && (defined (SUPPORT_INPUTYUV))
BYTE _CODE bCSCMtx_YUV2RGB_ITU601_16_235[] =
{
0x00,0x00,0x00,
0x00,0x08,0x6B,0x3A,0x50,0x3D,
0x00,0x08,0xF5,0x0A,0x02,0x00,
0x00,0x08,0xFD,0x3F,0xDA,0x0D
} ;
BYTE _CODE bCSCMtx_YUV2RGB_ITU601_0_255[] =
{
0x04,0x00,0xA7,
0x4F,0x09,0x81,0x39,0xDD,0x3C,
0x4F,0x09,0xC4,0x0C,0x01,0x00,
0x4F,0x09,0xFD,0x3F,0x1F,0x10
} ;
BYTE _CODE bCSCMtx_YUV2RGB_ITU709_16_235[] =
{
0x00,0x00,0x00,
0x00,0x08,0x55,0x3C,0x88,0x3E,
0x00,0x08,0x51,0x0C,0x00,0x00,
0x00,0x08,0x00,0x00,0x84,0x0E
} ;
BYTE _CODE bCSCMtx_YUV2RGB_ITU709_0_255[] =
{
0x04,0x00,0xA7,
0x4F,0x09,0xBA,0x3B,0x4B,0x3E,
0x4F,0x09,0x57,0x0E,0x02,0x00,
0x4F,0x09,0xFE,0x3F,0xE8,0x10
} ;
#endif

106
drivers/video/rockchip/hdmi/chips/cat66121/debug.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <debug.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _DEBUG_H_
#define _DEBUG_H_
#define Debug_message 1
#pragma message("debug.h")
#ifndef Debug_message
#define Debug_message 1
#endif
#if Debug_message
#define HDMITX_DEBUG_PRINTF(x) printk x
#define HDCP_DEBUG_PRINTF(x) printk x
#define EDID_DEBUG_PRINTF(x) printk x
#define HDMITX_DEBUG_INFO(x) printk x
#else
#define HDMITX_DEBUG_PRINTF(x)
#define HDCP_DEBUG_PRINTF(x)
#define EDID_DEBUG_PRINTF(x)
#define HDMITX_DEBUG_INFO(x)
#endif
#if( Debug_message & (1<<1))
#define HDMITX_DEBUG_PRINTF1(x) printk x
#define HDCP_DEBUG_PRINTF1(x) printk x
#define EDID_DEBUG_PRINTF1(x) printk x
#else
#define HDMITX_DEBUG_PRINTF1(x)
#define HDCP_DEBUG_PRINTF1(x)
#define EDID_DEBUG_PRINTF1(x)
#endif
#if( Debug_message & (1<<2))
#define HDMITX_DEBUG_PRINTF2(x) printk x
#define HDCP_DEBUG_PRINTF2(x) printk x
#define EDID_DEBUG_PRINTF2(x) printk x
#else
#define HDMITX_DEBUG_PRINTF2(x)
#define HDCP_DEBUG_PRINTF2(x)
#define EDID_DEBUG_PRINTF2(x)
#endif
#if( Debug_message & (1<<3))
#define HDMITX_DEBUG_PRINTF3(x) printk x
#define HDCP_DEBUG_PRINTF3(x) printk x
#define EDID_DEBUG_PRINTF3(x) printk x
#else
#define HDMITX_DEBUG_PRINTF3(x)
#define HDCP_DEBUG_PRINTF3(x)
#define EDID_DEBUG_PRINTF3(x)
#endif
#if( Debug_message & (1<<4))
#define HDMITX_DEBUG_PRINTF4(x) printk x
#define HDCP_DEBUG_PRINTF4(x) printk x
#define EDID_DEBUG_PRINTF4(x) printk x
#else
#define HDMITX_DEBUG_PRINTF4(x)
#define HDCP_DEBUG_PRINTF4(x)
#define EDID_DEBUG_PRINTF4(x)
#endif
#if( Debug_message & (1<<5))
#define HDMITX_DEBUG_PRINTF5(x) printk x
#define HDCP_DEBUG_PRINTF5(x) printk x
#define EDID_DEBUG_PRINTF5(x) printk x
#else
#define HDMITX_DEBUG_PRINTF5(x)
#define HDCP_DEBUG_PRINTF5(x)
#define EDID_DEBUG_PRINTF5(x)
#endif
#if( Debug_message & (1<<6))
#define HDMITX_DEBUG_PRINTF6(x) printk x
#define HDCP_DEBUG_PRINTF6(x) printk x
#define EDID_DEBUG_PRINTF6(x) printk x
#else
#define HDMITX_DEBUG_PRINTF6(x)
#define HDCP_DEBUG_PRINTF6(x)
#define EDID_DEBUG_PRINTF6(x)
#endif
#if( Debug_message & (1<<7))
#define HDMITX_DEBUG_PRINTF7(x) printk x
#define HDCP_DEBUG_PRINTF7(x) printk x
#define EDID_DEBUG_PRINTF7(x) printk x
#else
#define HDMITX_DEBUG_PRINTF7(x)
#define HDCP_DEBUG_PRINTF7(x)
#define EDID_DEBUG_PRINTF7(x)
#endif
#endif// _DEBUG_H_

58
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _HDMITX_H_
#define _HDMITX_H_
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include "debug.h"
#include "config.h"
#include "typedef.h"
#include "hdmitx_drv.h"
#define HDMITX_MAX_DEV_COUNT 1
///////////////////////////////////////////////////////////////////////
// Output Mode Type
///////////////////////////////////////////////////////////////////////
#define RES_ASPEC_4x3 0
#define RES_ASPEC_16x9 1
#define F_MODE_REPT_NO 0
#define F_MODE_REPT_TWICE 1
#define F_MODE_REPT_QUATRO 3
#define F_MODE_CSC_ITU601 0
#define F_MODE_CSC_ITU709 1
#define TIMER_LOOP_LEN 10
#define MS(x) (((x)+(TIMER_LOOP_LEN-1))/TIMER_LOOP_LEN); // for timer loop
// #define SUPPORT_AUDI_AudSWL 16 // Jeilin case.
#define SUPPORT_AUDI_AudSWL 24 // Jeilin case.
#if(SUPPORT_AUDI_AudSWL==16)
#define CHTSTS_SWCODE 0x02
#elif(SUPPORT_AUDI_AudSWL==18)
#define CHTSTS_SWCODE 0x04
#elif(SUPPORT_AUDI_AudSWL==20)
#define CHTSTS_SWCODE 0x03
#else
#define CHTSTS_SWCODE 0x0B
#endif
#endif // _HDMITX_H_

2594
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_drv.c Executable file
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746
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_drv.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx_drv.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _HDMITX_DRV_H_
#define _HDMITX_DRV_H_
//#define EXTERN_HDCPROM
/////////////////////////////////////////
// DDC Address
/////////////////////////////////////////
#define DDC_HDCP_ADDRESS 0x74
#define DDC_EDID_ADDRESS 0xA0
#define DDC_FIFO_MAXREQ 0x20
// I2C address
#define _80MHz 80000000
#define HDMI_TX_I2C_SLAVE_ADDR 0x98
#define CEC_I2C_SLAVE_ADDR 0x9C
#define DISABLE_HDMITX_CSC
///////////////////////////////////////////////////////////////////////
// Register offset
///////////////////////////////////////////////////////////////////////
#define REG_TX_VENDOR_ID0 0x00
#define REG_TX_VENDOR_ID1 0x01
#define REG_TX_DEVICE_ID0 0x02
#define REG_TX_DEVICE_ID1 0x03
#define O_TX_DEVID 0
#define M_TX_DEVID 0xF
#define O_TX_REVID 4
#define M_TX_REVID 0xF
#define REG_TX_SW_RST 0x04
#define B_TX_ENTEST (1<<7)
#define B_TX_REF_RST_HDMITX (1<<5)
#define B_TX_AREF_RST (1<<4)
#define B_HDMITX_VID_RST (1<<3)
#define B_HDMITX_AUD_RST (1<<2)
#define B_TX_HDMI_RST (1<<1)
#define B_TX_HDCP_RST_HDMITX (1<<0)
#define REG_TX_INT_CTRL 0x05
#define B_TX_INTPOL_ACTL 0
#define B_TX_INTPOL_ACTH (1<<7)
#define B_TX_INT_PUSHPULL 0
#define B_TX_INT_OPENDRAIN (1<<6)
#define REG_TX_INT_STAT1 0x06
#define B_TX_INT_AUD_OVERFLOW (1<<7)
#define B_TX_INT_ROMACQ_NOACK (1<<6)
#define B_TX_INT_RDDC_NOACK (1<<5)
#define B_TX_INT_DDCFIFO_ERR (1<<4)
#define B_TX_INT_ROMACQ_BUS_HANG (1<<3)
#define B_TX_INT_DDC_BUS_HANG (1<<2)
#define B_TX_INT_RX_SENSE (1<<1)
#define B_TX_INT_HPD_PLUG (1<<0)
#define REG_TX_INT_STAT2 0x07
#define B_TX_INT_HDCP_SYNC_DET_FAIL (1<<7)
#define B_TX_INT_VID_UNSTABLE (1<<6)
#define B_TX_INT_PKTACP (1<<5)
#define B_TX_INT_PKTNULL (1<<4)
#define B_TX_INT_PKTGENERAL (1<<3)
#define B_TX_INT_KSVLIST_CHK (1<<2)
#define B_TX_INT_AUTH_DONE (1<<1)
#define B_TX_INT_AUTH_FAIL (1<<0)
#define REG_TX_INT_STAT3 0x08
#define B_TX_INT_AUD_CTS (1<<6)
#define B_TX_INT_VSYNC (1<<5)
#define B_TX_INT_VIDSTABLE (1<<4)
#define B_TX_INT_PKTMPG (1<<3)
#define B_TX_INT_PKTSPD (1<<2)
#define B_TX_INT_PKTAUD (1<<1)
#define B_TX_INT_PKTAVI (1<<0)
#define REG_TX_INT_MASK1 0x09
#define B_TX_AUDIO_OVFLW_MASK (1<<7)
#define B_TX_DDC_NOACK_MASK (1<<5)
#define B_TX_DDC_FIFO_ERR_MASK (1<<4)
#define B_TX_DDC_BUS_HANG_MASK (1<<2)
#define B_TX_RXSEN_MASK (1<<1)
#define B_TX_HPD_MASK (1<<0)
#define REG_TX_INT_MASK2 0x0A
#define B_TX_PKT_AVI_MASK (1<<7)
#define B_TX_PKT_VID_UNSTABLE_MASK (1<<6)
#define B_TX_PKT_ACP_MASK (1<<5)
#define B_TX_PKT_NULL_MASK (1<<4)
#define B_TX_PKT_GEN_MASK (1<<3)
#define B_TX_KSVLISTCHK_MASK (1<<2)
#define B_TX_AUTH_DONE_MASK (1<<1)
#define B_TX_AUTH_FAIL_MASK (1<<0)
#define REG_TX_INT_MASK3 0x0B
#define B_TX_HDCP_SYNC_DET_FAIL_MASK (1<<6)
#define B_TX_AUDCTS_MASK (1<<5)
#define B_TX_VSYNC_MASK (1<<4)
#define B_TX_VIDSTABLE_MASK (1<<3)
#define B_TX_PKT_MPG_MASK (1<<2)
#define B_TX_PKT_SPD_MASK (1<<1)
#define B_TX_PKT_AUD_MASK (1<<0)
#define REG_TX_INT_CLR0 0x0C
#define B_TX_CLR_PKTACP (1<<7)
#define B_TX_CLR_PKTNULL (1<<6)
#define B_TX_CLR_PKTGENERAL (1<<5)
#define B_TX_CLR_KSVLISTCHK (1<<4)
#define B_TX_CLR_AUTH_DONE (1<<3)
#define B_TX_CLR_AUTH_FAIL (1<<2)
#define B_TX_CLR_RXSENSE (1<<1)
#define B_TX_CLR_HPD (1<<0)
#define REG_TX_INT_CLR1 0x0D
#define B_TX_CLR_VSYNC (1<<7)
#define B_TX_CLR_VIDSTABLE (1<<6)
#define B_TX_CLR_PKTMPG (1<<5)
#define B_TX_CLR_PKTSPD (1<<4)
#define B_TX_CLR_PKTAUD (1<<3)
#define B_TX_CLR_PKTAVI (1<<2)
#define B_TX_CLR_HDCP_SYNC_DET_FAIL (1<<1)
#define B_TX_CLR_VID_UNSTABLE (1<<0)
#define REG_TX_SYS_STATUS 0x0E
// readonly
#define B_TX_INT_ACTIVE (1<<7)
#define B_TX_HPDETECT (1<<6)
#define B_TX_RXSENDETECT (1<<5)
#define B_TXVIDSTABLE (1<<4)
// read/write
#define O_TX_CTSINTSTEP 2
#define M_TX_CTSINTSTEP (3<<2)
#define B_TX_CLR_AUD_CTS (1<<1)
#define B_TX_INTACTDONE (1<<0)
#define REG_TX_BANK_CTRL 0x0F
#define B_TX_BANK0 0
#define B_TX_BANK1 1
// DDC
#define REG_TX_DDC_MASTER_CTRL 0x10
#define B_TX_MASTERROM (1<<1)
#define B_TX_MASTERDDC (0<<1)
#define B_TX_MASTERHOST (1<<0)
#define B_TX_MASTERHDCP (0<<0)
#define REG_TX_DDC_HEADER 0x11
#define REG_TX_DDC_REQOFF 0x12
#define REG_TX_DDC_REQCOUNT 0x13
#define REG_TX_DDC_EDIDSEG 0x14
#define REG_TX_DDC_CMD 0x15
#define CMD_DDC_SEQ_BURSTREAD 0
#define CMD_LINK_CHKREAD 2
#define CMD_EDID_READ 3
#define CMD_FIFO_CLR 9
#define CMD_GEN_SCLCLK 0xA
#define CMD_DDC_ABORT 0xF
#define REG_TX_DDC_STATUS 0x16
#define B_TX_DDC_DONE (1<<7)
#define B_TX_DDC_ACT (1<<6)
#define B_TX_DDC_NOACK (1<<5)
#define B_TX_DDC_WAITBUS (1<<4)
#define B_TX_DDC_ARBILOSE (1<<3)
#define B_TX_DDC_ERROR (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE)
#define B_TX_DDC_FIFOFULL (1<<2)
#define B_TX_DDC_FIFOEMPTY (1<<1)
#define REG_TX_DDC_READFIFO 0x17
#define REG_TX_ROM_STARTADDR 0x18
#define REG_TX_HDCP_HEADER 0x19
#define REG_TX_ROM_HEADER 0x1A
#define REG_TX_BUSHOLD_T 0x1B
#define REG_TX_ROM_STAT 0x1C
#define B_TX_ROM_DONE (1<<7)
#define B_TX_ROM_ACTIVE (1<<6)
#define B_TX_ROM_NOACK (1<<5)
#define B_TX_ROM_WAITBUS (1<<4)
#define B_TX_ROM_ARBILOSE (1<<3)
#define B_TX_ROM_BUSHANG (1<<2)
// HDCP
#define REG_TX_AN_GENERATE 0x1F
#define B_TX_START_CIPHER_GEN 1
#define B_TX_STOP_CIPHER_GEN 0
#define REG_TX_CLK_CTRL0 0x58
#define O_TX_OSCLK_SEL 5
#define M_TX_OSCLK_SEL 3
#define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4)
#define O_TX_EXT_MCLK_SEL 2
#define M_TX_EXT_MCLK_SEL (3<<O_TX_EXT_MCLK_SEL)
#define B_TX_EXT_128FS (0<<O_TX_EXT_MCLK_SEL)
#define B_TX_EXT_256FS (1<<O_TX_EXT_MCLK_SEL)
#define B_TX_EXT_512FS (2<<O_TX_EXT_MCLK_SEL)
#define B_TX_EXT_1024FS (3<<O_TX_EXT_MCLK_SEL)
#define REG_TX_SHA_SEL 0x50
#define REG_TX_SHA_RD_BYTE1 0x51
#define REG_TX_SHA_RD_BYTE2 0x52
#define REG_TX_SHA_RD_BYTE3 0x53
#define REG_TX_SHA_RD_BYTE4 0x54
#define REG_TX_AKSV_RD_BYTE5 0x55
#define REG_TX_CLK_CTRL1 0x59
#define B_TX_EN_TXCLK_COUNT (1<<5)
#define B_TX_VDO_LATCH_EDGE (1<<3)
#define REG_TX_CLK_STATUS1 0x5E
#define REG_TX_CLK_STATUS2 0x5F
#define B_TX_IP_LOCK (1<<7)
#define B_TX_XP_LOCK (1<<6)
#define B_TX_OSF_LOCK (1<<5)
#define REG_TX_AUD_COUNT 0x60
#define REG_TX_AFE_DRV_CTRL 0x61
#define B_TX_AFE_DRV_PWD (1<<5)
#define B_TX_AFE_DRV_RST (1<<4)
#define REG_TX_PLL_CTRL 0x6A
// Input Data Format Register
#define REG_TX_INPUT_MODE 0x70
#define O_TX_INCLKDLY 0
#define M_TX_INCLKDLY 3
#define B_TX_INDDR (1<<2)
#define B_TX_SYNCEMB (1<<3)
#define B_TX_2X656CLK (1<<4)
#define B_TX_PCLKDIV2 (1<<5)
#define M_TX_INCOLMOD (3<<6)
#define B_TX_IN_RGB 0
#define B_TX_IN_YUV422 (1<<6)
#define B_TX_IN_YUV444 (2<<6)
#define REG_TX_TXFIFO_RST 0x71
#define B_TX_ENAVMUTERST 1
#define B_TXFFRST (1<<1)
#define REG_TX_CSC_CTRL 0x72
#define B_HDMITX_CSC_BYPASS 0
#define B_HDMITX_CSC_RGB2YUV 2
#define B_HDMITX_CSC_YUV2RGB 3
#define M_TX_CSC_SEL 3
#define B_TX_EN_DITHER (1<<7)
#define B_TX_EN_UDFILTER (1<<6)
#define B_TX_DNFREE_GO (1<<5)
#define SIZEOF_CSCMTX 21
#define SIZEOF_CSCGAIN 6
#define SIZEOF_CSCOFFSET 3
#define REG_TX_CSC_YOFF 0x73
#define REG_TX_CSC_COFF 0x74
#define REG_TX_CSC_RGBOFF 0x75
#define REG_TX_CSC_MTX11_L 0x76
#define REG_TX_CSC_MTX11_H 0x77
#define REG_TX_CSC_MTX12_L 0x78
#define REG_TX_CSC_MTX12_H 0x79
#define REG_TX_CSC_MTX13_L 0x7A
#define REG_TX_CSC_MTX13_H 0x7B
#define REG_TX_CSC_MTX21_L 0x7C
#define REG_TX_CSC_MTX21_H 0x7D
#define REG_TX_CSC_MTX22_L 0x7E
#define REG_TX_CSC_MTX22_H 0x7F
#define REG_TX_CSC_MTX23_L 0x80
#define REG_TX_CSC_MTX23_H 0x81
#define REG_TX_CSC_MTX31_L 0x82
#define REG_TX_CSC_MTX31_H 0x83
#define REG_TX_CSC_MTX32_L 0x84
#define REG_TX_CSC_MTX32_H 0x85
#define REG_TX_CSC_MTX33_L 0x86
#define REG_TX_CSC_MTX33_H 0x87
#define REG_TX_CSC_GAIN1V_L 0x88
#define REG_TX_CSC_GAIN1V_H 0x89
#define REG_TX_CSC_GAIN2V_L 0x8A
#define REG_TX_CSC_GAIN2V_H 0x8B
#define REG_TX_CSC_GAIN3V_L 0x8C
#define REG_TX_CSC_GAIN3V_H 0x8D
#define REG_TX_HVPol 0x90
#define REG_TX_HfPixel 0x91
#define REG_TX_HSSL 0x95
#define REG_TX_HSEL 0x96
#define REG_TX_HSH 0x97
#define REG_TX_VSS1 0xA0
#define REG_TX_VSE1 0xA1
#define REG_TX_VSS2 0xA2
#define REG_TX_VSE2 0xA3
// HDMI General Control Registers
#define REG_TX_HDMI_MODE 0xC0
#define B_TX_HDMI_MODE 1
#define B_TX_DVI_MODE 0
#define REG_TX_AV_MUTE 0xC1
#define REG_TX_GCP 0xC1
#define B_TX_CLR_AVMUTE 0
#define B_TX_SET_AVMUTE 1
#define B_TX_SETAVMUTE (1<<0)
#define B_TX_BLUE_SCR_MUTE (1<<1)
#define B_TX_NODEF_PHASE (1<<2)
#define B_TX_PHASE_RESYNC (1<<3)
#define O_TX_COLOR_DEPTH 4
#define M_TX_COLOR_DEPTH 7
#define B_TX_COLOR_DEPTH_MASK (M_TX_COLOR_DEPTH<<O_TX_COLOR_DEPTH)
#define B_TX_CD_NODEF 0
#define B_TX_CD_24 (4<<4)
#define B_TX_CD_30 (5<<4)
#define B_TX_CD_36 (6<<4)
#define B_TX_CD_48 (7<<4)
#define REG_TX_PKT_GENERAL_CTRL 0xC6
#define REG_TX_OESS_CYCLE 0xC3
/////////////////////////////////////////////////////////////////////
// Macro
/////////////////////////////////////////////////////////////////////
#define Switch_HDMITX_Bank(x) HDMITX_SetI2C_Byte(0x0f,1, (x)&1)
#define HDMITX_OrReg_Byte(reg,ormask) HDMITX_SetI2C_Byte(reg,(ormask),(ormask))
#define HDMITX_AndReg_Byte(reg,andmask) HDMITX_WriteI2C_Byte(reg,(HDMITX_ReadI2C_Byte(reg) & (andmask)))
/////////////////////////////////////////////////////////////////////
// data structure
/////////////////////////////////////////////////////////////////////
typedef struct _HDMITXDEV_STRUCT {
BYTE I2C_DEV ;
BYTE I2C_ADDR ;
/////////////////////////////////////////////////
// Interrupt Type
/////////////////////////////////////////////////
BYTE bIntType ; // = 0 ;
/////////////////////////////////////////////////
// Video Property
/////////////////////////////////////////////////
BYTE bInputVideoSignalType ; // for Sync Embedded,CCIR656,InputDDR
/////////////////////////////////////////////////
// Audio Property
/////////////////////////////////////////////////
BYTE bOutputAudioMode ; // = 0 ;
BYTE bAudioChannelSwap ; // = 0 ;
BYTE bAudioChannelEnable ;
BYTE bAudFs ;
unsigned long TMDSClock ;
unsigned long RCLK ;
BYTE bAuthenticated:1 ;
BYTE bHDMIMode: 1;
BYTE bIntPOL:1 ; // 0 = Low Active
BYTE bHPD:1 ;
// 2009/11/11 added by jj_tseng@ite.com.tw
BYTE bSPDIF_OUT;
BYTE TxEMEMStatus:1 ;
//~jau-chih.tseng@ite.com.tw 2009/11/11
} HDMITXDEV ;
//~jj_tseng@chipadvanced.com
typedef struct structRegSetEntry {
BYTE offset ;
BYTE invAndMask ;
BYTE OrMask ;
} RegSetEntry;
#include "hdmitx_hdcp.h"
#include "hdmitx_input.h"
// Audio Channel Control
#define REG_TX_AUDIO_CTRL0 0xE0
#define M_TX_AUD_SWL (3<<6)
#define M_TX_AUD_16BIT (0<<6)
#define M_TX_AUD_18BIT (1<<6)
#define M_TX_AUD_20BIT (2<<6)
#define M_TX_AUD_24BIT (3<<6)
#define B_TX_SPDIFTC (1<<5)
#define B_TX_AUD_SPDIF (1<<4)
#define B_TX_AUD_I2S (0<<4)
#define B_TX_AUD_EN_I2S3 (1<<3)
#define B_TX_AUD_EN_I2S2 (1<<2)
#define B_TX_AUD_EN_I2S1 (1<<1)
#define B_TX_AUD_EN_I2S0 (1<<0)
#define B_TX_AUD_EN_SPDIF 1
#define REG_TX_AUDIO_CTRL1 0xE1
#define B_TX_AUD_FULLPKT (1<<6)
#define B_TX_AUDFMT_STD_I2S (0<<0)
#define B_TX_AUDFMT_32BIT_I2S (1<<0)
#define B_TX_AUDFMT_LEFT_JUSTIFY (0<<1)
#define B_TX_AUDFMT_RIGHT_JUSTIFY (1<<1)
#define B_TX_AUDFMT_DELAY_1T_TO_WS (0<<2)
#define B_TX_AUDFMT_NO_DELAY_TO_WS (1<<2)
#define B_TX_AUDFMT_WS0_LEFT (0<<3)
#define B_TX_AUDFMT_WS0_RIGHT (1<<3)
#define B_TX_AUDFMT_MSB_SHIFT_FIRST (0<<4)
#define B_TX_AUDFMT_LSB_SHIFT_FIRST (1<<4)
#define B_TX_AUDFMT_RISE_EDGE_SAMPLE_WS (0<<5)
#define B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS (1<<5)
#define REG_TX_AUDIO_FIFOMAP 0xE2
#define O_TX_FIFO3SEL 6
#define O_TX_FIFO2SEL 4
#define O_TX_FIFO1SEL 2
#define O_TX_FIFO0SEL 0
#define B_TX_SELSRC3 3
#define B_TX_SELSRC2 2
#define B_TX_SELSRC1 1
#define B_TX_SELSRC0 0
#define REG_TX_AUDIO_CTRL3 0xE3
#define B_TX_AUD_MULCH (1<<7)
#define B_TX_EN_ZERO_CTS (1<<6)
#define B_TX_CHSTSEL (1<<4)
#define B_TX_S3RLCHG (1<<3)
#define B_TX_S2RLCHG (1<<2)
#define B_TX_S1RLCHG (1<<1)
#define B_TX_S0RLCHG (1<<0)
#define REG_TX_AUD_SRCVALID_FLAT 0xE4
#define B_TX_AUD_SPXFLAT_SRC3 (1<<7)
#define B_TX_AUD_SPXFLAT_SRC2 (1<<6)
#define B_TX_AUD_SPXFLAT_SRC1 (1<<5)
#define B_TX_AUD_SPXFLAT_SRC0 (1<<4)
#define B_TX_AUD_ERR2FLAT (1<<3)
#define B_TX_AUD_S3VALID (1<<2)
#define B_TX_AUD_S2VALID (1<<1)
#define B_TX_AUD_S1VALID (1<<0)
#define REG_TX_AUD_HDAUDIO 0xE5
#define B_TX_HBR (1<<3)
#define B_TX_DSD (1<<1)
//////////////////////////////////////////
// Bank 1
//////////////////////////////////////////
#define REGPktAudCTS0 0x30 // 7:0
#define REGPktAudCTS1 0x31 // 15:8
#define REGPktAudCTS2 0x32 // 19:16
#define REGPktAudN0 0x33 // 7:0
#define REGPktAudN1 0x34 // 15:8
#define REGPktAudN2 0x35 // 19:16
#define REGPktAudCTSCnt0 0x35 // 3:0
#define REGPktAudCTSCnt1 0x36 // 11:4
#define REGPktAudCTSCnt2 0x37 // 19:12
#define REG_TX_AUDCHST_MODE 0x91 // 191 REG_TX_AUD_CHSTD[2:0] 6:4
// REG_TX_AUD_CHSTC 3
// REG_TX_AUD_NLPCM 2
// REG_TX_AUD_MONO 0
#define REG_TX_AUDCHST_CAT 0x92 // 192 REG_TX_AUD_CHSTCAT 7:0
#define REG_TX_AUDCHST_SRCNUM 0x93 // 193 REG_TX_AUD_CHSTSRC 3:0
#define REG_TX_AUD0CHST_CHTNUM 0x94 // 194 REG_TX_AUD0_CHSTCHR 7:4
// REG_TX_AUD0_CHSTCHL 3:0
#define REG_TX_AUD1CHST_CHTNUM 0x95 // 195 REG_TX_AUD1_CHSTCHR 7:4
// REG_TX_AUD1_CHSTCHL 3:0
#define REG_TX_AUD2CHST_CHTNUM 0x96 // 196 REG_TX_AUD2_CHSTCHR 7:4
// REG_TX_AUD2_CHSTCHL 3:0
#define REG_TX_AUD3CHST_CHTNUM 0x97 // 197 REG_TX_AUD3_CHSTCHR 7:4
// REG_TX_AUD3_CHSTCHL 3:0
#define REG_TX_AUDCHST_CA_FS 0x98 // 198 REG_TX_AUD_CHSTCA 5:4
// REG_TX_AUD_CHSTFS 3:0
#define REG_TX_AUDCHST_OFS_WL 0x99 // 199 REG_TX_AUD_CHSTOFS 7:4
// REG_TX_AUD_CHSTWL 3:0
#define REG_TX_PKT_SINGLE_CTRL 0xC5
#define B_TX_SINGLE_PKT 1
#define B_TX_BURST_PKT
#define B_TX_SW_CTS (1<<1)
#define REG_TX_NULL_CTRL 0xC9
#define REG_TX_ACP_CTRL 0xCA
#define REG_TX_ISRC1_CTRL 0xCB
#define REG_TX_ISRC2_CTRL 0xCC
#define REG_TX_AVI_INFOFRM_CTRL 0xCD
#define REG_TX_AUD_INFOFRM_CTRL 0xCE
#define REG_TX_SPD_INFOFRM_CTRL 0xCF
#define REG_TX_MPG_INFOFRM_CTRL 0xD0
#define B_TX_ENABLE_PKT 1
#define B_TX_REPEAT_PKT (1<<1)
#define REG_TX_3D_INFO_CTRL 0xD2
//////////////////////////////////////////
// COMMON PACKET for NULL,ISRC1,ISRC2,SPD
//////////////////////////////////////////
#define REG_TX_PKT_HB00 0x38
#define REG_TX_PKT_HB01 0x39
#define REG_TX_PKT_HB02 0x3A
#define REG_TX_PKT_PB00 0x3B
#define REG_TX_PKT_PB01 0x3C
#define REG_TX_PKT_PB02 0x3D
#define REG_TX_PKT_PB03 0x3E
#define REG_TX_PKT_PB04 0x3F
#define REG_TX_PKT_PB05 0x40
#define REG_TX_PKT_PB06 0x41
#define REG_TX_PKT_PB07 0x42
#define REG_TX_PKT_PB08 0x43
#define REG_TX_PKT_PB09 0x44
#define REG_TX_PKT_PB10 0x45
#define REG_TX_PKT_PB11 0x46
#define REG_TX_PKT_PB12 0x47
#define REG_TX_PKT_PB13 0x48
#define REG_TX_PKT_PB14 0x49
#define REG_TX_PKT_PB15 0x4A
#define REG_TX_PKT_PB16 0x4B
#define REG_TX_PKT_PB17 0x4C
#define REG_TX_PKT_PB18 0x4D
#define REG_TX_PKT_PB19 0x4E
#define REG_TX_PKT_PB20 0x4F
#define REG_TX_PKT_PB21 0x50
#define REG_TX_PKT_PB22 0x51
#define REG_TX_PKT_PB23 0x52
#define REG_TX_PKT_PB24 0x53
#define REG_TX_PKT_PB25 0x54
#define REG_TX_PKT_PB26 0x55
#define REG_TX_PKT_PB27 0x56
#define REG_TX_AVIINFO_DB1 0x58
#define REG_TX_AVIINFO_DB2 0x59
#define REG_TX_AVIINFO_DB3 0x5A
#define REG_TX_AVIINFO_DB4 0x5B
#define REG_TX_AVIINFO_DB5 0x5C
#define REG_TX_AVIINFO_DB6 0x5E
#define REG_TX_AVIINFO_DB7 0x5F
#define REG_TX_AVIINFO_DB8 0x60
#define REG_TX_AVIINFO_DB9 0x61
#define REG_TX_AVIINFO_DB10 0x62
#define REG_TX_AVIINFO_DB11 0x63
#define REG_TX_AVIINFO_DB12 0x64
#define REG_TX_AVIINFO_DB13 0x65
#define REG_TX_AVIINFO_SUM 0x5D
#define REG_TX_PKT_AUDINFO_CC 0x68 // [2:0]
#define REG_TX_PKT_AUDINFO_SF 0x69 // [4:2]
#define REG_TX_PKT_AUDINFO_CA 0x6B // [7:0]
#define REG_TX_PKT_AUDINFO_DM_LSV 0x6C // [7][6:3]
#define REG_TX_PKT_AUDINFO_SUM 0x6D // [7:0]
// Source Product Description Info Frame
#define REG_TX_PKT_SPDINFO_SUM 0x70
#define REG_TX_PKT_SPDINFO_PB1 0x71
#define REG_TX_PKT_SPDINFO_PB2 0x72
#define REG_TX_PKT_SPDINFO_PB3 0x73
#define REG_TX_PKT_SPDINFO_PB4 0x74
#define REG_TX_PKT_SPDINFO_PB5 0x75
#define REG_TX_PKT_SPDINFO_PB6 0x76
#define REG_TX_PKT_SPDINFO_PB7 0x77
#define REG_TX_PKT_SPDINFO_PB8 0x78
#define REG_TX_PKT_SPDINFO_PB9 0x79
#define REG_TX_PKT_SPDINFO_PB10 0x7A
#define REG_TX_PKT_SPDINFO_PB11 0x7B
#define REG_TX_PKT_SPDINFO_PB12 0x7C
#define REG_TX_PKT_SPDINFO_PB13 0x7D
#define REG_TX_PKT_SPDINFO_PB14 0x7E
#define REG_TX_PKT_SPDINFO_PB15 0x7F
#define REG_TX_PKT_SPDINFO_PB16 0x80
#define REG_TX_PKT_SPDINFO_PB17 0x81
#define REG_TX_PKT_SPDINFO_PB18 0x82
#define REG_TX_PKT_SPDINFO_PB19 0x83
#define REG_TX_PKT_SPDINFO_PB20 0x84
#define REG_TX_PKT_SPDINFO_PB21 0x85
#define REG_TX_PKT_SPDINFO_PB22 0x86
#define REG_TX_PKT_SPDINFO_PB23 0x87
#define REG_TX_PKT_SPDINFO_PB24 0x88
#define REG_TX_PKT_SPDINFO_PB25 0x89
#define REG_TX_PKT_MPGINFO_FMT 0x8A
#define B_TX_MPG_FR 1
#define B_TX_MPG_MF_I (1<<1)
#define B_TX_MPG_MF_B (2<<1)
#define B_TX_MPG_MF_P (3<<1)
#define B_TX_MPG_MF_MASK (3<<1)
#define REG_TX_PKG_MPGINFO_DB0 0x8B
#define REG_TX_PKG_MPGINFO_DB1 0x8C
#define REG_TX_PKG_MPGINFO_DB2 0x8D
#define REG_TX_PKG_MPGINFO_DB3 0x8E
#define REG_TX_PKG_MPGINFO_SUM 0x8F
#define Frame_Pcaking 0
#define Top_and_Botton 6
#define Side_by_Side 8
////////////////////////////////////////////////////
// Function Prototype
////////////////////////////////////////////////////
#define hdmitx_ENABLE_NULL_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_ACP_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ACP_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_ISRC1_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC1_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_ISRC2_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC2_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_AVI_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AVI_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_AUD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AUD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_SPD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_SPD_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_MPG_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_ENABLE_GeneralPurpose_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); }
#define hdmitx_DISABLE_VSDB_PKT() { HDMITX_WriteI2C_Byte(REG_TX_3D_INFO_CTRL,0); }
#define hdmitx_DISABLE_NULL_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,0); }
#define hdmitx_DISABLE_ACP_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ACP_CTRL,0); }
#define hdmitx_DISABLE_ISRC1_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC1_CTRL,0); }
#define hdmitx_DISABLE_ISRC2_PKT() { HDMITX_WriteI2C_Byte(REG_TX_ISRC2_CTRL,0); }
#define hdmitx_DISABLE_AVI_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AVI_INFOFRM_CTRL,0); }
#define hdmitx_DISABLE_AUD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_AUD_INFOFRM_CTRL,0); }
#define hdmitx_DISABLE_SPD_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_SPD_INFOFRM_CTRL,0); }
#define hdmitx_DISABLE_MPG_INFOFRM_PKT() { HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,0); }
#define hdmitx_DISABLE_GeneralPurpose_PKT() { HDMITX_WriteI2C_Byte(REG_TX_NULL_CTRL,0); }
//////////////////////////////////////////////////////////////////////
// External Interface
//////////////////////////////////////////////////////////////////////
typedef enum {
PCLK_LOW = 0 ,
PCLK_MEDIUM,
PCLK_HIGH
} VIDEOPCLKLEVEL ;
// 2008/08/18 added by jj_tseng@chipadvanced.com
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX function prototype
/////////////////////////////////////////////////////////////////////////////////////
void InitHDMITX();
void HDMITX_InitTxDev(HDMITXDEV *pInstance);
BYTE CheckHDMITX(BYTE *pHPD,BYTE *pHPDChange);
BOOL getHDMITX_LinkStatus();
void HDMITX_PowerOn();
void HDMITX_PowerDown();
void hdmitx_LoadRegSetting(RegSetEntry table[]);
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX video function prototype
/////////////////////////////////////////////////////////////////////////////////////
void HDMITX_DisableVideoOutput();
BOOL HDMITX_EnableVideoOutput(VIDEOPCLKLEVEL level,BYTE inputColorMode,BYTE outputColorMode,BYTE bHDMI);
BOOL setHDMITX_VideoSignalType(BYTE inputSignalType);
void setHDMITX_ColorDepthPhase(BYTE ColorDepth,BYTE bPhase);
// TBD ...
// #ifdef SUPPORT_DEGEN
// BOOL ProgramDEGenModeByID(MODE_ID id,BYTE bInputSignalType);
// #endif // SUPPORT_DEGEN
#ifdef SUPPORT_SYNCEMBEDDED
BOOL setHDMITX_SyncEmbeddedByVIC(BYTE VIC,BYTE bInputSignalType);
#endif
void hdmitx_SetInputMode(BYTE InputMode,BYTE bInputSignalType);
void hdmitx_SetCSCScale(BYTE bInputMode,BYTE bOutputMode);
void hdmitx_SetupAFE(VIDEOPCLKLEVEL level);
void hdmitx_FireAFE();
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX audio function prototype
/////////////////////////////////////////////////////////////////////////////////////
void HDMITX_DisableAudioOutput();
void HDMITX_EnableAudioOutput(BYTE AudioType, BOOL bSPDIF, ULONG SampleFreq, BYTE ChNum, BYTE *pIEC60958ChStat, ULONG TMDSClock);
void setHDMITX_AudioChannelEnable(BOOL EnableAudio_b);
void setHDMITX_ChStat(BYTE ucIEC60958ChStat[]);
void setHDMITX_DSDAudio();
void setHDMITX_HBRAudio(BOOL bSPDIF);
void setHDMITX_LPCMAudio(BYTE AudioSrcNum, BYTE AudSWL, BOOL bSPDIF);
void setHDMITX_NCTS(BYTE Fs);
void setHDMITX_NLPCMAudio(BOOL bSPDIF);
void setHDMITX_UpdateChStatFs(ULONG Fs);
BOOL hdmitx_IsAudioChang();
void hdmitx_AutoAdjustAudio();
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX hdcp function prototype
/////////////////////////////////////////////////////////////////////////////////////
BOOL HDMITX_EnableHDCP(BYTE bEnable);
BOOL getHDMITX_AuthenticationDone();
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX pkt/infoframe function prototype
/////////////////////////////////////////////////////////////////////////////////////
void setHDMITX_AVMute(BYTE bEnable);
BOOL HDMITX_EnableAVIInfoFrame(BYTE bEnable,BYTE *pAVIInfoFrame);
BOOL HDMITX_EnableAudioInfoFrame(BYTE bEnable,BYTE *pAudioInfoFrame);
BOOL HDMITX_EnableVSInfoFrame(BYTE bEnable,BYTE *pVSInfoFrame);
SYS_STATUS hdmitx_SetAVIInfoFrame(AVI_InfoFrame *pAVIInfoFrame);
SYS_STATUS hdmitx_SetAudioInfoFrame(Audio_InfoFrame *pAudioInfoFrame);
SYS_STATUS hdmitx_SetSPDInfoFrame(SPD_InfoFrame *pSPDInfoFrame);
SYS_STATUS hdmitx_SetMPEGInfoFrame(MPEG_InfoFrame *pMPGInfoFrame);
SYS_STATUS hdmitx_SetVSIInfoFrame(VendorSpecific_InfoFrame *pVSIInfoFrame);
SYS_STATUS hdmitx_Set_GeneralPurpose_PKT(BYTE *pData);
/////////////////////////////////////////////////////////////////////////////////////
// HDMITX ddc/edid function prototype
/////////////////////////////////////////////////////////////////////////////////////
BOOL getHDMITX_EDIDBlock(int EDIDBlockID,BYTE *pEDIDData);
SYS_STATUS getHDMITX_EDIDBytes(BYTE *pData,BYTE bSegment,BYTE offset,SHORT Count);
void hdmitx_GenerateDDCSCLK();
void hdmitx_ClearDDCFIFO();
void hdmitx_AbortDDC();
#if defined(Debug_message) && (Debug_message==1)
void DumpHDMITXReg();
#else
#define DumpHDMITXReg()
#endif
#define delay1ms(x) mdelay(x)
////////////////////////////////////////////////////////////////////
// Required Interfance
////////////////////////////////////////////////////////////////////
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr);
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE d);
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N);
SYS_STATUS HDMITX_SetI2C_Byte(BYTE Reg,BYTE Mask,BYTE Value);
//SYS_STATUS HDMITX_ToggleBit(BYTE Reg,BYTE n);
#endif // _HDMITX_DRV_H_

1021
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_hdcp.c Executable file
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drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_hdcp.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx_hdcp.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _HDMITX_HDCP_H_
#define _HDMITX_HDCP_H_
#define REG_TX_HDCP_DESIRE 0x20
#define B_TX_ENABLE_HDPC11 (1<<1)
#define B_TX_CPDESIRE (1<<0)
#define REG_TX_AUTHFIRE 0x21
#define REG_TX_LISTCTRL 0x22
#define B_TX_LISTFAIL (1<<1)
#define B_TX_LISTDONE (1<<0)
#define REG_TX_AKSV 0x23
#define REG_TX_AKSV0 0x23
#define REG_TX_AKSV1 0x24
#define REG_TX_AKSV2 0x25
#define REG_TX_AKSV3 0x26
#define REG_TX_AKSV4 0x27
#define REG_TX_AN 0x28
#define REG_TX_AN_GEN 0x30
#define REG_TX_ARI 0x38
#define REG_TX_ARI0 0x38
#define REG_TX_ARI1 0x39
#define REG_TX_APJ 0x3A
#define REG_TX_BKSV 0x3B
#define REG_TX_BRI 0x40
#define REG_TX_BRI0 0x40
#define REG_TX_BRI1 0x41
#define REG_TX_BPJ 0x42
#define REG_TX_BCAP 0x43
#define B_TX_CAP_HDMI_REPEATER (1<<6)
#define B_TX_CAP_KSV_FIFO_RDY (1<<5)
#define B_TX_CAP_HDMI_FAST_MODE (1<<4)
#define B_CAP_HDCP_1p1 (1<<1)
#define B_TX_CAP_FAST_REAUTH (1<<0)
#define REG_TX_BSTAT 0x44
#define REG_TX_BSTAT0 0x44
#define REG_TX_BSTAT1 0x45
#define B_TX_CAP_HDMI_MODE (1<<12)
#define B_TX_CAP_DVI_MODE (0<<12)
#define B_TX_MAX_CASCADE_EXCEEDED (1<<11)
#define M_TX_REPEATER_DEPTH (0x7<<8)
#define O_TX_REPEATER_DEPTH 8
#define B_TX_DOWNSTREAM_OVER (1<<7)
#define M_TX_DOWNSTREAM_COUNT 0x7F
#define REG_TX_AUTH_STAT 0x46
#define B_TX_AUTH_DONE (1<<7)
////////////////////////////////////////////////////
// Function Prototype
////////////////////////////////////////////////////
BOOL getHDMITX_AuthenticationDone();
void hdmitx_hdcp_ClearAuthInterrupt();
void hdmitx_hdcp_ResetAuth();
void hdmitx_hdcp_Auth_Fire();
void hdmitx_hdcp_StartAnCipher();
void hdmitx_hdcp_StopAnCipher();
void hdmitx_hdcp_GenerateAn();
SYS_STATUS hdmitx_hdcp_GetBCaps(PBYTE pBCaps ,PUSHORT pBStatus);
SYS_STATUS hdmitx_hdcp_GetBKSV(BYTE *pBKSV);
void hdmitx_hdcp_Reset();
SYS_STATUS hdmitx_hdcp_Authenticate();
SYS_STATUS hdmitx_hdcp_VerifyIntegration();
void hdmitx_hdcp_CancelRepeaterAuthenticate();
void hdmitx_hdcp_ResumeRepeaterAuthenticate();
SYS_STATUS hdmitx_hdcp_CheckSHA(BYTE pM0[],USHORT BStatus,BYTE pKSVList[],int cDownStream,BYTE Vr[]);
SYS_STATUS hdmitx_hdcp_GetKSVList(BYTE *pKSVList,BYTE cDownStream);
SYS_STATUS hdmitx_hdcp_GetVr(BYTE *pVr);
SYS_STATUS hdmitx_hdcp_GetM0(BYTE *pM0);
SYS_STATUS hdmitx_hdcp_Authenticate_Repeater();
void hdmitx_hdcp_ResumeAuthentication();
#endif // _HDMITX_HDCP_H_

190
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_input.c Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx_input.c>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#include "hdmitx.h"
#include "hdmitx_drv.h"
#ifdef HDMITX_INPUT_INFO
extern HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT] ;
LONG CalcRCLK();
LONG CalcAudFS();
LONG CalcRCLK();
#define InitCEC() HDMITX_SetI2C_Byte(0x0F, 0x08, 0x00)
#define DisableCEC() HDMITX_SetI2C_Byte(0x0F, 0x08, 0x08)
LONG CalcAudFS()
{
// LONG RCLK ;
LONG Cnt ;
LONG FS ;
// RCLK = CalcRCLK();
Switch_HDMITX_Bank(0);
Cnt = (LONG)HDMITX_ReadI2C_Byte(0x60);
FS = hdmiTxDev[0].RCLK / 2 ;
FS /= Cnt ;
HDMITX_DEBUG_PRINTF1(("FS = %ld RCLK = %ld, Cnt = %ld\n",FS,hdmiTxDev[0].RCLK,Cnt)) ;
return FS ;
}
LONG CalcPCLK()
{
BYTE uc, div ;
int i ;
long sum , count, PCLK ;
Switch_HDMITX_Bank(0);
uc = HDMITX_ReadI2C_Byte(0x5F) & 0x80 ;
if( ! uc )
{
return 0 ;
}
// InitCEC();
// // uc = CEC_ReadI2C_Byte(0x09) & 0xFE ;
// CEC_WriteI2C_Byte(0x09, 1);
// delay1ms(100);
// CEC_WriteI2C_Byte(0x09, 0);
// RCLK = CEC_ReadI2C_Byte(0x47);
// RCLK <<= 8 ;
// RCLK |= CEC_ReadI2C_Byte(0x46);
// RCLK <<= 8 ;
// RCLK |= CEC_ReadI2C_Byte(0x45);
// DisableCEC();
// // RCLK *= 160 ; // RCLK /= 100 ;
// // RCLK in KHz.
HDMITX_SetI2C_Byte(0xD7, 0xF0, 0x80);
delay1ms(1);
HDMITX_SetI2C_Byte(0xD7, 0x80, 0x00);
count = HDMITX_ReadI2C_Byte(0xD7) & 0xF ;
count <<= 8 ;
count |= HDMITX_ReadI2C_Byte(0xD8);
for( div = 7 ; div > 0 ; div-- )
{
// printf("div = %d\n",(int)div) ;
if(count < (1<<(11-div)) )
{
break ;
}
}
HDMITX_SetI2C_Byte(0xD7, 0x70, div<<4);
uc = HDMITX_ReadI2C_Byte(0xD7) & 0x7F ;
for( i = 0 , sum = 0 ; i < 100 ; i ++ )
{
HDMITX_WriteI2C_Byte(0xD7, uc|0x80) ;
delay1ms(1);
HDMITX_WriteI2C_Byte(0xD7, uc) ;
count = HDMITX_ReadI2C_Byte(0xD7) & 0xF ;
count <<= 8 ;
count |= HDMITX_ReadI2C_Byte(0xD8);
sum += count ;
}
sum /= 100 ; count = sum ;
HDMITX_DEBUG_PRINTF1(("RCLK(in GetPCLK) = %ld\n",hdmiTxDev[0].RCLK));
HDMITX_DEBUG_PRINTF1(("div = %d, count = %d\n",(int)div,(int)count) );
HDMITX_DEBUG_PRINTF1(("count = %ld\n",count) );
PCLK = hdmiTxDev[0].RCLK * 128 / count * 16 ;
PCLK *= (1<<div);
if( HDMITX_ReadI2C_Byte(0x70) & 0x10 )
{
PCLK /= 2 ;
}
HDMITX_DEBUG_PRINTF1(("PCLK = %ld\n",PCLK) );
return PCLK ;
}
LONG CalcRCLK()
{
// BYTE uc ;
int i ;
long sum, RCLKCNT ;
InitCEC();
sum = 0 ;
for( i = 0 ; i < 5 ; i++ )
{
// uc = CEC_ReadI2C_Byte(0x09) & 0xFE ;
CEC_WriteI2C_Byte(0x09, 1);
delay1ms(100);
CEC_WriteI2C_Byte(0x09, 0);
RCLKCNT = CEC_ReadI2C_Byte(0x47);
RCLKCNT <<= 8 ;
RCLKCNT |= CEC_ReadI2C_Byte(0x46);
RCLKCNT <<= 8 ;
RCLKCNT |= CEC_ReadI2C_Byte(0x45);
// HDMITX_DEBUG_PRINTF1(("RCLK = %ld\n",RCLKCNT) );
sum += RCLKCNT ;
}
DisableCEC();
RCLKCNT = sum * 32 ;
HDMITX_DEBUG_PRINTF(("RCLK = %ld,%03ld,%03ld\n",RCLKCNT/1000000,(RCLKCNT%1000000)/1000,RCLKCNT%1000));
return RCLKCNT ;
}
USHORT hdmitx_getInputHTotal()
{
BYTE uc ;
USHORT hTotal ;
HDMITX_SetI2C_Byte(0x0F,1,0) ;
HDMITX_SetI2C_Byte(0xA8,8,8) ;
uc = HDMITX_ReadI2C_Byte(0xB2) ;
hTotal = (uc&1)?(1<<12):0 ;
uc = HDMITX_ReadI2C_Byte(0x91) ;
hTotal |= ((USHORT)uc)<<4 ;
uc = HDMITX_ReadI2C_Byte(0x90) ;
hTotal |= (uc&0xF0) >> 4 ;
HDMITX_SetI2C_Byte(0xA8,8,0) ;
return hTotal ;
}
USHORT hdmitx_getInputVTotal()
{
BYTE uc ;
USHORT vTotal ;
HDMITX_SetI2C_Byte(0x0F,1,0) ;
HDMITX_SetI2C_Byte(0xA8,8,8) ;
uc = HDMITX_ReadI2C_Byte(0x99) ;
vTotal = ((USHORT)uc&0xF)<<8 ;
uc = HDMITX_ReadI2C_Byte(0x98) ;
vTotal |= uc;
HDMITX_SetI2C_Byte(0xA8,8,0) ;
return vTotal ;
}
BOOL hdmitx_isInputInterlace()
{
BYTE uc ;
HDMITX_SetI2C_Byte(0x0F,1,0) ;
HDMITX_SetI2C_Byte(0xA8,8,8) ;
uc = HDMITX_ReadI2C_Byte(0xA5) ;
HDMITX_SetI2C_Byte(0xA8,8,0) ;
return uc&(1<<4)?TRUE:FALSE ;
}
BYTE hdmitx_getAudioCount()
{
return HDMITX_ReadI2C_Byte(REG_TX_AUD_COUNT) ;
}
#endif

26
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_input.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx_input.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _HDMITX_DEBUG_H_
#define _HDMITX_DEBUG_H_
#ifdef HDMITX_INPUT_INFO
LONG CalcPCLK();
LONG CalcAudFS();
LONG CalcRCLK();
BYTE hdmitx_getAudioCount() ;
USHORT hdmitx_getInputHTotal();
USHORT hdmitx_getInputVTotal();
BOOL hdmitx_isInputInterlace();
#endif
#endif

1371
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_sys.c Executable file
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15
drivers/video/rockchip/hdmi/chips/cat66121/hdmitx_sys.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <hdmitx_sys.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _HDMITX_SYS_H_
#define _HDMITX_SYS_H_
#include "cat66121_hdmi_hw.h"
#endif // _HDMITX_SYS_H_

152
drivers/video/rockchip/hdmi/chips/cat66121/sha1.c Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.c>
// @author Hermes.Wu@ite.com.tw
// @date 2011/08/26
// @fileversion: COMMON_FILE_1.01
//******************************************/
#include <stdio.h>
//#include <stdlib.h>
#include "sha1.h"
#ifndef DISABLE_HDCP
#define WCOUNT 17
ULONG VH[5];
ULONG w[WCOUNT];
#define rol(x,y)(((x)<< (y))| (((ULONG)x)>> (32-y)))
void SHATransform(ULONG * h)
{
int t;
ULONG tmp;
h[0]=0x67452301;
h[1]=0xefcdab89;
h[2]=0x98badcfe;
h[3]=0x10325476;
h[4]=0xc3d2e1f0;
for (t=0; t < 20; t++){
if(t>=16)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
}
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[3] & ~h[1]))+ h[4] + w[(t)% WCOUNT] + 0x5a827999;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=20; t < 40; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0x6ed9eba1;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=40; t < 60; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[1] & h[3])| (h[2] & h[3]))+ h[4] + w[(t)% WCOUNT] + 0x8f1bbcdc;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=60; t < 80; t++)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0xca62c1d6;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[0] +=0x67452301;
h[1] +=0xefcdab89;
h[2] +=0x98badcfe;
h[3] +=0x10325476;
h[4] +=0xc3d2e1f0;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
}
void SHA_Simple(void *p,WORD len,BYTE *output)
{
// SHA_State s;
WORD i,t;
ULONG c;
BYTE *pBuff=p;
for(i=0;i < len;i++)
{
t=i/4;
if(i%4==0)
{
w[t]=0;
}
c=pBuff[i];
c <<=(3-(i%4))*8;
w[t] |=c;
HDCP_DEBUG_PRINTF2(("pBuff[%d]=%02X,c=%08lX,w[%d]=%08lX\n",(int)i,(int)pBuff[i],c,(int)t,w[t]));
}
t=i/4;
if(i%4==0)
{
w[t]=0;
}
//c=0x80 << ((3-i%4)*24);
c=0x80;
c <<=((3-i%4)*8);
w[t]|=c;t++;
for(; t < 15;t++)
{
w[t]=0;
}
w[15]=len*8;
for(i = 0 ; i < 16 ; i++)
{
HDCP_DEBUG_PRINTF2(("w[%d] = %08lX\n",i,w[i]));
}
SHATransform(VH);
for(i=0;i < 5;i++)
{
output[i*4+3]=(BYTE)((VH[i]>>24)&0xFF);
output[i*4+2]=(BYTE)((VH[i]>>16)&0xFF);
output[i*4+1]=(BYTE)((VH[i]>>8)&0xFF);
output[i*4+0]=(BYTE)(VH[i]&0xFF);
}
}
#endif

46
drivers/video/rockchip/hdmi/chips/cat66121/sha1.h Executable file
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///*****************************************
// Copyright (C)2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.h>
// @author Jau-chih.Tseng@ite.com.tw
// @date 2010/06/04
// @fileversion: COMMON_FILE_1.01
//******************************************/
#ifndef _SHA_1_H_
#define _SHA_1_H_
#ifdef _MCU_8051_
#include "Mcu.h"
#endif
#include <string.h>
#if Debug_message
#include <stdio.h>
#endif
#include "config.h"
#include "typedef.h"
#ifndef HDCP_DEBUG_PRINTF
#define HDCP_DEBUG_PRINTF(x)
#endif //HDCP_DEBUG_PRINTF
#ifndef HDCP_DEBUG_PRINTF1
#define HDCP_DEBUG_PRINTF1(x)
#endif //HDCP_DEBUG_PRINTF1
#ifndef HDCP_DEBUG_PRINTF2
#define HDCP_DEBUG_PRINTF2(x)
#endif //HDCP_DEBUG_PRINTF2
#ifndef DISABLE_HDCP
void SHA_Simple(void *p,WORD len,BYTE *output);
void SHATransform(ULONG * h);
#endif
#endif // _SHA_1_H_

380
drivers/video/rockchip/hdmi/chips/cat66121/typedef.h Executable file
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <typedef.h>
// @author Jau-Chih.Tseng@ite.com.tw
// @date 2012/12/20
// @fileversion: ITE_HDMITX_SAMPLE_3.14
//******************************************/
#ifndef _TYPEDEF_H_
#define _TYPEDEF_H_
//////////////////////////////////////////////////
// data type
//////////////////////////////////////////////////
#ifdef _MCU_8051_
#define _CODE code
#define _DATA data
#define _XDATA xdata
#define _IDATA idata
typedef bit BOOL ;
#else
#define _CODE const
#define _DATA
#define _IDATA
#define _XDATA
typedef int BOOL ;
#endif // _MCU_8051_
typedef _CODE unsigned char cBYTE;
typedef char CHAR,*PCHAR ;
typedef unsigned char uchar,*puchar ;
typedef unsigned char UCHAR,*PUCHAR ;
typedef unsigned char byte,*pbyte ;
typedef unsigned char BYTE,*PBYTE ;
typedef short SHORT,*PSHORT ;
typedef unsigned short *pushort ;
typedef unsigned short USHORT,*PUSHORT ;
typedef unsigned short word,*pword ;
typedef unsigned short WORD,*PWORD ;
typedef unsigned int UINT,*PUINT ;
typedef long LONG,*PLONG ;
typedef unsigned long *pulong ;
typedef unsigned long ULONG,*PULONG ;
typedef unsigned long dword,*pdword ;
typedef unsigned long DWORD,*PDWORD ;
#define FALSE 0
#define TRUE 1
#define SUCCESS 0
#define FAIL -1
#define ON 1
#define OFF 0
#define LO_ACTIVE TRUE
#define HI_ACTIVE FALSE
typedef enum _SYS_STATUS {
ER_SUCCESS = 0,
ER_FAIL,
ER_RESERVED
} SYS_STATUS ;
#define ABS(x) (((x)>=0)?(x):(-(x)))
///////////////////////////////////////////////////////////////////////
// Video Data Type
///////////////////////////////////////////////////////////////////////
#define F_MODE_RGB444 0
#define F_MODE_YUV422 1
#define F_MODE_YUV444 2
#define F_MODE_CLRMOD_MASK 3
#define F_MODE_INTERLACE 1
#define F_VIDMODE_ITU709 (1<<4)
#define F_VIDMODE_ITU601 0
#define F_VIDMODE_0_255 0
#define F_VIDMODE_16_235 (1<<5)
#define F_VIDMODE_EN_UDFILT (1<<6)
#define F_VIDMODE_EN_DITHER (1<<7)
#define T_MODE_CCIR656 (1<<0)
#define T_MODE_SYNCEMB (1<<1)
#define T_MODE_INDDR (1<<2)
#define T_MODE_PCLKDIV2 (1<<3)
#define T_MODE_DEGEN (1<<4)
#define T_MODE_SYNCGEN (1<<5)
/////////////////////////////////////////////////////////////////////
// Packet and Info Frame definition and datastructure.
/////////////////////////////////////////////////////////////////////
#define VENDORSPEC_INFOFRAME_TYPE 0x81
#define AVI_INFOFRAME_TYPE 0x82
#define SPD_INFOFRAME_TYPE 0x83
#define AUDIO_INFOFRAME_TYPE 0x84
#define MPEG_INFOFRAME_TYPE 0x85
#define VENDORSPEC_INFOFRAME_VER 0x01
#define AVI_INFOFRAME_VER 0x02
#define SPD_INFOFRAME_VER 0x01
#define AUDIO_INFOFRAME_VER 0x01
#define MPEG_INFOFRAME_VER 0x01
#define VENDORSPEC_INFOFRAME_LEN 5
#define AVI_INFOFRAME_LEN 13
#define SPD_INFOFRAME_LEN 25
#define AUDIO_INFOFRAME_LEN 10
#define MPEG_INFOFRAME_LEN 10
#define ACP_PKT_LEN 9
#define ISRC1_PKT_LEN 16
#define ISRC2_PKT_LEN 16
typedef union _VendorSpecific_InfoFrame
{
struct {
BYTE Type ;
BYTE Ver ;
BYTE Len ;
BYTE CheckSum;
BYTE IEEE_0;//PB1
BYTE IEEE_1;//PB2
BYTE IEEE_2;//PB3
BYTE Rsvd:5 ;//PB4
BYTE HDMI_Video_Format:3 ;
BYTE Reserved_PB5:4 ;//PB5
BYTE _3D_Structure:4 ;
BYTE Reserved_PB6:4 ;//PB6
BYTE _3D_Ext_Data:4 ;
} info ;
struct {
BYTE VS_HB[3] ;
BYTE CheckSum;
BYTE VS_DB[28] ;
} pktbyte ;
} VendorSpecific_InfoFrame ;
typedef union _AVI_InfoFrame
{
struct {
BYTE Type;
BYTE Ver;
BYTE Len;
BYTE checksum ;
BYTE Scan:2;
BYTE BarInfo:2;
BYTE ActiveFmtInfoPresent:1;
BYTE ColorMode:2;
BYTE FU1:1;
BYTE ActiveFormatAspectRatio:4;
BYTE PictureAspectRatio:2;
BYTE Colorimetry:2;
BYTE Scaling:2;
BYTE FU2:6;
BYTE VIC:7;
BYTE FU3:1;
BYTE PixelRepetition:4;
BYTE FU4:4;
short Ln_End_Top;
short Ln_Start_Bottom;
short Pix_End_Left;
short Pix_Start_Right;
} info;
struct {
BYTE AVI_HB[3];
BYTE checksum ;
BYTE AVI_DB[AVI_INFOFRAME_LEN];
} pktbyte;
} AVI_InfoFrame;
typedef union _Audio_InfoFrame {
struct {
BYTE Type;
BYTE Ver;
BYTE Len;
BYTE checksum ;
BYTE AudioChannelCount:3;
BYTE RSVD1:1;
BYTE AudioCodingType:4;
BYTE SampleSize:2;
BYTE SampleFreq:3;
BYTE Rsvd2:3;
BYTE FmtCoding;
BYTE SpeakerPlacement;
BYTE Rsvd3:3;
BYTE LevelShiftValue:4;
BYTE DM_INH:1;
} info;
struct {
BYTE AUD_HB[3];
BYTE checksum ;
BYTE AUD_DB[5];
} pktbyte;
} Audio_InfoFrame;
typedef union _MPEG_InfoFrame {
struct {
BYTE Type;
BYTE Ver;
BYTE Len;
BYTE checksum ;
ULONG MpegBitRate;
BYTE MpegFrame:2;
BYTE Rvsd1:2;
BYTE FieldRepeat:1;
BYTE Rvsd2:3;
} info;
struct {
BYTE MPG_HB[3];
BYTE checksum ;
BYTE MPG_DB[MPEG_INFOFRAME_LEN];
} pktbyte;
} MPEG_InfoFrame;
typedef union _SPD_InfoFrame {
struct {
BYTE Type;
BYTE Ver;
BYTE Len;
BYTE checksum ;
char VN[8];
char PD[16];
BYTE SourceDeviceInfomation;
} info;
struct {
BYTE SPD_HB[3];
BYTE checksum ;
BYTE SPD_DB[SPD_INFOFRAME_LEN];
} pktbyte;
} SPD_InfoFrame;
///////////////////////////////////////////////////////////////////////////
// Using for interface.
///////////////////////////////////////////////////////////////////////////
#define PROG 1
#define INTERLACE 0
#define Vneg 0
#define Hneg 0
#define Vpos 1
#define Hpos 1
typedef struct {
WORD H_ActiveStart;
WORD H_ActiveEnd;
WORD H_SyncStart;
WORD H_SyncEnd;
WORD V_ActiveStart;
WORD V_ActiveEnd;
WORD V_SyncStart;
WORD V_SyncEnd;
WORD V2_ActiveStart;
WORD V2_ActiveEnd;
WORD HTotal;
WORD VTotal;
} CEAVTiming;
typedef struct {
BYTE VIC ;
BYTE PixelRep ;
WORD HActive;
WORD VActive;
WORD HTotal;
WORD VTotal;
ULONG PCLK;
BYTE xCnt;
WORD HFrontPorch;
WORD HSyncWidth;
WORD HBackPorch;
BYTE VFrontPorch;
BYTE VSyncWidth;
BYTE VBackPorch;
BYTE ScanMode:1;
BYTE VPolarity:1;
BYTE HPolarity:1;
} HDMI_VTiming;
//////////////////////////////////////////////////////////////////
// Audio relate definition and macro.
//////////////////////////////////////////////////////////////////
// 2008/08/15 added by jj_tseng@chipadvanced
#define F_AUDIO_ON (1<<7)
#define F_AUDIO_HBR (1<<6)
#define F_AUDIO_DSD (1<<5)
#define F_AUDIO_NLPCM (1<<4)
#define F_AUDIO_LAYOUT_1 (1<<3)
#define F_AUDIO_LAYOUT_0 (0<<3)
// HBR - 1100
// DSD - 1010
// NLPCM - 1001
// LPCM - 1000
#define T_AUDIO_MASK 0xF0
#define T_AUDIO_OFF 0
#define T_AUDIO_HBR (F_AUDIO_ON|F_AUDIO_HBR)
#define T_AUDIO_DSD (F_AUDIO_ON|F_AUDIO_DSD)
#define T_AUDIO_NLPCM (F_AUDIO_ON|F_AUDIO_NLPCM)
#define T_AUDIO_LPCM (F_AUDIO_ON)
// for sample clock
#define AUDFS_22p05KHz 4
#define AUDFS_44p1KHz 0
#define AUDFS_88p2KHz 8
#define AUDFS_176p4KHz 12
#define AUDFS_24KHz 6
#define AUDFS_48KHz 2
#define AUDFS_96KHz 10
#define AUDFS_192KHz 14
#define AUDFS_768KHz 9
#define AUDFS_32KHz 3
#define AUDFS_OTHER 1
// Audio Enable
#define ENABLE_SPDIF (1<<4)
#define ENABLE_I2S_SRC3 (1<<3)
#define ENABLE_I2S_SRC2 (1<<2)
#define ENABLE_I2S_SRC1 (1<<1)
#define ENABLE_I2S_SRC0 (1<<0)
#define AUD_SWL_NOINDICATE 0x0
#define AUD_SWL_16 0x2
#define AUD_SWL_17 0xC
#define AUD_SWL_18 0x4
#define AUD_SWL_20 0xA // for maximum 20 bit
#define AUD_SWL_21 0xD
#define AUD_SWL_22 0x5
#define AUD_SWL_23 0x9
#define AUD_SWL_24 0xB
#endif // _TYPEDEF_H_