From f090d642cdb284caeec24f5e070b73936aa1958f Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Mon, 17 Jun 2024 11:36:39 +0800
Subject: [PATCH] ARM: dts: RK3506: add CAN dts nodes

Change-Id: I091746467f07dd3c9840179f634467f28a54eb1e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm/boot/dts/rk3506.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi
index a6d1a6ba2fe6..1225de9ea729 100644
--- a/arch/arm/boot/dts/rk3506.dtsi
+++ b/arch/arm/boot/dts/rk3506.dtsi
@@ -425,6 +425,28 @@
 		status = "disabled";
 	};
 
+	can0: can@ff320000 {
+		compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd";
+		reg = <0xff320000 0x1000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>;
+		clock-names = "baudclk", "apb_pclk";
+		resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>;
+		reset-names = "can", "can-apb";
+		status = "disabled";
+	};
+
+	can1: can@ff330000 {
+		compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd";
+		reg = <0xff330000 0x1000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>;
+		clock-names = "baudclk", "apb_pclk";
+		resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>;
+		reset-names = "can", "can-apb";
+		status = "disabled";
+	};
+
 	fspi: spi@ff488000 {
 		compatible = "rockchip,fspi";
 		reg = <0xff488000 0x4000>;