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ARM: dtsi: rk3228: add dram timing node
Change-Id: Ieb7c43f6e546e75e72c7db99894d6ca0cfbb31a1 Signed-off-by: Tang Yun ping <typ@rock-chips.com>
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Gerrit Code Review
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commit
f09cbe4c13
@@ -6,6 +6,7 @@
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <rk3228_dram_default_timing.dtsi>
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/ {
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compatible = "rockchip,rk3228";
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@@ -140,6 +141,13 @@
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};
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};
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dram: dram {
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compatible = "rockchip,rk3228-dram";
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status = "okay";
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dram_freq = <600000000>;
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rockchip,dram_timing = <&dram_timing>;
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};
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rockchip_clocks_init: clocks-init{
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compatible = "rockchip,clocks-init";
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rockchip,clocks-init-parent =
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38
arch/arm/boot/dts/rk3228_dram_default_timing.dtsi
Executable file
38
arch/arm/boot/dts/rk3228_dram_default_timing.dtsi
Executable file
@@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2014-2015 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/ddr.h>
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#include <dt-bindings/dram/rockchip,rk3368.h>
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/ {
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dram_timing: dram_timing {
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compatible = "rockchip,dram-timing";
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dram_spd_bin = <DDR3_DEFAULT>;
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sr_idle = <1>;
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pd_idle = <0x20>;
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dram_dll_disb_freq = <300>;
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phy_dll_disb_freq = <400>;
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dram_odt_disb_freq = <333>;
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phy_odt_disb_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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lpddr2_drv = <LP2_DS_34ohm>;
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/* lpddr2 not supported odt */
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phy_clk_drv = <PHY_RON_45ohm>;
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phy_cmd_drv = <PHY_RON_34ohm>;
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phy_dqs_drv = <PHY_RON_34ohm>;
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phy_odt = <PHY_RTT_279ohm>;
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};
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};
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