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cacheinfo: Check sib_leaf in cache_leaves_are_shared()

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[ Upstream commit 7a306e3eab ]

If there is no ACPI/DT information, it is assumed that L1 caches
are private and L2 (and higher) caches are shared. A cache is
'shared' between two CPUs if it is accessible from these two
CPUs.

Each CPU owns a representation (i.e. has a dedicated cacheinfo struct)
of the caches it has access to. cache_leaves_are_shared() tries to
identify whether two representations are designating the same actual
cache.

In cache_leaves_are_shared(), if 'this_leaf' is a L2 cache (or higher)
and 'sib_leaf' is a L1 cache, the caches are detected as shared as
only this_leaf's cache level is checked.
This is leads to setting sib_leaf as being shared with another CPU,
which is incorrect as this is a L1 cache.

Check 'sib_leaf->level'. Also update the comment as the function is
called when populating 'shared_cpu_map'.

Fixes: f16d1becf9 ("cacheinfo: Use cache identifiers to check if the caches are shared if available")
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230414081453.244787-2-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Pierre Gondois
2023-04-14 10:14:49 +02:00
committed by Greg Kroah-Hartman
parent 8ba48e58ba
commit f0b58720f2
1 changed files with 2 additions and 3 deletions
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5
drivers/base/cacheinfo.c
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@@ -38,11 +38,10 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
{ {
/* /*
* For non DT/ACPI systems, assume unique level 1 caches, * For non DT/ACPI systems, assume unique level 1 caches,
* system-wide shared caches for all other levels. This will be used * system-wide shared caches for all other levels.
* only if arch specific code has not populated shared_cpu_map
*/ */
if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)))
return !(this_leaf->level == 1); return (this_leaf->level != 1) && (sib_leaf->level != 1);
if ((sib_leaf->attributes & CACHE_ID) && if ((sib_leaf->attributes & CACHE_ID) &&
(this_leaf->attributes & CACHE_ID)) (this_leaf->attributes & CACHE_ID))