From f11c689938c40ce7ec157a14ba89bdb6c4d16ae8 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Wed, 22 Nov 2017 16:10:48 +0800 Subject: [PATCH] clk: rockchip: rk3128: fix incorrect configuration 1. The first parent name of sclk_cif_out_src is wrong, it is "sclk_cif_src". 2. The MUX configuration for sclk_cif_out_src is wrong, it should be muxdiv_offset=29, mux_shift=2, mux_width=1. Change-Id: I36a0ec0791afdef398d37ac8b92b7831619fb01b Signed-off-by: Liang Chen Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3128.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index e4367c8c5b63..d378aa816724 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -147,7 +147,7 @@ PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" }; PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" }; PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" }; -PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" }; +PNAME(mux_clk_cif_out_src_p) = { "sclk_cif_src", "xin24m" }; PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; @@ -356,7 +356,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 2, MFLAGS, RK2928_CLKGATE_CON(3), 7, GFLAGS), MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0, - RK2928_CLKSEL_CON(13), 14, 2, MFLAGS), + RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0, RK2928_CLKSEL_CON(29), 2, 5, DFLAGS), @@ -496,7 +496,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS), GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),