Merge commit 'cf28107f98a2ab7f21527b4eef3fcb971096ce16'

* commit 'cf28107f98a2ab7f21527b4eef3fcb971096ce16': mfd: rkx110_x120: pwm: Add module license soc: rockchip: power-domain: Add memory reset support for rk3576 arm64: dts: rockchip: rk3576: Assign audio_frac_1 to AUPLL clk: rockchip: rk3576: Export CLK_AUDIO_FRAC_SRC video: rockchip: mpp: reset rkvdec before pm suspend video: rockchip: mpp: add reset ready check for vdpu383 media: rockchip: isp: fix multi sensor for isp39 media: i2c: rk628: modify audio status report media: i2c: rk628: fix interrupts can be triggered in suspend Change-Id: Iad409e73d4a62329bd12f3341cbc5a5f800e7249
2026-06-10 04:48:04 +09:00 · 2024-05-17 19:55:27 +08:00
parent 652db7f32e cf28107f98
commit f1783b7f6f
11 changed files with 100 additions and 18 deletions
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1772,13 +1772,16 @@
 		#reset-cells = <1>;

 		assigned-clocks =
+			<&cru CLK_AUDIO_FRAC_1_SRC>,
 			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
 			<&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
 			<&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>,
 			<&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>,
 			<&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>,
 			<&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>;
+		assigned-clock-parents = <&cru PLL_AUPLL>;
 		assigned-clock-rates =
+			<0>,
 			<1188000000>, <1000000000>,
 			<786432000>, <18432000>,
 			<96000000>, <128000000>,
--- a/drivers/clk/rockchip/clk-rk3576.c
+++ b/drivers/clk/rockchip/clk-rk3576.c
@@ -455,25 +455,25 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
 	COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL,
 			RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS,
 			RK3576_CLKGATE_CON(2), 1, GFLAGS),
-	MUX(0, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,
+	MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,
 			RK3576_CLKSEL_CON(13), 0, 2, MFLAGS),
 	COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0,
-			RK3576_CLKSEL_CON(12), 0,
+			RK3576_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
 			RK3576_CLKGATE_CON(1), 10, GFLAGS),
-	MUX(0, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,
+	MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,
 			RK3576_CLKSEL_CON(15), 0, 2, MFLAGS),
 	COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0,
-			RK3576_CLKSEL_CON(14), 0,
+			RK3576_CLKSEL_CON(14), CLK_FRAC_DIVIDER_NO_LIMIT,
 			RK3576_CLKGATE_CON(1), 11, GFLAGS),
-	MUX(0, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,
+	MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,
 			RK3576_CLKSEL_CON(17), 0, 2, MFLAGS),
 	COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0,
-			RK3576_CLKSEL_CON(16), 0,
+			RK3576_CLKSEL_CON(16), CLK_FRAC_DIVIDER_NO_LIMIT,
 			RK3576_CLKGATE_CON(1), 12, GFLAGS),
-	MUX(0, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,
+	MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,
 			RK3576_CLKSEL_CON(19), 0, 2, MFLAGS),
 	COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0,
-			RK3576_CLKSEL_CON(18), 0,
+			RK3576_CLKSEL_CON(18), CLK_FRAC_DIVIDER_NO_LIMIT,
 			RK3576_CLKGATE_CON(1), 13, GFLAGS),
 	MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0,
 			RK3576_CLKSEL_CON(22), 0, 2, MFLAGS),
--- a/drivers/media/i2c/rk628/rk628.h
+++ b/drivers/media/i2c/rk628/rk628.h
@@ -308,6 +308,7 @@ struct rk628 {
 	struct dentry *debug_dir;
 	struct gpio_desc *hdmirx_det_gpio;
 	bool last_mipi_status;
+	bool is_suspend;
 };

 #define rk628_dbg(rk628, format, ...)	\
--- a/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c
+++ b/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c
@@ -252,6 +252,8 @@ static bool tx_5v_power_present(struct v4l2_subdev *sd)

 	ret = rk628_hdmirx_tx_5v_power_detect(bt1120->plugin_det_gpio);
 	v4l2_dbg(2, debug, sd, "%s: %d\n", __func__, ret);
+	if (bt1120->rk628->is_suspend)
+		ret = false;

 	return ret;
 }
@@ -1770,9 +1772,11 @@ static int rk628_bt1120_resume(struct device *dev)
 	rk628_cru_initialize(bt1120->rk628);
 	rk628_bt1120_initial(sd);
 	rk628_hdmirx_plugout(sd);
+	enable_irq(bt1120->plugin_irq);
 	enable_irq(bt1120->hdmirx_irq);
 	schedule_delayed_work(&bt1120->delayed_work_enable_hotplug,
 			     msecs_to_jiffies(500));
+	bt1120->rk628->is_suspend = false;

 	return 0;
 }
@@ -1785,6 +1789,9 @@ static int rk628_bt1120_suspend(struct device *dev)

 	v4l2_info(sd, "%s: suspend!\n", __func__);

+	bt1120->rk628->is_suspend = true;
+	rk628_hdmirx_plugout(sd);
+	disable_irq(bt1120->plugin_irq);
 	disable_irq(bt1120->hdmirx_irq);
 	cancel_delayed_work_sync(&bt1120->delayed_work_res_change);
 	cancel_delayed_work_sync(&bt1120->delayed_work_enable_hotplug);
--- a/drivers/media/i2c/rk628/rk628_csi_v4l2.c
+++ b/drivers/media/i2c/rk628/rk628_csi_v4l2.c
@@ -383,6 +383,8 @@ static bool tx_5v_power_present(struct v4l2_subdev *sd)

 	ret = rk628_hdmirx_tx_5v_power_detect(csi->plugin_det_gpio);
 	v4l2_dbg(2, debug, sd, "%s: %d\n", __func__, ret);
+	if (csi->rk628->is_suspend)
+		ret = false;

 	return ret;
 }
@@ -2889,6 +2891,11 @@ static int rk628_csi_get_custom_ctrl(struct v4l2_ctrl *ctrl)
 	if (ctrl->id == RK_V4L2_CID_AUDIO_SAMPLING_RATE) {
 		ret = get_audio_sampling_rate(sd);
 		*ctrl->p_new.p_s32 = ret;
+	} else if (ctrl->id == RK_V4L2_CID_AUDIO_PRESENT) {
+		ret = tx_5v_power_present(sd) ? rk628_hdmirx_audio_present(csi->audio_info) : 0;
+		*ctrl->p_new.p_s32 = ret;
+	} else {
+		ret = -EINVAL;
 	}

 	return ret;
@@ -2911,6 +2918,7 @@ static const struct v4l2_ctrl_config rk628_csi_ctrl_audio_sampling_rate = {
 };

 static const struct v4l2_ctrl_config rk628_csi_ctrl_audio_present = {
+	.ops = &rk628_csi_custom_ctrl_ops,
 	.id = RK_V4L2_CID_AUDIO_PRESENT,
 	.name = "Audio present",
 	.type = V4L2_CTRL_TYPE_BOOLEAN,
@@ -3009,9 +3017,11 @@ static int rk628_csi_resume(struct device *dev)
 	rk628_cru_initialize(csi->rk628);
 	rk628_csi_initial(sd);
 	rk628_hdmirx_plugout(sd);
+	enable_irq(csi->plugin_irq);
 	enable_irq(csi->hdmirx_irq);
 	schedule_delayed_work(&csi->delayed_work_enable_hotplug,
 			     msecs_to_jiffies(500));
+	csi->rk628->is_suspend = false;

 	return 0;
 }
@@ -3024,6 +3034,9 @@ static int rk628_csi_suspend(struct device *dev)

 	v4l2_info(sd, "%s: suspend!\n", __func__);

+	csi->rk628->is_suspend = true;
+	rk628_hdmirx_plugout(sd);
+	disable_irq(csi->plugin_irq);
 	disable_irq(csi->hdmirx_irq);
 	cancel_delayed_work_sync(&csi->delayed_work_res_change);
 	cancel_delayed_work_sync(&csi->delayed_work_enable_hotplug);
@@ -3403,8 +3416,12 @@ static int rk628_csi_probe(struct i2c_client *client,
 	/* custom controls */
 	csi->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&csi->hdl,
 			&rk628_csi_ctrl_audio_sampling_rate, NULL);
+	if (csi->audio_sampling_rate_ctrl)
+		csi->audio_sampling_rate_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
 	csi->audio_present_ctrl = v4l2_ctrl_new_custom(&csi->hdl,
 			&rk628_csi_ctrl_audio_present, NULL);
+	if (csi->audio_present_ctrl)
+		csi->audio_present_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;

 	sd->ctrl_handler = &csi->hdl;
 	if (csi->hdl.error) {
--- a/drivers/media/platform/rockchip/isp/isp_params_v39.c
+++ b/drivers/media/platform/rockchip/isp/isp_params_v39.c
@@ -2512,6 +2512,11 @@ isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
 				ISP39_DHAZ_THUMB_ROW_MAX : arg->thumb_row & ~1;
 	thumb_col = arg->thumb_col > ISP39_DHAZ_THUMB_COL_MAX ?
 				ISP39_DHAZ_THUMB_COL_MAX : arg->thumb_col & ~1;
+	if (dev->hw_dev->dev_link_num > 1 && thumb_row > 4 &&
+	    !dev->hw_dev->is_frm_buf && thumb_col > 4) {
+		thumb_row = 4;
+		thumb_col = 4;
+	}
 	blk_het = ALIGN(h / thumb_row, 2);
 	blk_wid = ALIGN(w / thumb_col, 2);
 	priv_val->dhaz_blk_num = thumb_row * thumb_col;
@@ -3959,6 +3964,8 @@ void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
 	mask = ISP39_MODULE_YNR | ISP39_MODULE_CNR | ISP39_MODULE_SHARP;
 	if  ((module_ens & mask) && ((module_ens & mask) != mask))
 		dev_err(params_vdev->dev->dev, "ynr cnr sharp no enable together\n");
+	if (module_ens & ISP39_MODULE_YUVME && !(module_ens & ISP39_MODULE_BAY3D))
+		dev_err(params_vdev->dev->dev, "yuvme need bay3d enable together\n");
 	v4l2_dbg(4, rkisp_debug, &params_vdev->dev->v4l2_dev,
 		 "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
 		 __func__, id, new_params->frame_id, module_en_update, module_ens);
@@ -4922,7 +4929,7 @@ rkisp_params_disable_isp_v39(struct rkisp_isp_params_vdev *params_vdev)
 	int i;

 	params_vdev->isp39_params->module_ens = 0;
-	params_vdev->isp39_params->module_en_update = 0x7ffffffffff;
+	params_vdev->isp39_params->module_en_update = ~ISP39_MODULE_FORCE;

 	for (i = 0; i < params_vdev->dev->unite_div; i++) {
 		__isp_isr_other_en(params_vdev, params_vdev->isp39_params, RKISP_PARAMS_ALL, i);
--- a/drivers/media/platform/rockchip/isp/procfs.c
+++ b/drivers/media/platform/rockchip/isp/procfs.c
@@ -12,6 +12,7 @@
 #include "regs_v2x.h"
 #include "isp_params_v3x.h"
 #include "isp_params_v32.h"
+#include "isp_params_v39.h"

 #ifdef CONFIG_PROC_FS

@@ -830,6 +831,7 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p)

 static void isp39_show(struct rkisp_device *dev, struct seq_file *p)
 {
+	struct rkisp_isp_params_val_v39 *priv = dev->params_vdev.priv_val;
 	u32 full_range_flg = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
 	static const char * const effect[] = { "OFF", "BLACKWHITE" };
 	u32 val, val1, val2;
@@ -869,27 +871,38 @@ static void isp39_show(struct rkisp_device *dev, struct seq_file *p)
 	seq_printf(p, "%-10s %s(0x%x)\n", "HDRDRC", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "HDRMGE", (val & 1) ? "ON" : "OFF", val);
+	val = rkisp_read(dev, ISP3X_DHAZ_CTRL, false);
+	val1 = rkisp_read(dev, ISP39_DHAZ_THUMB_SIZE, false);
+	seq_printf(p, "%-10s %s(0x%x) contrast:%d hist:%d enhance:%d blk(row:%d col:%d)\n",
+		   "DHAZ", (val & 1) ? "ON" : "OFF", val,
+		   !!(val & BIT(4)), !!(val & BIT(8)), !!(val & BIT(20)),
+		   val1 & 0x1f, (val1 & 0x1f00) >> 8);
 	val = rkisp_read(dev, ISP3X_BAY3D_CTRL, false);
 	val1 = rkisp_read(dev, ISP39_BAY3D_CTRL1, false);
 	val2 = rkisp_read(dev, ISP39_BAY3D_CTRL2, false);
-	seq_printf(p, "%-10s %s(0x%x 0x%x 0x%x)\n", "BAY3D",
-		   (val & 1) ? "ON" : "OFF", val, val1, val2);
+	seq_printf(p, "%-10s %s(0x%x 0x%x 0x%x) bypass:%d iirsparse:%d size:%d\n",
+		   "BAY3D", (val & 1) ? "ON" : "OFF", val, val1, val2,
+		   !!(val & BIT(1)), !!(val & BIT(2)),
+		   priv ? priv->buf_3dnr_iir.size : 0);
+	val = rkisp_read(dev, ISP39_YUVME_CTRL, false);
+	seq_printf(p, "%-10s %s(0x%x) bypass:%d size:%d\n",
+		   "YUVME", (val & 1) ? "ON" : "OFF", val, !!(val & BIT(1)),
+		   priv ? priv->buf_3dnr_cur.size : 0);
 	val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
-	seq_printf(p, "%-10s %s(0x%x)\n", "YNR", (val & 1) ? "ON" : "OFF", val);
+	seq_printf(p, "%-10s %s(0x%x) bypass(lospnr:%d hispnr:%d)\n",
+		   "YNR", (val & 1) ? "ON" : "OFF", val,
+		   !!(val & BIT(1)), !!(val & BIT(2)));
 	val = rkisp_read(dev, ISP3X_CNR_CTRL, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "CNR", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP3X_SHARP_EN, false);
-	seq_printf(p, "%-10s %s(0x%x)\n", "SHARP", (val & 1) ? "ON" : "OFF", val);
-	val = rkisp_read(dev, ISP3X_DHAZ_CTRL, false);
-	seq_printf(p, "%-10s %s(0x%x)\n", "DHAZ", (val & 1) ? "ON" : "OFF", val);
+	seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "SHARP",
+		   (val & 1) ? "ON" : "OFF", val, !!(val & BIT(1)));
 	val = rkisp_read(dev, ISP3X_3DLUT_CTRL, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "3DLUT", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP3X_LDCH_STS, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "LDCH", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP39_LDCV_CTRL, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "LDCV", (val & 1) ? "ON" : "OFF", val);
-	val = rkisp_read(dev, ISP39_YUVME_CTRL, false);
-	seq_printf(p, "%-10s %s(0x%x)\n", "YUVME", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP39_RGBIR_CTRL, false);
 	seq_printf(p, "%-10s %s(0x%x)\n", "RGBIR", (val & 1) ? "ON" : "OFF", val);
 	val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
--- a/drivers/mfd/rkx110_x120/rkx120_pwm.c
+++ b/drivers/mfd/rkx110_x120/rkx120_pwm.c
@@ -395,3 +395,5 @@ static struct platform_driver rkx120_pwm_driver = {
 	.remove = rkx120_pwm_remove,
 };
 module_platform_driver(rkx120_pwm_driver);
+
+MODULE_LICENSE("GPL");
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -341,6 +341,7 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
 	.pwr_w_mask = (pwr) << 16,			\
 	.pwr_mask = (pwr),				\
 	.status_mask = (status),			\
+	.mem_status_mask = (r_status),			\
 	.repair_status_mask = (r_status),		\
 	.req_offset = r_offset,				\
 	.req_w_mask = (req) << 16,			\
@@ -2287,6 +2288,9 @@ static const struct rockchip_pmu_info rk3568_pmu = {
 static const struct rockchip_pmu_info rk3576_pmu = {
 	.pwr_offset = 0x210,
 	.status_offset = 0x230,
+	.chain_status_offset = 0x248,
+	.mem_status_offset = 0x250,
+	.mem_pwr_offset = 0x300,
 	.req_offset = 0x110,
 	.idle_offset = 0x128,
 	.ack_offset = 0x120,
--- a/drivers/video/rockchip/mpp/mpp_rkvdec2.c
+++ b/drivers/video/rockchip/mpp/mpp_rkvdec2.c
@@ -1416,15 +1416,31 @@ static int rkvdec_vdpu383_reset(struct mpp_dev *mpp)
 {
 	struct rkvdec2_dev *dec = to_rkvdec2_dev(mpp);
 	struct rkvdec_link_dev *link = dec->link_dec;
+	int ret = 0;
+	u32 irq_status = 0;

 	mpp_debug_enter();

+	/* disable irq */
+	writel(link->info->ip_en_val & BIT(15), link->reg_base + link->info->ip_en_base);
 	/* use ip reset to reset core and mmu */
 	writel(link->info->ip_reset_en, link->reg_base + link->info->ip_reset_base);
-	udelay(5);
+	ret = readl_relaxed_poll_timeout(link->reg_base + link->info->status_base,
+					 irq_status,
+					 irq_status & 0x800,
+					 0, 200);
+	if (ret)
+		dev_err(mpp->dev, "reset timeout\n");
 	/* clear reset ready status bit */
 	writel(link->info->ip_reset_mask, link->reg_base + link->info->status_base);

+	/* clear irq and status */
+	writel_relaxed(0xffff0000, link->reg_base + link->info->irq_base);
+	writel_relaxed(0xffff0000, link->reg_base + link->info->status_base);
+
+	/* enable irq */
+	writel(link->info->ip_en_val, link->reg_base + link->info->ip_en_base);
+
 	mpp_debug_leave();

 	return 0;
@@ -2011,6 +2027,14 @@ static int __maybe_unused rkvdec2_runtime_suspend(struct device *dev)
 				disable_irq(mpp->iommu_info->irq);
 		}

+		/*
+		 * to ensure hardware is fully idle,
+		 * reset and wait for reset ready before suspend.
+		 */
+		if (mpp->hw_ops->reset)
+			mpp->hw_ops->reset(mpp);
+		mpp_iommu_refresh(mpp->iommu_info, mpp->dev);
+
 		if (mpp->hw_ops->clk_off)
 			mpp->hw_ops->clk_off(mpp);
 	}
--- a/include/dt-bindings/clock/rockchip,rk3576-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
@@ -553,6 +553,10 @@
 #define ACLK_CRYPTO_NS			551
 #define CLK_PKA_CRYPTO_NS		552
 #define ACLK_RKVDEC_ROOT_BAK		553
+#define CLK_AUDIO_FRAC_0_SRC		554
+#define CLK_AUDIO_FRAC_1_SRC		555
+#define CLK_AUDIO_FRAC_2_SRC		556
+#define CLK_AUDIO_FRAC_3_SRC		557

 /* secure clk */
 #define CLK_STIMER0_ROOT		600