From f18548643d9bdd874b1c69df2807ec134dc5eda7 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Thu, 28 Dec 2017 16:17:21 +0800 Subject: [PATCH] serial: 8250_dw: set CPR 0x00023ff2 if it is 0 The UART CPR may be 0 of some rockchip soc, but it supports fifo and AFC, fifo entry is 32 default. Change-Id: I44f420c556f703c2848c38dc8449546274ef887d Signed-off-by: Huibin Hong --- drivers/tty/serial/8250/8250_dw.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index d31b975dd3fd..6b854237c788 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -472,6 +472,15 @@ static void dw8250_setup_port(struct uart_port *p) } reg = dw8250_readl_ext(p, DW_UART_CPR); + +#ifdef CONFIG_ARCH_ROCKCHIP + /* + * The UART CPR may be 0 of some rockchip soc, + * but it supports fifo and AFC, fifo entry is 32 default. + */ + if (reg == 0) + reg = 0x00023ff2; +#endif if (!reg) return; @@ -480,6 +489,9 @@ static void dw8250_setup_port(struct uart_port *p) p->type = PORT_16550A; p->flags |= UPF_FIXED_TYPE; p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); +#ifdef CONFIG_ARCH_ROCKCHIP + up->tx_loadsz = p->fifosize * 3 / 4; +#endif up->capabilities = UART_CAP_FIFO; }