From f1a4a909e6e2ab74b4de630322ef9ae386aed54c Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Fri, 21 Jun 2024 17:35:18 +0800
Subject: [PATCH] ARM: dts: rk3506: Add SAIx_MCLK{OUT,IN} nodes

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iab05e8dfa9745c39a4e1e221bac69db7a40cf42b
---
 arch/arm/boot/dts/rk3506.dtsi | 67 +++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi
index 5f5bfe0da0a1..a41c39b8a114 100644
--- a/arch/arm/boot/dts/rk3506.dtsi
+++ b/arch/arm/boot/dts/rk3506.dtsi
@@ -40,6 +40,9 @@
 
 	clocks {
 		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
 
 		clk_rc: clk-rc {
 			compatible = "fixed-clock";
@@ -61,6 +64,70 @@
 			clock-frequency = <32768>;
 			clock-output-names = "xin32k";
 		};
+
+		mclkin_sai0: mclkin-sai0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sai0_mclk_in";
+		};
+
+		mclkin_sai1: mclkin-sai1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sai1_mclk_in";
+		};
+
+		mclkin_sai2: mclkin-sai2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sai2_mclk_in";
+		};
+
+		mclkin_sai3: mclkin-sai3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sai3_mclk_in";
+		};
+
+		mclkout_sai0: mclkout-sai0@ff910004 {
+			compatible = "rockchip,clk-out";
+			reg = <0xff910004 0x4>;
+			clocks = <&cru MCLK_OUT_SAI0>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai0_to_io";
+			rockchip,bit-shift = <8>;
+		};
+
+		mclkout_sai1: mclkout-sai1@ff910004 {
+			compatible = "rockchip,clk-out";
+			reg = <0xff910004 0x4>;
+			clocks = <&cru MCLK_OUT_SAI1>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai1_to_io";
+			rockchip,bit-shift = <9>;
+		};
+
+		mclkout_sai2: mclkout-sai2@ff288004 {
+			compatible = "rockchip,clk-out";
+			reg = <0xff288004 0x4>;
+			clocks = <&cru MCLK_OUT_SAI2>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai2_to_io";
+			rockchip,bit-shift = <2>;
+		};
+
+		mclkout_sai3: mclkout-sai3@ff288004 {
+			compatible = "rockchip,clk-out";
+			reg = <0xff288004 0x4>;
+			clocks = <&cru MCLK_OUT_SAI3>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai3_to_io";
+			rockchip,bit-shift = <3>;
+		};
 	};
 
 	cpus {