From f1bd21e650b30645c40ba9e707cb76e97f0ca15b Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Tue, 18 Jun 2024 14:48:00 +0800
Subject: [PATCH] ARM: dts: RK3506: add wdt0/wdt1/saradc

Change-Id: Ic50718f3c852cd33566acb71610556bc9f0bd0b8
Signed-off-by: Simon Xue <xxm@rock-chips.com>
---
 arch/arm/boot/dts/rk3506.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi
index fbd2bee5a95b..ff5a1d48be52 100644
--- a/arch/arm/boot/dts/rk3506.dtsi
+++ b/arch/arm/boot/dts/rk3506.dtsi
@@ -391,6 +391,24 @@
 		status = "disabled";
 	};
 
+	wdt0: watchdog@ff260000 {
+		compatible = "snps,dw-wdt";
+		reg = <0xff260000 0x100>;
+		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+		clock-names = "tclk", "pclk";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	wdt1: watchdog@ff268000 {
+		compatible = "snps,dw-wdt";
+		reg = <0xff268000 0x100>;
+		clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>;
+		clock-names = "tclk", "pclk";
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
 	grf: syscon@ff288000 {
 		compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd";
 		reg = <0xff288000 0x4000>;
@@ -578,6 +596,18 @@
 		status = "disabled";
 	};
 
+	saradc: adc@ff4e8000 {
+		compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc";
+		reg = <0xff4e8000 0x8000>;
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@ff581000 {
 		compatible = "arm,gic-400";
 		reg = <0xff581000 0x1000>,