diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 55d856f57211..c53849c03a66 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -47,43 +47,49 @@ }; }; - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5640-codec"; - simple-audio-card,mclk-fs = <512>; + rt5640_sound: rt5640-sound { status = "okay"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&i2s>; - }; - - codec { - sound-dai = <&rt5640>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&i2s>; - }; - - codec { - sound-dai = <&hdmi>; - }; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rt5640"; + hp-det-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 2>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&i2s>; + rockchip,codec = <&rt5640>; + rockchip,audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "Speaker", "SPOLP", + "Speaker", "SPOLN", + "Speaker", "SPORP", + "Speaker", "SPORN", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "DMIC L1", "Main Mic", + "DMIC R1", "Main Mic", + "IN3P", "Headset Mic", + "Headset Mic", "MICBIAS1"; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; }; }; - hdmi_analog_sound: hdmi-analog-sound { - compatible = "rockchip,rk3288-hdmi-analog", - "rockchip,rk3368-hdmi-analog"; - rockchip,model = "rockchip,rt5640-codec"; - rockchip,cpu = <&i2s>; - rockchip,codec = <&rt5640>, <&hdmi>; + hdmi_sound: hdmi-sound { status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <256>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; }; backlight: backlight { @@ -368,8 +374,6 @@ reg = <0x1c>; clocks = <&cru SCLK_I2S0_OUT>; clock-names = "mclk"; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; }; diff --git a/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts index 258cff792f76..255b4eefe5e4 100644 --- a/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts +++ b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts @@ -117,6 +117,14 @@ status = "okay"; }; +&ramdisk_r { + reg = <0x12ec000 (15 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x21ec000 (7 * 0x00100000)>; +}; + &sdmmc { max-frequency = <50000000>; bus-width = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi index 228081882c8c..bf9b4ca8d9a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi @@ -120,7 +120,7 @@ #gpio-cells = <2>; #clock-cells = <1>; clock-output-names = "rk805-clkout1", "rk805-clkout2"; - rk805,system-power-controoler; + rockchip,system-power-controller; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index 63b8833f93df..a90ff4e4ef86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -1857,8 +1857,8 @@ &vop { status = "okay"; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; }; &vop_mmu { diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index ce5a1c013865..acfdb52213ce 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -949,7 +949,6 @@ CONFIG_NVMEM_ROCKCHIP_EFUSE=y CONFIG_NVMEM_ROCKCHIP_OTP=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_RK_NAND=y CONFIG_RK_HEADSET=y CONFIG_ROCKCHIP_RKNPU=y CONFIG_EXT4_FS=y diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index ae95fb5b3d3a..f844376b2f28 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1883,6 +1883,7 @@ static const struct vop2_cluster_regs rk3568_vop_cluster0 = { .afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1), .enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0), .lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4), + .frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31), .src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0), .dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0), .src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0), @@ -1893,6 +1894,7 @@ static const struct vop2_cluster_regs rk3568_vop_cluster1 = { .afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1), .enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0), .lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4), + .frm_reset_en = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 31), .src_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL, 0xffffffff, 0), .dst_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_COLOR_CTRL, 0xffffffff, 0), .src_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0), @@ -1903,6 +1905,7 @@ static const struct vop2_cluster_regs rk3588_vop_cluster2 = { .afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1), .enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0), .lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4), + .frm_reset_en = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 31), .src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0), .dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0), .src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0), @@ -1913,6 +1916,7 @@ static const struct vop2_cluster_regs rk3588_vop_cluster3 = { .afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1), .enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0), .lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4), + .frm_reset_en = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 31), .src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0), .dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0), .src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0), diff --git a/drivers/media/i2c/gc2093.c b/drivers/media/i2c/gc2093.c index 44e7aa14b0f6..d8651a27b59b 100644 --- a/drivers/media/i2c/gc2093.c +++ b/drivers/media/i2c/gc2093.c @@ -82,6 +82,8 @@ #define GC2093_LANES 2 +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" + static const char * const gc2093_supply_names[] = { "dovdd", /* Digital I/O power */ "avdd", /* Analog power */ @@ -142,7 +144,6 @@ struct gc2093 { struct mutex lock; bool streaming; bool power_on; - unsigned int cfg_num; const struct gc2093_mode *cur_mode; u32 module_index; @@ -421,6 +422,138 @@ static const struct reg_sequence gc2093_1080p_hdr_settings[] = { {0x024d, 0x01}, }; +/* + * window size=1920*1080 mipi@2lane + * mclk=27M mipi_clk=792Mbps + * pixel_line_total=2640 line_frame_total=1500 + * row_time=20us frame_rate=50fps + */ +static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = { + /* System */ + {0x03fe, 0x80}, + {0x03fe, 0x80}, + {0x03fe, 0x80}, + {0x03fe, 0x00}, + {0x03f2, 0x00}, + {0x03f3, 0x00}, + {0x03f4, 0x36}, + {0x03f5, 0xc0}, + {0x03f6, 0x0B}, + {0x03f7, 0x01}, + {0x03f8, 0x58}, + {0x03f9, 0x40}, + {0x03fc, 0x8e}, + /* Cisctl & Analog */ + {0x0087, 0x18}, + {0x00ee, 0x30}, + {0x00d0, 0xbf}, + {0x01a0, 0x00}, + {0x01a4, 0x40}, + {0x01a5, 0x40}, + {0x01a6, 0x40}, + {0x01af, 0x09}, + {0x0001, 0x00}, + {0x0002, 0x02}, + {0x0003, 0x04}, + {0x0004, 0x02}, + {0x0005, 0x02}, + {0x0006, 0x94}, + {0x0007, 0x00}, + {0x0008, 0x11}, + {0x0009, 0x00}, + {0x000a, 0x02}, + {0x000b, 0x00}, + {0x000c, 0x04}, + {0x000d, 0x04}, + {0x000e, 0x40}, + {0x000f, 0x07}, + {0x0010, 0x8c}, + {0x0013, 0x15}, + {0x0019, 0x0c}, + {0x0041, 0x05}, + {0x0042, 0xdc}, + {0x0053, 0x60}, + {0x008d, 0x92}, + {0x0090, 0x00}, + {0x00c7, 0xe1}, + {0x001b, 0x73}, + {0x0028, 0x0d}, + {0x0029, 0x24}, + {0x002b, 0x04}, + {0x002e, 0x23}, + {0x0037, 0x03}, + {0x0043, 0x04}, + {0x0044, 0x20}, + {0x004a, 0x01}, + {0x004b, 0x20}, + {0x0055, 0x30}, + {0x006b, 0x44}, + {0x0077, 0x00}, + {0x0078, 0x20}, + {0x007c, 0xa1}, + {0x00d3, 0xd4}, + {0x00e6, 0x50}, + /* Gain */ + {0x00b6, 0xc0}, + {0x00b0, 0x60}, + /* Isp */ + {0x0102, 0x89}, + {0x0104, 0x01}, + {0x010e, 0x01}, + {0x0158, 0x00}, + {0x0183, 0x01}, + {0x0187, 0x50}, + /* Dark sun*/ + {0x0123, 0x08}, + {0x0123, 0x00}, + {0x0120, 0x01}, + {0x0121, 0x00}, + {0x0122, 0x10}, + {0x0124, 0x03}, + {0x0125, 0xff}, + {0x0126, 0x3c}, + {0x001a, 0x8c}, + {0x00c6, 0xe0}, + /* Blk */ + {0x0026, 0x30}, + {0x0142, 0x00}, + {0x0149, 0x1e}, + {0x014a, 0x0f}, + {0x014b, 0x00}, + {0x0155, 0x00}, + {0x0414, 0x78}, + {0x0415, 0x78}, + {0x0416, 0x78}, + {0x0417, 0x78}, + {0x0454, 0x78}, + {0x0455, 0x78}, + {0x0456, 0x78}, + {0x0457, 0x78}, + {0x04e0, 0x18}, + /* Window */ + {0x0192, 0x02}, + {0x0194, 0x03}, + {0x0195, 0x04}, + {0x0196, 0x38}, + {0x0197, 0x07}, + {0x0198, 0x80}, + /* MIPI */ + {0x019a, 0x06}, + {0x007b, 0x2a}, + {0x0023, 0x2d}, + {0x0201, 0x27}, + {0x0202, 0x56}, + {0x0203, 0xb6}, + {0x0212, 0x80}, + {0x0213, 0x07}, + {0x0215, 0x12}, + {0x003e, 0x91}, + /* HDR En */ + {0x0027, 0x71}, + {0x0215, 0x92}, + {0x024d, 0x01}, +}; + static const struct gc2093_mode supported_modes[] = { { .width = 1920, @@ -457,6 +590,25 @@ static const struct gc2093_mode supported_modes[] = { .vc[PAD2] = 1, .vc[PAD3] = 1,//M->csi wr2 }, + { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 250000, + }, + .exp_def = 0x460, + .hts_def = 0xa50, + .vts_def = 0x5dc, + .link_freq_index = LINK_FREQ_396M_INDEX, + .reg_list = gc2093_1080p_25fps_hdr_settings, + .reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings), + .hdr_mode = HDR_X2, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 + .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 + }, }; /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ @@ -585,6 +737,7 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_EXPOSURE: + dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val); if (gc2093->cur_mode->hdr_mode != NO_HDR) goto ctrl_end; dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val); @@ -594,28 +747,36 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val & 0xff); break; case V4L2_CID_ANALOGUE_GAIN: + dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n", + ctrl->val, gc2093->cur_mode->hdr_mode); if (gc2093->cur_mode->hdr_mode != NO_HDR) goto ctrl_end; dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val); gc2093_set_gain(gc2093, ctrl->val); break; case V4L2_CID_VBLANK: + dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val); vts = gc2093->cur_mode->height + ctrl->val; gc2093->cur_vts = vts; ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H, (vts >> 8) & 0x3f); ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L, vts & 0xff); - gc2093_modify_fps_info(gc2093); + if (!ret) + gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height; + if (gc2093->cur_vts != gc2093->cur_mode->vts_def) + gc2093_modify_fps_info(gc2093); dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val); break; case V4L2_CID_HFLIP: - regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG, - MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0); + dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val); + regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG, + MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0); break; case V4L2_CID_VFLIP: - regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG, - FLIP_MASK, ctrl->val ? FLIP_MASK : 0); + dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val); + regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG, + FLIP_MASK, ctrl->val ? FLIP_MASK : 0); break; default: dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n", @@ -672,7 +833,7 @@ static int gc2093_initialize_controls(struct gc2093 *gc2093) h_blank, h_blank, 1, h_blank); if (gc2093->hblank) gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; - + gc2093->cur_fps = mode->max_fps; vblank_def = mode->vts_def - mode->height; gc2093->cur_vts = mode->vts_def; gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops, @@ -819,11 +980,24 @@ static void gc2093_get_module_inf(struct gc2093 *gc2093, strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module)); } +static int gc2093_get_channel_info(struct gc2093 *gc2093, + struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + ch_info->vc = gc2093->cur_mode->vc[ch_info->index]; + ch_info->width = gc2093->cur_mode->width; + ch_info->height = gc2093->cur_mode->height; + ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT; + return 0; +} + static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) { struct gc2093 *gc2093 = to_gc2093(sd); struct preisp_hdrae_exp_s *hdrae_exp = arg; struct rkmodule_hdr_cfg *hdr_cfg; + struct rkmodule_channel_info *ch_info; long ret = 0; u32 i, h, w; u32 stream = 0; @@ -913,15 +1087,18 @@ static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) hdr_cfg = (struct rkmodule_hdr_cfg *)arg; w = gc2093->cur_mode->width; h = gc2093->cur_mode->height; - for (i = 0; i < gc2093->cfg_num; i++) { + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { if (w == supported_modes[i].width && h == supported_modes[i].height && supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) { gc2093->cur_mode = &supported_modes[i]; break; } + dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n", + i, supported_modes[i].width, supported_modes[i].height, + supported_modes[i].hdr_mode); } - if (i == gc2093->cfg_num) { + if (i == ARRAY_SIZE(supported_modes)) { dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n", hdr_cfg->hdr_mode, w, h); ret = -EINVAL; @@ -957,6 +1134,10 @@ static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) usleep_range(delay_us, delay_us + 2000); } break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = gc2093_get_channel_info(gc2093, ch_info); + break; default: ret = -ENOIOCTLCMD; break; @@ -989,8 +1170,16 @@ static int __gc2093_start_stream(struct gc2093 *gc2093) } } } + dev_info(gc2093->dev, + "%dx%d@%d, mode %d, vts 0x%x\n", + gc2093->cur_mode->width, + gc2093->cur_mode->height, + gc2093->cur_fps.denominator / gc2093->cur_fps.numerator, + gc2093->cur_mode->hdr_mode, + gc2093->cur_vts); + dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot); return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE, - GC2093_MODE_STREAMING); + GC2093_MODE_STREAMING); } static int __gc2093_stop_stream(struct gc2093 *gc2093) @@ -1012,6 +1201,7 @@ static long gc2093_compat_ioctl32(struct v4l2_subdev *sd, struct rkmodule_inf *inf; struct rkmodule_hdr_cfg *hdr; struct preisp_hdrae_exp_s *hdrae; + struct rkmodule_channel_info *ch_info; long ret = 0; u32 stream = 0; @@ -1081,6 +1271,21 @@ static long gc2093_compat_ioctl32(struct v4l2_subdev *sd, else ret = -EFAULT; break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = gc2093_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; default: ret = -ENOIOCTLCMD; break; @@ -1099,11 +1304,17 @@ static int gc2093_s_stream(struct v4l2_subdev *sd, int on) fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator, gc2093->cur_mode->max_fps.numerator); - dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on, - gc2093->cur_mode->width, - gc2093->cur_mode->height, - fps); + dev_info(gc2093->dev, + "%dx%d@%d, mode %d, vts 0x%x\n", + gc2093->cur_mode->width, + gc2093->cur_mode->height, + gc2093->cur_fps.denominator / gc2093->cur_fps.numerator, + gc2093->cur_mode->hdr_mode, + gc2093->cur_vts); + dev_info(gc2093->dev, + "stream:%d\n, on:%d", + gc2093->streaming, on); mutex_lock(&gc2093->lock); on = !!on; if (on == gc2093->streaming) @@ -1150,7 +1361,10 @@ static int gc2093_g_frame_interval(struct v4l2_subdev *sd, struct gc2093 *gc2093 = to_gc2093(sd); const struct gc2093_mode *mode = gc2093->cur_mode; - fi->interval = mode->max_fps; + if (gc2093->streaming) + fi->interval = gc2093->cur_fps; + else + fi->interval = mode->max_fps; return 0; } @@ -1178,9 +1392,7 @@ static int gc2093_enum_frame_sizes(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { - struct gc2093 *gc2093 = to_gc2093(sd); - - if (fse->index >= gc2093->cfg_num) + if (fse->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; if (fse->code != GC2093_MEDIA_BUS_FMT) @@ -1197,9 +1409,7 @@ static int gc2093_enum_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_interval_enum *fie) { - struct gc2093 *gc2093 = to_gc2093(sd); - - if (fie->index >= gc2093->cfg_num) + if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; fie->code = GC2093_MEDIA_BUS_FMT; @@ -1395,6 +1605,136 @@ static const struct dev_pm_ops gc2093_pm_ops = { gc2093_runtime_resume, NULL) }; + +#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP +static u32 rk_cam_hdr; +static u32 rk_cam_w; +static u32 rk_cam_h; +static u32 rk_cam_fps; + +static int __init __maybe_unused rk_cam_hdr_setup(char *str) +{ + int ret = 0; + unsigned long val = 0; + + ret = kstrtoul(str, 0, &val); + if (!ret) + rk_cam_hdr = (u32)val; + else + pr_err("get rk_cam_hdr fail\n"); + return 1; +} + +static int __init __maybe_unused rk_cam_w_setup(char *str) +{ + int ret = 0; + unsigned long val = 0; + + ret = kstrtoul(str, 0, &val); + if (!ret) + rk_cam_w = (u32)val; + else + pr_err("get rk_cam_w fail\n"); + return 1; +} + +static int __init __maybe_unused rk_cam_h_setup(char *str) +{ + int ret = 0; + unsigned long val = 0; + + ret = kstrtoul(str, 0, &val); + if (!ret) + rk_cam_h = (u32)val; + else + pr_err("get rk_cam_h fail\n"); + return 1; +} + +static int __init __maybe_unused rk_cam_fps_setup(char *str) +{ + int ret = 0; + unsigned long val = 0; + + ret = kstrtoul(str, 0, &val); + if (!ret) + rk_cam_fps = (u32)val; + else + pr_err("get rk_cam_fps fail\n"); + return 1; +} + +__setup("rk_cam_hdr=", rk_cam_hdr_setup); +__setup("rk_cam_w=", rk_cam_w_setup); +__setup("rk_cam_h=", rk_cam_h_setup); +__setup("rk_cam_fps=", rk_cam_fps_setup); + +static void find_terminal_resolution(struct gc2093 *gc2093) +{ + int i = 0; + const struct gc2093_mode *mode = NULL; + const struct gc2093_mode *fit_mode = NULL; + u32 cur_fps = 0; + u32 dst_fps = 0; + u32 tmp_fps = 0; + + if (rk_cam_w == 0 || rk_cam_h == 0 || + rk_cam_fps == 0) + goto err_find_res; + + dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n", + rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps); + dst_fps = rk_cam_fps; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + mode = &supported_modes[i]; + cur_fps = mode->max_fps.denominator / mode->max_fps.numerator; + if (mode->width == rk_cam_w && mode->height == rk_cam_h && + mode->hdr_mode == rk_cam_hdr) { + if (cur_fps == dst_fps) { + gc2093->cur_mode = mode; + return; + } + if (cur_fps >= dst_fps) { + if (fit_mode) { + tmp_fps = fit_mode->max_fps.denominator / + fit_mode->max_fps.numerator; + if (tmp_fps - dst_fps > cur_fps - dst_fps) + fit_mode = mode; + } else { + fit_mode = mode; + } + } + } + } + if (fit_mode) { + gc2093->cur_mode = fit_mode; + return; + } +err_find_res: + dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!", + rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr); + gc2093->cur_mode = &supported_modes[0]; +} +#else +static void find_terminal_resolution(struct gc2093 *gc2093) +{ + u32 hdr_mode = 0; + struct device_node *node = gc2093->dev->of_node; + int i = 0; + + of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode); + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (hdr_mode == supported_modes[i].hdr_mode) { + gc2093->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) + gc2093->cur_mode = &supported_modes[0]; + +} +#endif + static int gc2093_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -1442,6 +1782,8 @@ static int gc2093_probe(struct i2c_client *client, return -EINVAL; } + find_terminal_resolution(gc2093); + gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); if (IS_ERR(gc2093->reset_gpio)) dev_warn(dev, "Failed to get reset-gpios\n"); @@ -1458,11 +1800,6 @@ static int gc2093_probe(struct i2c_client *client, mutex_init(&gc2093->lock); - /* set default mode */ - gc2093->cur_mode = &supported_modes[0]; - gc2093->cfg_num = ARRAY_SIZE(supported_modes); - gc2093->cur_vts = gc2093->cur_mode->vts_def; - sd = &gc2093->subdev; v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops); ret = gc2093_initialize_controls(gc2093); diff --git a/drivers/media/i2c/lt6911uxe.c b/drivers/media/i2c/lt6911uxe.c index 111d03a0b220..3eb692e14cd3 100644 --- a/drivers/media/i2c/lt6911uxe.c +++ b/drivers/media/i2c/lt6911uxe.c @@ -1389,15 +1389,14 @@ static long lt6911uxe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) break; case RKMODULE_SET_CSI_DPHY_PARAM: dphy_param = (struct rkmodule_csi_dphy_param *)arg; - if (dphy_param->vendor == rk3588_dcphy_param.vendor) + if (dphy_param->vendor == PHY_VENDOR_SAMSUNG) rk3588_dcphy_param = *dphy_param; dev_dbg(<6911uxe->i2c_client->dev, "sensor set dphy param\n"); break; case RKMODULE_GET_CSI_DPHY_PARAM: dphy_param = (struct rkmodule_csi_dphy_param *)arg; - if (dphy_param->vendor == rk3588_dcphy_param.vendor) - *dphy_param = rk3588_dcphy_param; + *dphy_param = rk3588_dcphy_param; dev_dbg(<6911uxe->i2c_client->dev, "sensor get dphy param\n"); break; diff --git a/drivers/media/i2c/lt7911uxc.c b/drivers/media/i2c/lt7911uxc.c index a8b70b9cb91b..1a9843658f48 100644 --- a/drivers/media/i2c/lt7911uxc.c +++ b/drivers/media/i2c/lt7911uxc.c @@ -1172,15 +1172,14 @@ static long lt7911uxc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) break; case RKMODULE_SET_CSI_DPHY_PARAM: dphy_param = (struct rkmodule_csi_dphy_param *)arg; - if (dphy_param->vendor == rk3588_dcphy_param.vendor) + if (dphy_param->vendor == PHY_VENDOR_SAMSUNG) rk3588_dcphy_param = *dphy_param; dev_dbg(<7911uxc->i2c_client->dev, "sensor set dphy param\n"); break; case RKMODULE_GET_CSI_DPHY_PARAM: dphy_param = (struct rkmodule_csi_dphy_param *)arg; - if (dphy_param->vendor == rk3588_dcphy_param.vendor) - *dphy_param = rk3588_dcphy_param; + *dphy_param = rk3588_dcphy_param; dev_dbg(<7911uxc->i2c_client->dev, "sensor get dphy param\n"); break; diff --git a/drivers/media/platform/rockchip/isp/regs_v3x.h b/drivers/media/platform/rockchip/isp/regs_v3x.h index 79c0d35e1717..af325bd17a46 100644 --- a/drivers/media/platform/rockchip/isp/regs_v3x.h +++ b/drivers/media/platform/rockchip/isp/regs_v3x.h @@ -2169,9 +2169,12 @@ #define ISP3X_CAC_LUT_MODE(x) (((x) & 0x3) << 24) /* CNR */ +#define ISP3X_CNR_THUMB_MIX_CUR_EN BIT(4) + #define ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX GENMASK(15, 12) /* YNR */ +#define ISP3X_YNR_THUMB_MIX_CUR_EN BIT(24) #define ISP3X_YNR_EN_SHD BIT(31) /* BLS */ @@ -2201,6 +2204,9 @@ /* HDRTMO */ /* HDRDRC */ +#define ISP3X_DRC_WEIPRE_FRAME_MASK GENMASK(23, 16) + +#define ISP3X_DRC_IIR_WEIGHT_MASK GENMASK(22, 16) /* HDRMGE */ diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index c3b9af95c581..e89d7392708e 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -505,7 +505,9 @@ static void rkisp_dvfs(struct rkisp_device *dev) do_div(data_rate, 1000 * 1000); /* increase margin: 25% * num */ data_rate += (data_rate >> 2) * num; - + /* one frame two-run, data double */ + if (hw->is_multi_overflow && num > 1) + data_rate *= 2; /* compare with isp clock adjustment table */ for (i = 0; i < hw->num_clk_rate_tbl; i++) if (data_rate <= hw->clk_rate_tbl[i].clk_rate) @@ -528,45 +530,36 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on) struct rkisp_hw_dev *hw = dev->hw_dev; if (on) { - /* enable bay3d and mi */ + /* enable mi */ rkisp_update_regs(dev, ISP3X_MI_WR_CTRL, ISP3X_MI_WR_CTRL); rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1); - if (dev->isp_ver == ISP_V21) { - rkisp_update_regs(dev, ISP21_BAY3D_CTRL, ISP21_BAY3D_CTRL); - } else if (dev->isp_ver == ISP_V30) { + if (dev->isp_ver == ISP_V30) { rkisp_update_regs(dev, ISP3X_MPFBC_CTRL, ISP3X_MPFBC_CTRL); rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL); - rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL); rkisp_update_regs(dev, ISP3X_SWS_CFG, ISP3X_SWS_CFG); } else if (dev->isp_ver == ISP_V32) { rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL); rkisp_update_regs(dev, ISP32_MI_BPDS_WR_CTRL, ISP32_MI_BPDS_WR_CTRL); rkisp_update_regs(dev, ISP32_MI_MPDS_WR_CTRL, ISP32_MI_MPDS_WR_CTRL); - rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL); } } else { - /* disabled bay3d and mi. rv1106 sdmmc workaround, 3a_wr no close */ + /* disabled mi. rv1106 sdmmc workaround, 3a_wr no close */ writel(CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN, hw->base_addr + ISP3X_MI_WR_CTRL); - if (dev->isp_ver == ISP_V21) { - writel(0, hw->base_addr + ISP21_BAY3D_CTRL); - } else if (dev->isp_ver == ISP_V30) { + if (dev->isp_ver == ISP_V30) { writel(0, hw->base_addr + ISP3X_MPFBC_CTRL); writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL); - writel(0, hw->base_addr + ISP3X_BAY3D_CTRL); writel(0xc, hw->base_addr + ISP3X_SWS_CFG); if (hw->is_unite) { writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL); writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL); writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL); - writel(0, hw->base_next_addr + ISP3X_BAY3D_CTRL); writel(0xc, hw->base_next_addr + ISP3X_SWS_CFG); } } else if (dev->isp_ver == ISP_V32) { writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL); writel(0, hw->base_addr + ISP32_MI_BPDS_WR_CTRL); writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL); - writel(0, hw->base_addr + ISP3X_BAY3D_CTRL); } } rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite); @@ -728,19 +721,54 @@ run_next: if (dev->sw_rd_cnt) { /* the frame first running to off mi to save bandwidth */ rkisp_multi_overflow_hdl(dev, false); - /* FST_FRAME for YNR/CNR/SHP/ADRC/DHAZ no to refer to sram info */ - val = ISP3X_YNR_FST_FRAME | ISP3X_CNR_FST_FRAME | ISP32_SHP_FST_FRAME | - ISP3X_ADRC_FST_FRAME | ISP3X_DHAZ_FST_FRAME; + + /* FST_FRAME no to read sram thumb */ + val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME; + if (dev->isp_ver == ISP_V32) + val |= ISP32_SHP_FST_FRAME; + else + val |= ISP3X_CNR_FST_FRAME; rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false, hw->is_unite); + /* ADRC low iir thumb weight for first sensor switch */ + val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN); + val &= ~ISP3X_DRC_IIR_WEIGHT_MASK; + writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN); + /* ADRC iir5x5 and cur3x3 weight */ + val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO); + val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK; + writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO); + /* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ + val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL); + val |= ISP3X_YNR_THUMB_MIX_CUR_EN; + writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL); + if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) { + /* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */ + val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL); + val |= ISP3X_CNR_THUMB_MIX_CUR_EN; + writel(val, hw->base_addr + ISP3X_CNR_CTRL); + if (hw->is_unite) + writel(val, hw->base_next_addr + ISP3X_CNR_CTRL); + } + params_vdev->rdbk_times += dev->sw_rd_cnt; stats_vdev->rdbk_drop = true; is_upd = true; } else if (is_try) { + /* the frame second running to on mi */ rkisp_multi_overflow_hdl(dev, true); rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE); - val = ISP3X_YNR_FST_FRAME | ISP3X_CNR_FST_FRAME | ISP32_SHP_FST_FRAME | - ISP3X_ADRC_FST_FRAME | ISP3X_DHAZ_FST_FRAME; + + val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME; + if (dev->isp_ver == ISP_V32) + val |= ISP32_SHP_FST_FRAME; + else + val |= ISP3X_CNR_FST_FRAME; rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false, hw->is_unite); + val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN); + writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN); + val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO); + writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO); + is_upd = true; } } @@ -805,6 +833,8 @@ run_next: val &= ~SW_IBUF_OP_MODE(0xf); tmp = SW_IBUF_OP_MODE(dev->rd_mode); val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm); + if (dev->isp_ver > ISP_V20) + dma2frm = dev->sw_rd_cnt; v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev, "readback frame:%d time:%d 0x%x\n", cur_frame_id, dma2frm + 1, val); diff --git a/drivers/video/rockchip/rga3/rga_mm.c b/drivers/video/rockchip/rga3/rga_mm.c index 1ca0d7c3501d..d261833b3ace 100644 --- a/drivers/video/rockchip/rga3/rga_mm.c +++ b/drivers/video/rockchip/rga3/rga_mm.c @@ -1302,13 +1302,6 @@ static int rga_mm_sync_dma_sg_for_device(struct rga_internal_buffer *buffer, struct sg_table *sgt; struct rga_scheduler_t *scheduler; - sgt = rga_mm_lookup_sgt(buffer); - if (sgt == NULL) { - pr_err("%s(%d), failed to get sgt, core = 0x%x\n", - __func__, __LINE__, job->core); - return -EINVAL; - } - scheduler = buffer->dma_buffer->scheduler; if (scheduler == NULL) { pr_err("%s(%d), failed to get scheduler, core = 0x%x\n", @@ -1316,7 +1309,18 @@ static int rga_mm_sync_dma_sg_for_device(struct rga_internal_buffer *buffer, return -EFAULT; } - dma_sync_sg_for_device(scheduler->dev, sgt->sgl, sgt->orig_nents, dir); + if (buffer->mm_flag & RGA_MEM_PHYSICAL_CONTIGUOUS) { + dma_sync_single_for_device(scheduler->dev, buffer->phys_addr, buffer->size, dir); + } else { + sgt = rga_mm_lookup_sgt(buffer); + if (sgt == NULL) { + pr_err("%s(%d), failed to get sgt, core = 0x%x\n", + __func__, __LINE__, job->core); + return -EINVAL; + } + + dma_sync_sg_for_device(scheduler->dev, sgt->sgl, sgt->orig_nents, dir); + } return 0; } @@ -1328,13 +1332,6 @@ static int rga_mm_sync_dma_sg_for_cpu(struct rga_internal_buffer *buffer, struct sg_table *sgt; struct rga_scheduler_t *scheduler; - sgt = rga_mm_lookup_sgt(buffer); - if (sgt == NULL) { - pr_err("%s(%d), failed to get sgt, core = 0x%x\n", - __func__, __LINE__, job->core); - return -EINVAL; - } - scheduler = buffer->dma_buffer->scheduler; if (scheduler == NULL) { pr_err("%s(%d), failed to get scheduler, core = 0x%x\n", @@ -1342,7 +1339,18 @@ static int rga_mm_sync_dma_sg_for_cpu(struct rga_internal_buffer *buffer, return -EFAULT; } - dma_sync_sg_for_cpu(scheduler->dev, sgt->sgl, sgt->orig_nents, dir); + if (buffer->mm_flag & RGA_MEM_PHYSICAL_CONTIGUOUS) { + dma_sync_single_for_cpu(scheduler->dev, buffer->phys_addr, buffer->size, dir); + } else { + sgt = rga_mm_lookup_sgt(buffer); + if (sgt == NULL) { + pr_err("%s(%d), failed to get sgt, core = 0x%x\n", + __func__, __LINE__, job->core); + return -EINVAL; + } + + dma_sync_sg_for_cpu(scheduler->dev, sgt->sgl, sgt->orig_nents, dir); + } return 0; }