From f1d8703f0caf74f4cccc25e88d615452dcbeee31 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Fri, 3 Dec 2021 15:05:25 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Add config for rk3588 sata This patch aims to configure sata for better compatibility. 1. Set ssc downward spread spectrum. 2. Enable the adaptive Continuous Time Linear Equalizer (CTLE). 3. Set ssc to 31.5KHz for 24MHz ref clk. 4. Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm. Signed-off-by: Yifeng Zhao Change-Id: Iec71d588183bf89a65d6cbce7635dd8768f2ea5d --- .../rockchip/phy-rockchip-naneng-combphy.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5188ae0541f9..61c56b64aea1 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -704,6 +704,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->usb_mode_set, true); break; case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ + writel(0x8F, priv->mmio + (0x06 << 2)); + param_write(priv->phy_grf, &cfg->con0_for_sata, true); param_write(priv->phy_grf, &cfg->con1_for_sata, true); param_write(priv->phy_grf, &cfg->con2_for_sata, true); @@ -722,7 +730,7 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) switch (rate) { case 24000000: - if (priv->mode == PHY_TYPE_USB3) { + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ val = readl(priv->mmio + (0x0e << 2)); val &= ~GENMASK(7, 6); @@ -740,6 +748,13 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) break; case 100000000: param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(7, 4); + val |= 0x50; + writel(val, priv->mmio + (0x1f << 2)); + } break; default: dev_err(priv->dev, "Unsupported rate: %lu\n", rate); @@ -768,7 +783,7 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, - .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, /* pipe-grf */