From f2467914dbf27409adcdaf4a89476368d9134e02 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Sat, 22 Mar 2025 19:42:04 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b-pinctrl: Set pull-up and drv
 strength to level 3 for sdmmc0

Change-Id: Ic789da081e2fa3defb620d4c37c7f598e748c5a5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 .../arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi
index fb59db77a644..9f3559f96edd 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi
@@ -1767,34 +1767,34 @@
 		sdmmc0_bus4_pins: sdmmc0-bus4-pins {
 			rockchip,pins =
 				/* sdmmc0_d0 */
-				<2 RK_PA0 1 &pcfg_pull_up>,
+				<2 RK_PA0 1 &pcfg_pull_up_drv_level_3>,
 				/* sdmmc0_d1 */
-				<2 RK_PA1 1 &pcfg_pull_up>,
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_3>,
 				/* sdmmc0_d2 */
-				<2 RK_PA2 1 &pcfg_pull_up>,
+				<2 RK_PA2 1 &pcfg_pull_up_drv_level_3>,
 				/* sdmmc0_d3 */
-				<2 RK_PA3 1 &pcfg_pull_up>;
+				<2 RK_PA3 1 &pcfg_pull_up_drv_level_3>;
 		};
 
 		/omit-if-no-ref/
 		sdmmc0_cmd_pins: sdmmc0-cmd-pins {
 			rockchip,pins =
 				/* sdmmc0_cmd */
-				<2 RK_PA5 1 &pcfg_pull_up>;
+				<2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
 		};
 
 		/omit-if-no-ref/
 		sdmmc0_clk_pins: sdmmc0-clk-pins {
 			rockchip,pins =
 				/* sdmmc0_clk */
-				<2 RK_PA4 1 &pcfg_pull_none>;
+				<2 RK_PA4 1 &pcfg_pull_up_drv_level_3>;
 		};
 
 		/omit-if-no-ref/
 		sdmmc0_detn_pins: sdmmc0-detn-pins {
 			rockchip,pins =
 				/* sdmmc0_detn */
-				<0 RK_PA5 1 &pcfg_pull_none>;
+				<0 RK_PA5 1 &pcfg_pull_up>;
 		};
 	};
 
@@ -1830,7 +1830,7 @@
 		sdmmc1_detn_pins: sdmmc1-detn-pins {
 			rockchip,pins =
 				/* sdmmc1_detn */
-				<3 RK_PB6 3 &pcfg_pull_none>;
+				<3 RK_PB6 3 &pcfg_pull_up>;
 		};
 	};