From f27e74f627ffa614ede7accc417b8b07dca078b3 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Fri, 26 Apr 2019 13:02:07 +0900 Subject: [PATCH] Revert "sm1: emmc run hs200 busmode [1/1]" This reverts commit 3640f39081460f23efa0cf6db1d8fe19b9c6f96b. Change-Id: If16a4473ac4d1973a83a6fed685688606ecee745 --- drivers/amlogic/mmc/aml_sd_emmc.c | 26 -------------------------- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 6 ++---- 2 files changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c index 7522ac48a7db..84f5f93c91b0 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc.c +++ b/drivers/amlogic/mmc/aml_sd_emmc.c @@ -3643,32 +3643,6 @@ static struct meson_mmc_data mmc_data_tl1 = { .sdmmc.sdr104.core_phase = 2, }; -static struct meson_mmc_data mmc_data_sm1 = { - .chip_type = MMC_CHIP_SM1, - .port_a_base = 0xffe03000, - .port_b_base = 0xffe05000, - .port_c_base = 0xffe07000, - .pinmux_base = 0xff634400, - .clksrc_base = 0xff63c000, - .ds_pin_poll = 0x3a, - .ds_pin_poll_en = 0x48, - .ds_pin_poll_bit = 13, - .sdmmc.init.core_phase = 3, - .sdmmc.init.tx_phase = 0, - .sdmmc.init.rx_phase = 0, - .sdmmc.calc.core_phase = 0, - .sdmmc.calc.tx_phase = 2, - .sdmmc.hs.core_phase = 3, - .sdmmc.ddr.core_phase = 2, - .sdmmc.ddr.tx_phase = 0, - .sdmmc.hs2.core_phase = 2, - .sdmmc.hs2.tx_phase = 0, - .sdmmc.hs4.tx_delay = 0, - .sdmmc.sd_hs.core_phase = 3, - .sdmmc.sdr104.core_phase = 2, - .sdmmc.sdr104.tx_phase = 0, -}; - static const struct of_device_id meson_mmc_of_match[] = { { .compatible = "amlogic, meson-mmc-gxbb", diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 0f02a26407f3..888e2c4272c7 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -1192,10 +1192,8 @@ tunning: nmatch = aml_sd_emmc_tuning_transfer(mmc, opcode, blk_pattern, host->blk_test, blksz); if (nmatch != TUNING_NUM_PER_POINT) { - if (host->data->chip_type != MMC_CHIP_SM1) { - clkc->core_phase = para->hs2.tx_phase; - clkc->tx_phase = para->hs2.core_phase; - } + clkc->core_phase = para->hs2.tx_phase; + clkc->tx_phase = para->hs2.core_phase; writel(vclk, host->base + SD_EMMC_CLOCK_V3); pr_info("%s:try clock:0x%x>>>rx_tuning[%d] = %d\n", mmc_hostname(host->mmc),