From f283539a10efd19fac8ae04a4dde838d5d18302d Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 8 Mar 2022 10:39:22 +0800 Subject: [PATCH] drm/rockchip: vop2: support use video port default parent When video port output image under 4K@60Hz(dclk less than 600MHz), The dclk parent use hdmi0 phy pll or hdmi1 phy pll. In some cases the hdmi0 phy pll or hdmi1 phy pll is not enough for all output interface. For example, hdmi0 and hdmi0 connect to video port0 and dp connect to video port1. In this case, It need the video port1 need use default dclk parent. Signed-off-by: Zhang Yubing Change-Id: Icdf050bb1e7a9f36022f5dd196358136c1d9242c --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index d6700487b99d..827c9a62558a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3664,8 +3664,8 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp, vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk); hdmi1_phy_pll->vp_mask |= BIT(vp->id); } else { - DRM_ERROR("No free hdmi phy pll for DP\n"); - return -EBUSY; + vop2_clk_set_parent(vp->dclk, vp->dclk_parent); + DRM_INFO("No free hdmi phy pll for DP, use default parent\n"); } } } else {