audio: VAD use HIFI PLL [1/1]

PD#SWPL-12746

Problem:
VAD does not use HIFI PLL, it will effect vad wakup

Solution:
VAD use HIFI PLL

Verify:
T962X2_X301

Change-Id: Iad13661c4ec3495130f485447f3c8b034bee9ce2
Signed-off-by: jian.zhou <jian.zhou@amlogic.com>
This commit is contained in:
jian.zhou
2019-09-11 03:59:12 -04:00
committed by Tao Zeng
parent bae244e017
commit f2e9723f1d
9 changed files with 57 additions and 56 deletions

View File

@@ -1575,8 +1575,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1680,7 +1680,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1716,8 +1716,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1771,8 +1771,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1569,8 +1569,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1674,7 +1674,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1710,8 +1710,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1765,8 +1765,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1570,8 +1570,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1675,7 +1675,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1711,8 +1711,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1766,8 +1766,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1564,8 +1564,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1669,7 +1669,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1705,8 +1705,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1760,8 +1760,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1571,8 +1571,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1676,7 +1676,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1712,8 +1712,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1767,8 +1767,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1564,8 +1564,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1669,7 +1669,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1705,8 +1705,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1760,8 +1760,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1563,8 +1563,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1668,7 +1668,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1704,8 +1704,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1759,8 +1759,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

View File

@@ -1556,8 +1556,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -1661,7 +1661,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_FCLK_DIV5
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
@@ -1697,8 +1697,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
@@ -1752,8 +1752,8 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0

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@@ -433,6 +433,7 @@ static int vad_set_clks(struct vad *p_vad, bool enable)
/* enable clock gate */
ret = clk_prepare_enable(p_vad->gate);
clk_set_rate(p_vad->pll, 25000000);
/* enable clock */
ret = clk_prepare_enable(p_vad->pll);
if (ret) {