diff --git a/drivers/media/platform/rockchip/vpss/common.c b/drivers/media/platform/rockchip/vpss/common.c
index b73b71ee5d1d..49fad005b8fd 100644
--- a/drivers/media/platform/rockchip/vpss/common.c
+++ b/drivers/media/platform/rockchip/vpss/common.c
@@ -111,6 +111,8 @@ void rkvpss_update_regs(struct rkvpss_device *dev, u32 start, u32 end)
 					mask |= (RKVPSS_ISP2VPSS_CHN0_SEL(3) << j * 2);
 				}
 				*val |= (readl(base + i) & mask);
+			} else {
+				*val |= readl(base + i);
 			}
 		}
 		writel(*val, base + i);
diff --git a/drivers/media/platform/rockchip/vpss/hw.c b/drivers/media/platform/rockchip/vpss/hw.c
index 6be54c704596..bd974b17cfeb 100644
--- a/drivers/media/platform/rockchip/vpss/hw.c
+++ b/drivers/media/platform/rockchip/vpss/hw.c
@@ -519,7 +519,8 @@ void rkvpss_soft_reset(struct rkvpss_hw_dev *hw)
 		rockchip_iommu_enable(hw->dev);
 	}
 
-	rkvpss_hw_write(hw, RKVPSS_VPSS_CTRL, RKVPSS_ACK_FRM_PRO_DIS);
+	rkvpss_hw_set_bits(hw, RKVPSS_VPSS_CTRL, RKVPSS_ACK_FRM_PRO_DIS,
+			   RKVPSS_ACK_FRM_PRO_DIS);
 	rkvpss_hw_write(hw, RKVPSS_VPSS_IRQ_CFG, 0x3fff);
 	rkvpss_hw_write(hw, RKVPSS_MI_IMSC, 0xd0000000);
 	rkvpss_hw_set_bits(hw, RKVPSS_VPSS_ONLINE, RKVPSS_ONLINE_MODE_MASK,
diff --git a/drivers/media/platform/rockchip/vpss/regs.h b/drivers/media/platform/rockchip/vpss/regs.h
index 5d9442cbb720..d73d6db5addd 100644
--- a/drivers/media/platform/rockchip/vpss/regs.h
+++ b/drivers/media/platform/rockchip/vpss/regs.h
@@ -1179,8 +1179,10 @@
 #define IS_SYNC_REG(x) ({ \
 	typeof(x) __x = (x); \
 	(__x == RKVPSS_VPSS_CTRL || __x == RKVPSS_VPSS_ONLINE || \
-	 __x == RKVPSS_VPSS_UPDATE || __x == RKVPSS_MI_WR_INIT || \
-	 __x == RKVPSS_MI_WR_WRAP_CTRL || __x == RKVPSS_MI_WR_VFLIP_CTRL); \
+	 __x == RKVPSS_VPSS_UPDATE || __x == RKVPSS_VPSS_CLK_GATE || \
+	 __x == RKVPSS_VPSS_IMSC || __x == RKVPSS_MI_WR_CTRL || \
+	 __x == RKVPSS_MI_WR_INIT || __x == RKVPSS_MI_WR_WRAP_CTRL || \
+	 __x == RKVPSS_MI_WR_VFLIP_CTRL); \
 })
 
 #endif