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UPSTREAM: tty: serial: qcom-geni-serial: align #define values

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Keep the #define symbols aligned for better readability.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20221229155030.418800-5-brgl@bgdev.pl
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Bug: 370629635
Change-Id: I70a55f560269d0d9deec4bf499ee75d07065d030
(cherry picked from commit 6cde11dbf4)
Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com>
This commit is contained in:
Bartosz Golaszewski
2022-12-29 16:50:20 +01:00
committed by John Stultz
parent b92a6c8545
commit f4eec633c0
1 changed files with 30 additions and 30 deletions
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60
drivers/tty/serial/qcom_geni_serial.c
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@@ -39,57 +39,57 @@
#define SE_UART_MANUAL_RFR 0x2ac #define SE_UART_MANUAL_RFR 0x2ac
/* SE_UART_TRANS_CFG */ /* SE_UART_TRANS_CFG */
#define UART_TX_PAR_EN BIT(0) #define UART_TX_PAR_EN BIT(0)
#define UART_CTS_MASK BIT(1) #define UART_CTS_MASK BIT(1)
/* SE_UART_TX_STOP_BIT_LEN */ /* SE_UART_TX_STOP_BIT_LEN */
#define TX_STOP_BIT_LEN_1 0 #define TX_STOP_BIT_LEN_1 0
#define TX_STOP_BIT_LEN_2 2 #define TX_STOP_BIT_LEN_2 2
/* SE_UART_RX_TRANS_CFG */ /* SE_UART_RX_TRANS_CFG */
#define UART_RX_PAR_EN BIT(3) #define UART_RX_PAR_EN BIT(3)
/* SE_UART_RX_WORD_LEN */ /* SE_UART_RX_WORD_LEN */
#define RX_WORD_LEN_MASK GENMASK(9, 0) #define RX_WORD_LEN_MASK GENMASK(9, 0)
/* SE_UART_RX_STALE_CNT */ /* SE_UART_RX_STALE_CNT */
#define RX_STALE_CNT GENMASK(23, 0) #define RX_STALE_CNT GENMASK(23, 0)
/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
#define PAR_CALC_EN BIT(0) #define PAR_CALC_EN BIT(0)
#define PAR_EVEN 0x00 #define PAR_EVEN 0x00
#define PAR_ODD 0x01 #define PAR_ODD 0x01
#define PAR_SPACE 0x10 #define PAR_SPACE 0x10
/* SE_UART_MANUAL_RFR register fields */ /* SE_UART_MANUAL_RFR register fields */
#define UART_MANUAL_RFR_EN BIT(31) #define UART_MANUAL_RFR_EN BIT(31)
#define UART_RFR_NOT_READY BIT(1) #define UART_RFR_NOT_READY BIT(1)
#define UART_RFR_READY BIT(0) #define UART_RFR_READY BIT(0)
/* UART M_CMD OP codes */ /* UART M_CMD OP codes */
#define UART_START_TX 0x1 #define UART_START_TX 0x1
/* UART S_CMD OP codes */ /* UART S_CMD OP codes */
#define UART_START_READ 0x1 #define UART_START_READ 0x1
#define UART_OVERSAMPLING 32 #define UART_OVERSAMPLING 32
#define STALE_TIMEOUT 16 #define STALE_TIMEOUT 16
#define DEFAULT_BITS_PER_CHAR 10 #define DEFAULT_BITS_PER_CHAR 10
#define GENI_UART_CONS_PORTS 1 #define GENI_UART_CONS_PORTS 1
#define GENI_UART_PORTS 3 #define GENI_UART_PORTS 3
#define DEF_FIFO_DEPTH_WORDS 16 #define DEF_FIFO_DEPTH_WORDS 16
#define DEF_TX_WM 2 #define DEF_TX_WM 2
#define DEF_FIFO_WIDTH_BITS 32 #define DEF_FIFO_WIDTH_BITS 32
#define UART_RX_WM 2 #define UART_RX_WM 2
/* SE_UART_LOOPBACK_CFG */ /* SE_UART_LOOPBACK_CFG */
#define RX_TX_SORTED BIT(0) #define RX_TX_SORTED BIT(0)
#define CTS_RTS_SORTED BIT(1) #define CTS_RTS_SORTED BIT(1)
#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
/* UART pin swap value */ /* UART pin swap value */
#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
#define IO_MACRO_IO0_SEL 0x3 #define IO_MACRO_IO0_SEL 0x3
#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
#define IO_MACRO_IO2_IO3_SWAP 0x4640 #define IO_MACRO_IO2_IO3_SWAP 0x4640
/* We always configure 4 bytes per FIFO word */ /* We always configure 4 bytes per FIFO word */