From f50cc405937158c3e2f5dd28f623ff7c34ed7294 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Wed, 3 Nov 2021 17:23:59 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588: Add dcphy rx node Signed-off-by: Zefa Chen Change-Id: Ib00a670cb021125076eb0e3c8d81a456bed7becd --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index dc4236fbf53d..67e18084f968 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -18,6 +18,8 @@ #size-cells = <2>; aliases { + csi2dcphy0 = &csi2_dcphy0; + csi2dcphy1 = &csi2_dcphy1; dsi0 = &dsi0; dsi1 = &dsi1; ethernet1 = &gmac1; @@ -270,6 +272,18 @@ <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; }; + csi2_dcphy0: csi2-dcphy0 { + compatible = "rockchip,rk3588-csi2-dcphy"; + rockchip,hw = <&csi2_dcphy0_hw>; + status = "disabled"; + }; + + csi2_dcphy1: csi2-dcphy1 { + compatible = "rockchip,rk3588-csi2-dcphy"; + rockchip,hw = <&csi2_dcphy1_hw>; + status = "disabled"; + }; + display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vop_out>; @@ -3823,6 +3837,17 @@ status = "disabled"; }; + csi2_dcphy0_hw: csi2-dcphy0-hw@feda0000 { + compatible = "rockchip,rk3588-csi2-dcphy-hw"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY0>; + clock-names = "pclk"; + resets = <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "phy"; + rockchip,grf = <&mipidcphy0_grf>; + status = "disabled"; + }; + mipi_dcphy1: phy@fedb0000 { compatible = "rockchip,rk3588-mipi-dcphy"; reg = <0x0 0xfedb0000 0x0 0x10000>; @@ -3838,6 +3863,17 @@ status = "disabled"; }; + csi2_dcphy1_hw: csi2-dcphy1-hw@fedb0000 { + compatible = "rockchip,rk3588-csi2-dcphy-hw"; + reg = <0x0 0xfedb0000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_S_MIPI_DCPHY1>; + reset-names = "phy"; + rockchip,grf = <&mipidcphy1_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>;