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usb: dwc3: core: update LC timer as per USB Spec V3.2

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commit 9149c9b0c7e046273141e41eebd8a517416144ac upstream.

This fix addresses STAR 9001285599, which only affects DWC_usb3 version
3.20a. The timer value for PM_LC_TIMER in DWC_usb3 3.20a for the Link
ECN changes is incorrect. If the PM TIMER ECN is enabled via GUCTL2[19],
the link compliance test (TD7.21) may fail. If the ECN is not enabled
(GUCTL2[19] = 0), the controller will use the old timer value (5us),
which is still acceptable for the link compliance test. Therefore, clear
GUCTL2[19] to pass the USB link compliance test: TD 7.21.

Cc: stable@vger.kernel.org
Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20240829094502.26502-1-quic_faisalh@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Faisal Hassan
2024-08-29 15:15:02 +05:30
committed by Greg Kroah-Hartman
parent 46df22d791
commit f519b04534
2 changed files with 17 additions and 0 deletions
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15
drivers/usb/dwc3/core.c
View File

@@ -1305,6 +1305,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
} }
/*
* STAR 9001285599: This issue affects DWC_usb3 version 3.20a
* only. If the PM TIMER ECM is enabled through GUCTL2[19], the
* link compliance test (TD7.21) may fail. If the ECN is not
* enabled (GUCTL2[19] = 0), the controller will use the old timer
* value (5us), which is still acceptable for the link compliance
* test. Therefore, do not enable PM TIMER ECM in 3.20a by
* setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
*/
if (DWC3_VER_IS(DWC3, 320A)) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
reg &= ~DWC3_GUCTL2_LC_TIMER;
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
}
/* /*
* When configured in HOST mode, after issuing U3/L2 exit controller * When configured in HOST mode, after issuing U3/L2 exit controller
* fails to send proper CRC checksum in CRC5 feild. Because of this * fails to send proper CRC checksum in CRC5 feild. Because of this

2
drivers/usb/dwc3/core.h
View File

@@ -404,6 +404,7 @@
/* Global User Control Register 2 */ /* Global User Control Register 2 */
#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
#define DWC3_GUCTL2_LC_TIMER BIT(19)
/* Global User Control Register 3 */ /* Global User Control Register 3 */
#define DWC3_GUCTL3_SPLITDISABLE BIT(14) #define DWC3_GUCTL3_SPLITDISABLE BIT(14)
@@ -1232,6 +1233,7 @@ struct dwc3 {
#define DWC3_REVISION_290A 0x5533290a #define DWC3_REVISION_290A 0x5533290a
#define DWC3_REVISION_300A 0x5533300a #define DWC3_REVISION_300A 0x5533300a
#define DWC3_REVISION_310A 0x5533310a #define DWC3_REVISION_310A 0x5533310a
#define DWC3_REVISION_320A 0x5533320a
#define DWC3_REVISION_330A 0x5533330a #define DWC3_REVISION_330A 0x5533330a
#define DWC31_REVISION_ANY 0x0 #define DWC31_REVISION_ANY 0x0