From f55add63e6330f5dfd491da4d246cb870a8e50f1 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 10 Nov 2020 09:43:16 +0800 Subject: [PATCH] clk: rockchip: rk3568: support hdmi setting clk Note: Dclk_vop0, exclusive HPLL, DCLK_VOP0 and HPLL is 1:1 relationship. dts need setting parent as: assigned-clocks = <&cru DCLK_VOP0>; assigned-clock-parents = <&pmucru PLL_HPLL>; Dclk_vop1, exclusive VPLL, DCLK_VOP1 and VPLL is 1:n relationship. n = DIV_ROUND_UP(600M, DCLk_rate) dts need setting parent as: assigned-clocks = <&cru DCLK_VOP1>; assigned-clock-parents = <&cru PLL_VPLL>; Dclk_vop2, no exclusive PLL, GPLL\CPLL\VPLL or HPLL near frequency division. Signed-off-by: Elaine Zhang Change-Id: I3172025737e544c8989ab9fabe0e7ba06d6db1db --- drivers/clk/rockchip/clk-rk3568.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 396af0e21616..1bcb073d6a13 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -79,8 +79,10 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), { /* sentinel */ }, }; @@ -1078,12 +1080,12 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(20), 8, GFLAGS), GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, RK3568_CLKGATE_CON(20), 9, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 0, + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS), - COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 0, + COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 11, GFLAGS), + RK3568_CLKGATE_CON(20), 11, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE), COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 12, GFLAGS),