From f58cc2736aa4811b30b2a02ea4ffae83ea66c834 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 25 Apr 2025 12:19:26 +0800 Subject: [PATCH] arm64: dts: rockchip: rv1126b-evb: Change clock rates to 24M for fephy Change-Id: I906b8a3e483f6db790701a10d6a0aa71080948bc Signed-off-by: David Wu --- arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts | 2 +- arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi index 5c3fed632304..262b8c2674a2 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi @@ -325,7 +325,7 @@ compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22"; reg = <2>; clocks = <&cru CLK_MACPHY>; - clock-frequency = <50000000>; + clock-frequency = <24000000>; resets = <&cru SRST_RESETN_MACPHY>; pinctrl-names = "default"; pinctrl-0 = <&fephym1_pins>; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts index f3a7677ba283..24d56147893f 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts @@ -320,7 +320,7 @@ compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22"; reg = <2>; clocks = <&cru CLK_MACPHY>; - clock-frequency = <50000000>; + clock-frequency = <24000000>; resets = <&cru SRST_RESETN_MACPHY>; pinctrl-names = "default"; pinctrl-0 = <&fephym2_pins>; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts b/arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts index 7655959ea5ef..4f3ea4610f34 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rv1126b-iotest-v10.dts @@ -129,7 +129,7 @@ compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22"; reg = <2>; clocks = <&cru CLK_MACPHY>; - clock-frequency = <50000000>; + clock-frequency = <24000000>; resets = <&cru SRST_RESETN_MACPHY>; phy-is-integrated; };