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emmc: modify cophase for tl1 [1/1]

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PD#172587

Problem:
emmc data crc error

Solution:
modify cophase under kernel for tl1

Verify:
test pass on skt

Change-Id: Id4997ef2288a53e6f401744664aaf6b05cf36e38
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>

Conflicts:
	arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
This commit is contained in:
Ruixuan Li
2018-11-26 20:53:39 +08:00
committed by Dongjin Kim
parent cd3580450b
commit f5c42df116
4 changed files with 34 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
View File

@@ -1443,34 +1443,6 @@
};
}; /* end of pinctrl_aobus */
&audio_data{
status = "okay";
};
&i2c2 {
status = "okay";
pinctrl-names="default";
pinctrl-0=<&i2c2_z_pins>;
clock-frequency = <400000>;
tas5805: tas5805@36 {
compatible = "ti,tas5805";
#sound-dai-cells = <0>;
codec_name = "tas5805";
reg = <0x2d>;
status = "disable";
};
ad82584f: ad82584f@62 {
compatible = "ESMT, ad82584f";
#sound-dai-cells = <0>;
reg = <0x31>;
status = "okay";
reset_pin = <&gpio_ao GPIOAO_6 0>;
};
};
&sd_emmc_c {
status = "okay";
emmc {

18
arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
View File

@@ -1529,6 +1529,24 @@
};
};
&sd_emmc_c {
status = "okay";
emmc {
caps = "MMC_CAP_8_BIT_DATA",
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
/* "MMC_CAP_1_8V_DDR", */
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <200000000>;
};
};
&sd_emmc_b {
status = "okay";
sd {

2
drivers/amlogic/mmc/aml_sd_emmc.c
View File

@@ -3648,7 +3648,7 @@ static struct meson_mmc_data mmc_data_tl1 = {
.sdmmc.init.core_phase = 3,
.sdmmc.init.tx_phase = 0,
.sdmmc.init.rx_phase = 0,
.sdmmc.hs.core_phase = 1,
.sdmmc.hs.core_phase = 3,
.sdmmc.ddr.core_phase = 2,
.sdmmc.hs2.core_phase = 2,
.sdmmc.hs4.tx_delay = 0,

18
drivers/amlogic/mmc/aml_sd_emmc_v3.c
View File

@@ -116,6 +116,7 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host)
u32 vconf = 0;
struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf;
struct mmc_phase *init = &(host->data->sdmmc.init);
struct mmc_phase *calc = &(host->data->sdmmc.calc);
writel(0, host->base + SD_EMMC_ADJUST_V3);
writel(0, host->base + SD_EMMC_DELAY1_V3);
@@ -133,6 +134,11 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host)
pclkc->core_phase = init->core_phase; /* 2: 180 phase */
pclkc->rx_phase = init->rx_phase;
pclkc->tx_phase = init->tx_phase;
if ((host->data->chip_type >= MMC_CHIP_G12A)
&& (host->data->chip_type != MMC_CHIP_TL1)) {
pclkc->core_phase = calc->core_phase;
pclkc->tx_phase = calc->tx_phase;
}
pclkc->always_on = 1; /* Keep clock always on */
writel(vclkc, host->base + SD_EMMC_CLOCK_V3);
@@ -369,7 +375,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
/* overide co-phase by dts */
if (pdata->co_phase)
clkc->core_phase = pdata->co_phase;
if (pdata->calc_f) {
if ((pdata->calc_f)
&& ((host->data->chip_type >= MMC_CHIP_G12A)
&& (host->data->chip_type != MMC_CHIP_TL1))) {
clkc->core_phase = para->calc.core_phase;
clkc->tx_phase = para->calc.tx_phase;
}
@@ -381,7 +389,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
|| (host->data->chip_type == MMC_CHIP_TXLX)
|| (host->data->chip_type == MMC_CHIP_G12A))
clkc->core_phase = para->sd_hs.core_phase;
if (pdata->calc_f) {
if ((pdata->calc_f)
&& ((host->data->chip_type >= MMC_CHIP_G12A)
&& (host->data->chip_type != MMC_CHIP_TL1))) {
clkc->core_phase = para->calc.core_phase;
clkc->tx_phase = para->calc.tx_phase;
}
@@ -397,7 +407,9 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
}
}
if (pdata->calc_f) {
if ((pdata->calc_f)
&& ((host->data->chip_type >= MMC_CHIP_G12A)
&& (host->data->chip_type != MMC_CHIP_TL1))) {
if (timing <= MMC_TIMING_SD_HS) {
ret = aml_fixdiv_calc(&fixdiv, &pdata->clk_lay);
if (!ret) {