From f5f09fbd44a5d44ff839beffe5b488c67eb34d52 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 12 Jun 2024 16:06:06 +0800 Subject: [PATCH] mmc: dw_mmc-rockchip: Fix internal phase calculate ciu clock from CRU is 2 times of interface clock, so the delay number maybe not so accurate as the sample phase is based on interface clock. Change-Id: Ib8d66f1c7af18fa3888dafc4528a95aabfa8572f Fixes: 1505eda5b9d2 ("mmc: dw_mmc-rockchip: Add internal phase support") Signed-off-by: Shawn Lin --- drivers/mmc/host/dw_mmc-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 6a39dac56f2d..2e0bd74f4030 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -48,7 +48,7 @@ struct dw_mci_rockchip_priv_data { */ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) { - unsigned long rate = clk_get_rate(host->ciu_clk); + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; u32 raw_value; u16 degrees; u32 delay_num = 0; @@ -79,7 +79,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) { - unsigned long rate = clk_get_rate(host->ciu_clk); + unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; u8 nineties, remainder; u8 delay_num; u32 raw_value;