diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-hdmi2csi-avb.dts b/arch/arm/boot/dts/rk3288-evb-rk628-hdmi2csi-avb.dts deleted file mode 100644 index 9bcd5dec4bff..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628-hdmi2csi-avb.dts +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk3288-evb-rk628.dtsi" - -/ { - model = "Rockchip RK3288 EVB RK628 Board"; - compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288"; - - chosen { - bootargs = "rootwait earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0 androidboot.selinux=permissive"; - }; - - hdmiin-sound { - compatible = "rockchip,rockchip-rt5651-rk628-sound"; - rockchip,cpu = <&i2s>; - rockchip,codec = <&rt5651>; - status = "okay"; - }; -}; - -&video_phy { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_in_vopb { - status = "disabled"; -}; - -&hdmi_in_vopl { - status = "okay"; -}; - -&route_hdmi { - connect = <&vopl_out_hdmi>; - status = "disabled"; -}; - -&rk628 { - reg = <0x51>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - enable-gpios = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&rk628_combrxphy { - status = "okay"; -}; - -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_csi { - status = "okay"; - plugin-det-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "RK628-CSI"; - rockchip,camera-module-lens-name = "NC"; - - port { - hdmiin_out0: endpoint { - remote-endpoint = <&hdmi2mipi_in>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&mipi_phy_rx0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi2mipi_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmiin_out0>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp_mipi_in>; - }; - }; - }; -}; - -&rkisp1 { - status = "okay"; - port { - #address-cells = <1>; - #size-cells = <0>; - - isp_mipi_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&dphy_rx_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts deleted file mode 100644 index ca0a9d54befc..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk3288-evb-rk628.dtsi" - -&rk628_dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in_post_process: endpoint { - remote-endpoint = <&post_process_out_dsi0>; - }; - }; - }; - - panel@0 { - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - disable-delay-ms = <120>; - unprepare-delay-ms = <120>; - init-delay-ms = <120>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | - MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 ff 98 81 03 - 39 00 02 01 00 - 39 00 02 02 00 - 39 00 02 03 53 - 39 00 02 04 53 - 39 00 02 05 13 - 39 00 02 06 04 - 39 00 02 07 02 - 39 00 02 08 02 - 39 00 02 09 00 - 39 00 02 0a 00 - 39 00 02 0b 00 - 39 00 02 0c 00 - 39 00 02 0d 00 - 39 00 02 0e 00 - 39 00 02 0f 00 - 39 00 02 10 00 - 39 00 02 11 00 - 39 00 02 12 00 - 39 00 02 13 00 - 39 00 02 14 00 - 39 00 02 15 08 - 39 00 02 16 10 - 39 00 02 17 00 - 39 00 02 18 08 - 39 00 02 19 00 - 39 00 02 1a 00 - 39 00 02 1b 00 - 39 00 02 1c 00 - 39 00 02 1d 00 - 39 00 02 1e c0 - 39 00 02 1f 80 - 39 00 02 20 02 - 39 00 02 21 09 - 39 00 02 22 00 - 39 00 02 23 00 - 39 00 02 24 00 - 39 00 02 25 00 - 39 00 02 26 00 - 39 00 02 27 00 - 39 00 02 28 55 - 39 00 02 29 03 - 39 00 02 2a 00 - 39 00 02 2b 00 - 39 00 02 2c 00 - 39 00 02 2d 00 - 39 00 02 2e 00 - 39 00 02 2f 00 - 39 00 02 30 00 - 39 00 02 31 00 - 39 00 02 32 00 - 39 00 02 33 00 - 39 00 02 34 04 - 39 00 02 35 05 - 39 00 02 36 05 - 39 00 02 37 00 - 39 00 02 38 3c - 39 00 02 39 35 - 39 00 02 3a 00 - 39 00 02 3b 40 - 39 00 02 3c 00 - 39 00 02 3d 00 - 39 00 02 3e 00 - 39 00 02 3f 00 - 39 00 02 40 00 - 39 00 02 41 88 - 39 00 02 42 00 - 39 00 02 43 00 - 39 00 02 44 1f - 39 00 02 50 01 - 39 00 02 51 23 - 39 00 02 52 45 - 39 00 02 53 67 - 39 00 02 54 89 - 39 00 02 55 ab - 39 00 02 56 01 - 39 00 02 57 23 - 39 00 02 58 45 - 39 00 02 59 67 - 39 00 02 5a 89 - 39 00 02 5b ab - 39 00 02 5c cd - 39 00 02 5d ef - 39 00 02 5e 03 - 39 00 02 5f 14 - 39 00 02 60 15 - 39 00 02 61 0c - 39 00 02 62 0d - 39 00 02 63 0e - 39 00 02 64 0f - 39 00 02 65 10 - 39 00 02 66 11 - 39 00 02 67 08 - 39 00 02 68 02 - 39 00 02 69 0a - 39 00 02 6a 02 - 39 00 02 6b 02 - 39 00 02 6c 02 - 39 00 02 6d 02 - 39 00 02 6e 02 - 39 00 02 6f 02 - 39 00 02 70 02 - 39 00 02 71 02 - 39 00 02 72 06 - 39 00 02 73 02 - 39 00 02 74 02 - 39 00 02 75 14 - 39 00 02 76 15 - 39 00 02 77 0f - 39 00 02 78 0e - 39 00 02 79 0d - 39 00 02 7a 0c - 39 00 02 7b 11 - 39 00 02 7c 10 - 39 00 02 7d 06 - 39 00 02 7e 02 - 39 00 02 7f 0a - 39 00 02 80 02 - 39 00 02 81 02 - 39 00 02 82 02 - 39 00 02 83 02 - 39 00 02 84 02 - 39 00 02 85 02 - 39 00 02 86 02 - 39 00 02 87 02 - 39 00 02 88 08 - 39 00 02 89 02 - 39 00 02 8a 02 - 39 00 04 ff 98 81 04 - 39 00 02 00 80 - 39 00 02 70 00 - 39 00 02 71 00 - 39 00 02 66 fe - 39 00 02 82 15 - 39 00 02 84 15 - 39 00 02 85 15 - 39 00 02 3a 24 - 39 00 02 32 ac - 39 00 02 8c 80 - 39 00 02 3c f5 - 39 00 02 88 33 - 39 00 04 ff 98 81 01 - 39 00 02 22 0a - 39 00 02 31 00 - 39 00 02 53 78 - 39 00 02 55 7b - 39 00 02 60 20 - 39 00 02 61 00 - 39 00 02 62 0d - 39 00 02 63 00 - 39 00 02 a0 00 - 39 00 02 a1 10 - 39 00 02 a2 1c - 39 00 02 a3 13 - 39 00 02 a4 15 - 39 00 02 a5 26 - 39 00 02 a6 1a - 39 00 02 a7 1d - 39 00 02 a8 67 - 39 00 02 a9 1c - 39 00 02 aa 29 - 39 00 02 ab 58 - 39 00 02 ac 26 - 39 00 02 ad 28 - 39 00 02 ae 5c - 39 00 02 af 30 - 39 00 02 b0 31 - 39 00 02 b1 32 - 39 00 02 b2 00 - 39 00 02 c0 00 - 39 00 02 c1 10 - 39 00 02 c2 1c - 39 00 02 c3 13 - 39 00 02 c4 15 - 39 00 02 c5 26 - 39 00 02 c6 1a - 39 00 02 c7 1d - 39 00 02 c8 67 - 39 00 02 c9 1c - 39 00 02 ca 29 - 39 00 02 cb 5b - 39 00 02 cc 26 - 39 00 02 cd 28 - 39 00 02 ce 5c - 39 00 02 cf 30 - 39 00 02 d0 31 - 39 00 02 d1 2e - 39 00 02 d2 32 - 39 00 02 d3 00 - 39 00 04 ff 98 81 00 - 05 fa 01 11 - 05 14 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <64000000>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <40>; - hsync-len = <10>; - hback-porch = <40>; - vfront-porch = <22>; - vsync-len = <4>; - vback-porch = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_dsi0: endpoint { - remote-endpoint = <&dsi0_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&video_phy { - status = "okay"; -}; - -&rgb_in_vopb { - status = "disabled"; -}; - -&rgb_in_vopl { - status = "okay"; -}; - -&route_rgb { - connect = <&vopl_out_rgb>; - status = "disabled"; -}; - -&vopb { - assigned-clocks = <&cru DCLK_VOP0>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vopl { - assigned-clocks = <&cru DCLK_VOP1>; - assigned-clock-parents = <&cru PLL_CPLL>; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts deleted file mode 100644 index 18ff5ed03d5f..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk3288-evb-rk628.dtsi" - -&sound { - status = "okay"; -}; - -&rk628_hdmi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_in_post_process: endpoint { - remote-endpoint = <&post_process_out_hdmi>; - }; - }; - }; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - - -&video_phy { - status = "okay"; -}; - -&rgb_in_vopb { - status = "disabled"; -}; - -&rgb_in_vopl { - status = "okay"; -}; - -&route_rgb { - connect = <&vopl_out_rgb>; - status = "disabled"; -}; - -&vopb { - assigned-clocks = <&cru DCLK_VOP0>; - assigned-clock-parents = <&cru PLL_CPLL>; -}; - -&vopl { - assigned-clocks = <&cru DCLK_VOP1>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts deleted file mode 100644 index 81577652ae11..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk3288-evb-rk628.dtsi" - -/ { - model = "Rockchip RK3288 EVB RK628 Board"; - compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288"; - - panel { - compatible = "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - prepare-delay-ms = <20>; - enable-delay-ms = <20>; - disable-delay-ms = <20>; - unprepare-delay-ms = <20>; - bus-format = ; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <48000000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <90>; - hfront-porch = <90>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <90>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&rk628_lvds { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_in_post_process: endpoint { - remote-endpoint = <&post_process_out_lvds>; - }; - }; - - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_lvds: endpoint { - remote-endpoint = <&lvds_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&video_phy { - status = "okay"; -}; - -&rgb_in_vopb { - status = "disabled"; -}; - -&rgb_in_vopl { - status = "okay"; -}; - -&route_rgb { - connect = <&vopl_out_rgb>; - status = "disabled"; -}; - -&vopb { - assigned-clocks = <&cru DCLK_VOP0>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vopl { - assigned-clocks = <&cru DCLK_VOP1>; - assigned-clock-parents = <&cru PLL_CPLL>; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-dual-avb.dts b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-dual-avb.dts deleted file mode 100644 index 5fa6de887356..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-dual-avb.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk3288-evb-rk628.dtsi" - -/ { - vcc33_lcd: vcc33-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc33_lcd"; - regulator-boot-on; - gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc33_lcd>; - enable-gpios = <&gpio5 RK_PC1 GPIO_ACTIVE_HIGH>; - prepare-delay-ms = <20>; - enable-delay-ms = <20>; - disable-delay-ms = <20>; - unprepare-delay-ms = <20>; - bus-format = ; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <149000000>; - hactive = <1920>; - vactive = <1080>; - hback-porch = <96>; - hfront-porch = <120>; - vback-porch = <8>; - vfront-porch = <33>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&rk628_lvds { - rockchip,link-type = "dual-link-even-odd-pixels"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_in_post_process: endpoint { - remote-endpoint = <&post_process_out_lvds>; - }; - }; - - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_lvds: endpoint { - remote-endpoint = <&lvds_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&video_phy { - status = "okay"; -}; - -&rgb_in_vopb { - status = "disabled"; -}; - -&rgb_in_vopl { - status = "okay"; -}; - -&route_rgb { - connect = <&vopl_out_rgb>; - status = "disabled"; -}; - -&vopb { - assigned-clocks = <&cru DCLK_VOP0>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vopl { - assigned-clocks = <&cru DCLK_VOP1>; - assigned-clock-parents = <&cru PLL_CPLL>; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk628.dtsi b/arch/arm/boot/dts/rk3288-evb-rk628.dtsi deleted file mode 100644 index 0d23a231768d..000000000000 --- a/arch/arm/boot/dts/rk3288-evb-rk628.dtsi +++ /dev/null @@ -1,614 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -#include -#include -#include "rk3288.dtsi" -#include "rk3288-android.dtsi" - -/ { - model = "Rockchip RK3288 EVB RK628 Board"; - compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288"; - - chosen: chosen { - bootargs = "rootwait earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <1000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <170000>; - }; - - menu { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <640000>; - }; - - esc { - label = "esc"; - linux,code = ; - press-threshold-microvolt = <1000000>; - }; - - home { - label = "home"; - linux,code = ; - press-threshold-microvolt = <1300000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - }; - - i2s_mclkin: i2s-mclkin { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&cru SCLK_I2S0_OUT>; - clock-mult = <1>; - clock-div = <1>; - clock-output-names = "i2s_mclkin"; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "realtek,rt5651-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC1", "Microphone Jack", - "MIC2", "Microphone Jack", - "Microphone Jack", "micbias1", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - status = "disabled"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&i2s>; - }; - - codec { - sound-dai = <&rt5651>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&i2s>; - }; - - codec { - sound-dai = <&rk628_hdmi>; - }; - }; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-logic { - compatible = "pwm-regulator"; - rockchip,pwm_id = <1>; - rockchip,pwm_voltage = <1100000>; - pwms = <&pwm1 0 25000 1>; - regulator-name = "vcc_log"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1360000>; - regulator-always-on; - regulator-boot-on; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; -}; - -&backlight { - /delete-property/ enable-gpios; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_log>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd_arm"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <6000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_codec: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vccio_wl: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vccio_wl"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - rk628: rk628@50 { - reg = <0x50>; - interrupt-parent = <&gpio7>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; - enable-gpios = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio7 RK_PB6 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&i2c2 { - status = "okay"; - - rt5651: rt5651@1a { - compatible = "rockchip,rt5651"; - reg = <0x1a>; - clocks = <&cru SCLK_I2S0_OUT>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - }; -}; - -&i2s { - #sound-dai-cells = <0>; - status = "okay"; -}; - -#include "rk628.dtsi" - -&io_domains { - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_io>; - flash0-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_lcd>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - status = "okay"; -}; - -&rockchip_suspend { - rockchip,pwm-regulator-config = < - (0 - | PWM1_REGULATOR_EN - ) - >; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm1_pin_pull_down>; - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - max-frequency = <100000000>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - no-sdio; - no-mmc; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&backlight { - status = "okay"; -}; - -&rga { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - rockchip-relinquish-port; - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk628.dtsi b/arch/arm/boot/dts/rk628.dtsi deleted file mode 100644 index 3a2f45c7ecfa..000000000000 --- a/arch/arm/boot/dts/rk628.dtsi +++ /dev/null @@ -1,391 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - -#include -#include - -/ { - rk628_xin_osc0_func: rk628-xin-osc0-func { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "rk628_xin_osc0_func"; - }; - - rk628_xin_osc0_half: rk628-xin-osc0-half { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&rk628_xin_osc0_func>; - clock-mult = <1>; - clock-div = <2>; - clock-output-names = "rk628_xin_osc0_half"; - }; -}; - -&rk628 { - compatible = "rockchip,rk628"; - - rk628_cru: cru { - compatible = "rockchip,rk628-cru"; - #clock-cells = <1>; - #reset-cells = <1>; - status = "okay"; - }; - - rk628_efuse: efuse { - compatible = "rockchip,rk628-efuse"; - clocks = <&rk628_cru CGU_PCLK_EFUSE>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_EFUSE>; - #phy-cells = <0>; - status = "disabled"; - }; - - rk628_pinctrl: pinctrl { - compatible = "rockchip,rk628-pinctrl"; - status = "okay"; - - rk628_gpio0: rk628-gpio0 { - clocks = <&rk628_cru CGU_PCLK_GPIO0>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rk628_gpio1: rk628-gpio1 { - clocks = <&rk628_cru CGU_PCLK_GPIO1>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rk628_gpio2: rk628-gpio2 { - clocks = <&rk628_cru CGU_PCLK_GPIO2>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rk628_gpio3: rk628-gpio3 { - clocks = <&rk628_cru CGU_PCLK_GPIO3>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rk628_i2sm0_pins: i2sm0 { - pins = "gpio0a2", /* i2sm0_sck */ - "gpio0a3", /* i2sm0_lr */ - "gpio0a4", /* i2sm0_d0 */ - "gpio0a5", /* i2sm0_d1 */ - "gpio0a6", /* i2sm0_d2 */ - "gpio0a7"; /* i2sm0_d3 */ - function = "i2sm0"; - }; - - rk628_hpd_in_pins: hpd-in { - pins = "gpio0b0"; - function = "hpd_in"; - }; - - rk628_ddc_tx_pins: ddc-tx { - pins = "gpio0b1", /* ddc_tx_sda */ - "gpio0b2"; /* ddc_tx_scl */ - function = "ddc_tx"; - }; - - rk628_cec_tx_pins: cec-tx { - pins = "gpio0b3"; - function = "cec_tx"; - }; - - rk628_test_clkout_pins: test-clkout { - pins = "gpio1a0"; - function = "test_clkout"; - }; - - rk628_i2sm1_pins: i2sm1 { - pins = "gpio1a2", /* i2sm1_sck */ - "gpio1a3", /* i2sm1_lr */ - "gpio1a4", /* i2sm1_d0 */ - "gpio1a5", /* i2sm1_d1 */ - "gpio1a6", /* i2sm1_d2 */ - "gpio1a7"; /* i2sm1_d3 */ - function = "i2sm1"; - }; - - rk628_hpdm0_out_pins: hpdm0-out { - pins = "gpio1b0"; - function = "hpdm0_out"; - }; - - rk628_ddcm0_rx_pins: ddcm0-rx { - pins = "gpio1b1", /* ddcm0_rx_sda */ - "gpio1b2"; /* ddcm0_rx_scl */ - function = "ddcm0_rx"; - }; - - rk628_cecm0_rx_pins: cecm0_rx { - pins = "gpio1b3"; - function = "cecm0_rx"; - }; - - rk628_vop_pins: vop { - pins = "gpio2a0", /* vop_d0 */ - "gpio2a1", /* vop_d1 */ - "gpio2a2", /* vop_d2 */ - "gpio2a3", /* vop_d3 */ - "gpio2a4", /* vop_d4 */ - "gpio2a5", /* vop_d5 */ - "gpio2a6", /* vop_d6 */ - "gpio2a7", /* vop_d7 */ - "gpio2b0", /* vop_d8 */ - "gpio2b1", /* vop_d9 */ - "gpio2b2", /* vop_d10 */ - "gpio2b3", /* vop_d11 */ - "gpio2b4", /* vop_d12 */ - "gpio2b5", /* vop_d13 */ - "gpio2b6", /* vop_d14 */ - "gpio2b7", /* vop_d15 */ - "gpio2c0", /* vop_d16 */ - "gpio2c1", /* vop_d17 */ - "gpio2c2", /* vop_d18 */ - "gpio2c3", /* vop_d19 */ - "gpio2c4", /* vop_d20 */ - "gpio2c5", /* vop_d21 */ - "gpio2c6", /* vop_d22 */ - "gpio2c7", /* vop_d23 */ - "gpio3a0", /* vop_den */ - "gpio3a1", /* vop_hsync */ - "gpio3a3", /* vop_vsync */ - "gpio3b0"; /* vop_dclk */ - function = "vop"; - drive-strength = <1>; - }; - - rk628_hpdm1_out: hpdm1-out { - pins = "gpio3a4"; - function = "hpdm1_out"; - }; - - rk628_ddcm1_rx_pins: ddcm1-rx { - pins = "gpio3a5", /* ddcm1_rx_sda */ - "gpio3a6"; /* ddcm1_rx_scl */ - function = "ddcm1_rx"; - }; - - rk628_cecm1_rx_pins: cecm1-rx { - pins = "gpio3a7"; - function = "cecm1_rx"; - }; - - rk628_gvi_hpd_pins: gvi-hpd { - pins = "gpio3b1"; - function = "gvi_hpd"; - }; - - rk628_gvi_lock_pins: gvi-lock { - pins = "gpio3b2"; - function = "gvi_lock"; - }; - - rk628_hdmirx_cec0: hdmirx-cec0 { - pins = "hdmirx_cec"; - function = "hdmirx_cec0"; - }; - - rk628_hdmirx_cec1: hdmirx-cec1 { - pins = "hdmirx_cec"; - function = "hdmirx_cec1"; - }; - - rk628_rxddc_input0: rxddc-input0 { - pins = "rxddc_scl", - "rxddc_sda"; - function = "rxddc_input0"; - }; - - rk628_rxddc_input1: rxddc-input1 { - pins = "rxddc_scl", - "rxddc_sda"; - function = "rxddc_input1"; - }; - - rk628_i2sm0_input: i2sm0-input { - pins = "i2sm_sck", - "i2sm_d", - "i2sm_lr"; - function = "i2sm0_input"; - }; - - rk628_i2sm1_input: i2sm1-input { - pins = "i2sm_sck", - "i2sm_d", - "i2sm_lr"; - function = "i2sm1_input"; - }; - }; - - rk628_combtxphy: combtxphy { - compatible = "rockchip,rk628-combtxphy"; - clocks = <&rk628_cru CGU_PCLK_TXPHY_CON>, <&rk628_cru CGU_SCLK_VOP>; - clock-names = "pclk", "ref_clk"; - resets = <&rk628_cru RGU_TXPHY_CON>; - #phy-cells = <0>; - status = "disabled"; - }; - - rk628_combrxphy: combrxphy { - compatible = "rockchip,rk628-combrxphy"; - clocks = <&rk628_cru CGU_PCLK_RXPHY>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_RXPHY>; - #phy-cells = <0>; - status = "disabled"; - }; - - rk628_dsi0: dsi0 { - compatible = "rockchip,rk628-dsi0"; - clocks = <&rk628_cru CGU_PCLK_DSI0>, - <&rk628_cru CGU_CLK_CFG_DPHY0>; - clock-names = "pclk", "cfg"; - resets = <&rk628_cru RGU_DSI0>; - phys = <&rk628_combtxphy>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rk628_dsi1: dsi1 { - compatible = "rockchip,rk628-dsi1"; - clocks = <&rk628_cru CGU_PCLK_DSI1>, - <&rk628_cru CGU_CLK_CFG_DPHY1>; - clock-names = "pclk", "cfg"; - resets = <&rk628_cru RGU_DSI1>; - phys = <&rk628_combtxphy>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rk628_lvds: lvds { - compatible = "rockchip,rk628-lvds"; - phys = <&rk628_combtxphy>; - status = "disabled"; - }; - - rk628_gvi: gvi { - compatible = "rockchip,rk628-gvi"; - clocks = <&rk628_cru CGU_PCLK_GVIHOST>; - clock-names = "pclk"; - resets = <&rk628_cru RGU_GVIHOST>; - phys = <&rk628_combtxphy>; - status = "disabled"; - }; - - rk628_rgb_tx: rgb-tx { - compatible = "rockchip,rk628-rgb-tx"; - status = "disabled"; - }; - - rk628_yuv_rx: yuv-rx { - compatible = "rockchip,rk628-yuv-rx"; - status = "disabled"; - }; - - rk628_yuv_tx: yuv-tx { - compatible = "rockchip,rk628-yuv-tx"; - status = "disabled"; - }; - - rk628_bt1120_rx: bt1120-rx { - compatible = "rockchip,rk628-bt1120-rx"; - clocks = <&rk628_cru CGU_BT1120DEC>; - clock-names = "bt1120dec"; - resets = <&rk628_cru RGU_BT1120DEC>; - status = "disabled"; - }; - - rk628_bt1120_tx: bt1120-tx { - compatible = "rockchip,rk628-bt1120-tx"; - status = "disabled"; - }; - - rk628_post_process: post-process { - compatible = "rockchip,rk628-post-process"; - clocks = <&rk628_cru CGU_SCLK_VOP>, - <&rk628_cru CGU_CLK_RX_READ>; - clock-names = "sclk_vop", "rx_read"; - resets = <&rk628_cru RGU_DECODER>, - <&rk628_cru RGU_CLK_RX>, - <&rk628_cru RGU_VOP>; - reset-names = "decoder", "clk_rx", "vop"; - status = "disabled"; - }; - - rk628_hdmi: hdmi { - compatible = "rockchip,rk628-hdmi"; - clocks = <&rk628_cru CGU_PCLK_HDMITX>, - <&rk628_cru CGU_SCLK_VOP>; - clock-names = "pclk", "dclk"; - pinctrl-names = "default"; - pinctrl-0 = <&rk628_hpd_in_pins &rk628_ddc_tx_pins &rk628_i2sm0_pins>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - rk628_hdmirx: hdmirx { - compatible = "rockchip,rk628-hdmirx"; - clocks = <&rk628_cru CGU_PCLK_HDMIRX>, - <&rk628_cru CGU_CLK_HDMIRX_CEC>, - <&rk628_cru CGU_CLK_HDMIRX_AUD>, - <&rk628_cru CGU_CLK_IMODET>; - clock-names = "pclk", "cec", "audio", "imodet"; - resets = <&rk628_cru RGU_HDMIRX>, - <&rk628_cru RGU_HDMIRX_PON>; - reset-names = "hdmirx", "hdmirx_pon"; - phys = <&rk628_combrxphy>; - status = "disabled"; - }; - - rk628_csi: csi { - compatible = "rockchip,rk628-csi"; - clocks = <&rk628_cru CGU_PCLK_HDMIRX>, - <&rk628_cru CGU_CLK_IMODET>, - <&rk628_cru CGU_CLK_HDMIRX_AUD>, - <&rk628_cru CGU_CLK_HDMIRX_CEC>, - <&rk628_cru CGU_SCLK_VOP>, - <&rk628_cru CGU_CLK_RX_READ>, - <&rk628_cru CGU_PCLK_CSI>, - <&rk628_cru CGU_CLK_TESTOUT>; - clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec", - "vop", "rx_read", "csi0", "i2s_mclk"; - assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>; - assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>; - resets = <&rk628_cru RGU_HDMIRX>, - <&rk628_cru RGU_HDMIRX_PON>, - <&rk628_cru RGU_DECODER>, - <&rk628_cru RGU_CLK_RX>, - <&rk628_cru RGU_VOP>, - <&rk628_cru RGU_CSI>; - reset-names = "hdmirx", "hdmirx_pon", "decoder", "clk_rx", - "vop", "csi0"; - phys = <&rk628_combrxphy>, <&rk628_combtxphy>; - phy-names = "combrxphy", "combtxphy"; - pinctrl-names = "default"; - pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts b/arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts index 138a4467bc02..ab6b493a0d0c 100644 --- a/arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts +++ b/arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts @@ -76,7 +76,7 @@ &pinctrl { buttons { pwr_key: pwr-key { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 21a898fea122..c5c4ed22dfab 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -185,10 +185,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb5-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi index 75f624ec9c44..c733ca4b32c8 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi @@ -345,13 +345,13 @@ vcc_3v0: DCDC_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-initial-mode = <0x2>; regulator-name = "vcc_3v0"; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; + regulator-suspend-microvolt = <3000000>; }; }; @@ -396,13 +396,13 @@ vcc3v0_pmu: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vcc3v0_pmu"; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; + regulator-suspend-microvolt = <3000000>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts deleted file mode 100644 index 106e85c07eb4..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - */ - -#include "rk3568-evb6-ddr3-v10.dtsi" -#include "rk3568-android.dtsi" - -&dsi0 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - rk628: rk628@50 { - reg = <0x50>; - interrupt-parent = <&gpio0>; - interrupts = ; - enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&video_phy0 { - status = "disabled"; -}; - -#include - -&rk628_hdmi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_in_post_process: endpoint { - remote-endpoint = <&post_process_out_hdmi>; - }; - }; - }; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - mode-sync-pol = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_bt1120: endpoint { - remote-endpoint = <&bt1120_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_post_process>; - }; - }; - }; -}; - -&rk628_bt1120_rx { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bt1120_in_rgb: endpoint { - remote-endpoint = <&rgb_out_bt1120>; - }; - }; - - port@1 { - reg = <1>; - - bt1120_out_post_process: endpoint { - remote-endpoint = <&post_process_in_bt1120>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&bt1120_pins>; - - ports { - port@1 { - reg = <1>; - - rgb_out_bt1120: endpoint { - remote-endpoint = <&bt1120_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp2 { - status = "okay"; -}; - -&vcc3v3_lcd1_n { - status = "disabled"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts deleted file mode 100644 index 1cefbfa43d0f..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - */ - -#include "rk3568-evb6-ddr3-v10.dtsi" -#include "rk3568-android.dtsi" - -&dsi0 { - status = "disabled"; -}; - -&video_phy0 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - rk628: rk628@50 { - reg = <0x50>; - interrupt-parent = <&gpio0>; - interrupts = ; - enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -#include - -&backlight { - pwms = <&pwm14 0 25000 0>; -}; - -&pwm14 { - status = "okay"; -}; - -&rk628_dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in_post_process: endpoint { - remote-endpoint = <&post_process_out_dsi0>; - }; - }; - }; - - panel@0 { - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - disable-delay-ms = <120>; - unprepare-delay-ms = <120>; - init-delay-ms = <120>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | - MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings3: display-timings { - native-mode = <&dsi0_timing3>; - dsi0_timing3: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <2>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - mode-sync-pol = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_dsi0: endpoint { - remote-endpoint = <&dsi0_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp2 { - status = "okay"; -}; - -&vcc3v3_lcd1_n { - status = "disabled"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts deleted file mode 100644 index a4759f1ba85e..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - */ - -#include "rk3568-evb6-ddr3-v10.dtsi" -#include "rk3568-android.dtsi" - -&dsi0 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - rk628: rk628@50 { - reg = <0x50>; - interrupt-parent = <&gpio0>; - interrupts = ; - enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -#include - -&rk628_hdmi { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_in_post_process: endpoint { - remote-endpoint = <&post_process_out_hdmi>; - }; - }; - }; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - mode-sync-pol = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp2 { - status = "okay"; -}; - -&vcc3v3_lcd1_n { - status = "disabled"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts deleted file mode 100644 index ec43b24ddab1..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rk3568-evb6-ddr3-v10.dtsi" -#include "rk3568-android.dtsi" - -/ { - vcc33_lcd: vcc33-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc33_lcd"; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "simple-panel"; - power-supply = <&vcc33_lcd>; - backlight = <&backlight>; - enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - prepare-delay-ms = <20>; - enable-delay-ms = <20>; - disable-delay-ms = <20>; - unprepare-delay-ms = <20>; - bus-format = ; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <66600000>; - hactive = <800>; - vactive = <1280>; - hback-porch = <30>; - hfront-porch = <30>; - vback-porch = <3>; - vfront-porch = <3>; - hsync-len = <4>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&dsi0 { - status = "disabled"; -}; - -&video_phy0 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - rk628: rk628@50 { - reg = <0x50>; - interrupt-parent = <&gpio0>; - interrupts = ; - enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -#include - -&backlight { - pwms = <&pwm14 0 25000 0>; -}; - -&pwm14 { - status = "okay"; -}; - -&rk628_lvds { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_in_post_process: endpoint { - remote-endpoint = <&post_process_out_lvds>; - }; - }; - - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; -&rk628_combtxphy { - status = "okay"; -}; - -&rk628_post_process { - pinctrl-names = "default"; - pinctrl-0 = <&rk628_vop_pins>; - status = "okay"; - - mode-sync-pol = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - post_process_in_rgb: endpoint { - remote-endpoint = <&rgb_out_post_process>; - }; - }; - - port@1 { - reg = <1>; - - post_process_out_lvds: endpoint { - remote-endpoint = <&lvds_in_post_process>; - }; - }; - }; -}; - -&rgb { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - rgb_out_post_process: endpoint { - remote-endpoint = <&post_process_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp2 { - status = "okay"; -}; - -&vcc3v3_lcd1_n { - status = "disabled"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; - -&gmac1 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi index f5389891113d..9b56a477d78f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi @@ -5,14 +5,6 @@ */ / { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; vcc_mipidphy0: vcc-mipidcphy0-regulator { compatible = "regulator-fixed"; gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; @@ -74,7 +66,6 @@ rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT2022-PX1"; rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; port { imx415_out0: endpoint { remote-endpoint = <&mipidphy0_in_ucam0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi index 612b466cebed..b4eef542ca66 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi @@ -130,7 +130,7 @@ }; &display_subsystem { - clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi0>; + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts index ccb527f84094..f1ec17c12157 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts @@ -349,6 +349,10 @@ vin-supply = <&dphy3_vcc12v_buck>; }; +&max96712_dphy3 { + lock-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; +}; + &max96756_dphy0_vcc1v2 { vin-supply = <&vcc5v0_buck>; }; diff --git a/arch/arm64/configs/rk3588_vehicle.config b/arch/arm64/configs/rk3588_vehicle.config new file mode 100644 index 000000000000..ed11bde9aadb --- /dev/null +++ b/arch/arm64/configs/rk3588_vehicle.config @@ -0,0 +1,160 @@ +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_CW2017 is not set +# CONFIG_BATTERY_CW221X is not set +# CONFIG_BATTERY_RK817 is not set +# CONFIG_BATTERY_RK818 is not set +# CONFIG_CHARGER_BQ25700 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_RK817 is not set +# CONFIG_CHARGER_RK818 is not set +# CONFIG_CHARGER_SC8551 is not set +# CONFIG_CHARGER_SC89890 is not set +# CONFIG_CHARGER_SGM41542 is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMPASS_DEVICE is not set +# CONFIG_CPU_IDLE_GOV_MENU is not set +CONFIG_CPU_IDLE_GOV_TEO=y +# CONFIG_CPU_PX30 is not set +# CONFIG_CPU_RK3328 is not set +# CONFIG_CPU_RK3368 is not set +# CONFIG_CPU_RK3399 is not set +# CONFIG_CPU_RK3528 is not set +# CONFIG_CPU_RK3562 is not set +# CONFIG_CPU_RK3568 is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP_V3 is not set +# CONFIG_DRM_MAXIM_MAX96745 is not set +# CONFIG_DRM_MAXIM_MAX96755F is not set +# CONFIG_DRM_RK1000_TVE is not set +# CONFIG_DRM_RK630_TVE is not set +# CONFIG_DRM_ROHM_BU18XL82 is not set +# CONFIG_DRM_SII902X is not set +CONFIG_GPIO_NCA9539=y +# CONFIG_HALL_DEVICE is not set +CONFIG_HZ=1000 +CONFIG_HZ_1000=y +# CONFIG_HZ_300 is not set +# CONFIG_IIO_ST_LSM6DSR is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_LIGHT_DEVICE is not set +CONFIG_LOG_BUF_SHIFT=18 +# CONFIG_MALI400 is not set +# CONFIG_MALI_MIDGARD is not set +# CONFIG_MFD_RK618 is not set +# CONFIG_MFD_RK628 is not set +# CONFIG_MFD_RK630_I2C is not set +# CONFIG_MFD_RKX110_X120 is not set +CONFIG_MFD_SERDES_DISPLAY=y +# CONFIG_PROXIMITY_DEVICE is not set +# CONFIG_R8168 is not set +CONFIG_REALTEK_PHY=y +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_LP8752 is not set +# CONFIG_REGULATOR_MP8865 is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_WL2868C is not set +# CONFIG_REGULATOR_XZ3216 is not set +# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set +# CONFIG_ROCKCHIP_CLK_BOOST is not set +# CONFIG_ROCKCHIP_CLK_INV is not set +# CONFIG_ROCKCHIP_CLK_PVTM is not set +# CONFIG_ROCKCHIP_DDRCLK_SIP is not set +# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set +CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y +# CONFIG_ROCKCHIP_PLL_RK3066 is not set +# CONFIG_ROCKCHIP_PLL_RK3399 is not set +# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set +# CONFIG_ROCKCHIP_VOP is not set +CONFIG_SATA_AHCI_PLATFORM=m +# CONFIG_SLUB_SYSFS is not set +# CONFIG_SND_SOC_AW883XX is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_ES8311 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8396 is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK3528 is not set +# CONFIG_SND_SOC_RK817 is not set +# CONFIG_SND_SOC_RK_CODEC_DIGITAL is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_TOUCHSCREEN_ELAN5515 is not set +# CONFIG_TOUCHSCREEN_GSL3673 is not set +# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set +CONFIG_TOUCHSCREEN_GT1X=m +CONFIG_TOUCHSCREEN_HIMAX_CHIPSET=y +CONFIG_TOUCHSCREEN_ILI210X=m +# CONFIG_UCS12CM0 is not set +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +# CONFIG_VIDEO_AW36518 is not set +# CONFIG_VIDEO_AW8601 is not set +# CONFIG_VIDEO_CN3927V is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_FP5510 is not set +# CONFIG_VIDEO_GC2145 is not set +# CONFIG_VIDEO_GC2385 is not set +# CONFIG_VIDEO_GC4C33 is not set +# CONFIG_VIDEO_GC8034 is not set +# CONFIG_VIDEO_IMX415 is not set +CONFIG_VIDEO_MAXIM_SERDES=y +# CONFIG_VIDEO_OV02B10 is not set +# CONFIG_VIDEO_OV13850 is not set +# CONFIG_VIDEO_OV13855 is not set +# CONFIG_VIDEO_OV50C40 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV8858 is not set +# CONFIG_VIDEO_RK628_BT1120 is not set +# CONFIG_VIDEO_RK628_CSI is not set +# CONFIG_VIDEO_RK_IRCUT is not set +# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X is not set +# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21 is not set +# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32 is not set +# CONFIG_VIDEO_S5K3L6XX is not set +# CONFIG_VIDEO_S5KJN1 is not set +# CONFIG_VIDEO_SGM3784 is not set +# CONFIG_VL6180 is not set +# CONFIG_ROCKCHIP_DRM_SELF_TEST is not set +CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y +CONFIG_SERDES_DISPLAY_CHIP_NOVO=y +CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y +CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y +CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y +CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y +CONFIG_SERDES_DISPLAY_CHIP_ROHM=y +CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y +CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y +CONFIG_TOUCHSCREEN_HIMAX_COMMON=m +CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +# CONFIG_TOUCHSCREEN_HIMAX_EMBEDDED_FIRMWARE is not set +# CONFIG_TOUCHSCREEN_HIMAX_IC_HX83191 is not set +CONFIG_TOUCHSCREEN_HIMAX_IC_HX83192=m +# CONFIG_TOUCHSCREEN_HIMAX_IC_HX83193 is not set +CONFIG_TOUCHSCREEN_HIMAX_INCELL=y +# CONFIG_TOUCHSCREEN_HIMAX_INSPECT is not set +CONFIG_VIDEO_MAXIM_CAM_OV231X=y +CONFIG_VIDEO_MAXIM_CAM_OX01F10=y +CONFIG_VIDEO_MAXIM_CAM_OX03J10=y +CONFIG_VIDEO_MAXIM_CAM_SC320AT=y +CONFIG_VIDEO_MAXIM_DES_MAXIM4C=y +CONFIG_VIDEO_MAXIM_SER_MAX9295=y +CONFIG_VIDEO_MAXIM_SER_MAX96715=y +CONFIG_VIDEO_MAXIM_SER_MAX96717=y diff --git a/drivers/clk/rockchip/regmap/Kconfig b/drivers/clk/rockchip/regmap/Kconfig index 65f691bc4141..df30e308e163 100644 --- a/drivers/clk/rockchip/regmap/Kconfig +++ b/drivers/clk/rockchip/regmap/Kconfig @@ -8,9 +8,3 @@ config CLK_RK618 depends on MFD_RK618 default MFD_RK618 select COMMON_CLK_ROCKCHIP_REGMAP - -config CLK_RK628 - tristate "Clock driver for Rockchip RK628" - depends on MFD_RK628 - default MFD_RK628 - select COMMON_CLK_ROCKCHIP_REGMAP diff --git a/drivers/clk/rockchip/regmap/Makefile b/drivers/clk/rockchip/regmap/Makefile index 18d075d093d9..8127b7727750 100644 --- a/drivers/clk/rockchip/regmap/Makefile +++ b/drivers/clk/rockchip/regmap/Makefile @@ -10,4 +10,3 @@ clk-rockchip-regmap-objs := clk-regmap-mux.o \ clk-regmap-pll.o obj-$(CONFIG_CLK_RK618) += clk-rk618.o -obj-$(CONFIG_CLK_RK628) += clk-rk628.o diff --git a/drivers/clk/rockchip/regmap/clk-regmap.h b/drivers/clk/rockchip/regmap/clk-regmap.h index 4626e1982beb..91a32d3d710b 100644 --- a/drivers/clk/rockchip/regmap/clk-regmap.h +++ b/drivers/clk/rockchip/regmap/clk-regmap.h @@ -154,23 +154,6 @@ struct clk_composite_data { .flags = _flags, \ } -#define COMPOSITE_NOMUX(_id, _name, _parent_name, \ - _div_reg, _div_shift, _div_width, \ - _gate_reg, _gate_shift, _flags) \ -{ \ - .id = _id, \ - .name = _name, \ - .parent_names = (const char *[]){ _parent_name }, \ - .num_parents = 1, \ - .div_reg = _div_reg, \ - .div_shift = _div_shift, \ - .div_width = _div_width, \ - .div_flags = CLK_DIVIDER_HIWORD_MASK, \ - .gate_reg = _gate_reg, \ - .gate_shift = _gate_shift, \ - .flags = _flags, \ -} - #define COMPOSITE_NODIV(_id, _name, _parent_names, \ _mux_reg, _mux_shift, _mux_width, \ _gate_reg, _gate_shift, _flags) \ @@ -197,20 +180,6 @@ struct clk_composite_data { .flags = _flags, \ } -#define COMPOSITE_FRAC_NOMUX(_id, _name, _parent_name, \ - _div_reg, \ - _gate_reg, _gate_shift, _flags) \ -{ \ - .id = _id, \ - .name = _name, \ - .parent_names = (const char *[]){ _parent_name }, \ - .num_parents = 1, \ - .div_reg = _div_reg, \ - .gate_reg = _gate_reg, \ - .gate_shift = _gate_shift, \ - .flags = _flags, \ -} - #define COMPOSITE_FRAC_NOGATE(_id, _name, _parent_names, \ _mux_reg, _mux_shift, _mux_width, \ _div_reg, \ diff --git a/drivers/clk/rockchip/regmap/clk-rk628.c b/drivers/clk/rockchip/regmap/clk-rk628.c deleted file mode 100644 index 7f501db660e0..000000000000 --- a/drivers/clk/rockchip/regmap/clk-rk628.c +++ /dev/null @@ -1,609 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Wyon Bi - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-regmap.h" - -#define RK628_PLL(_id, _name, _parent_name, _reg, _flags) \ - PLL(_id, _name, _parent_name, _reg, 13, 12, 10, _flags) - -#define REG(x) ((x) + 0xc0000) - -#define CRU_CPLL_CON0 REG(0x0000) -#define CRU_CPLL_CON1 REG(0x0004) -#define CRU_CPLL_CON2 REG(0x0008) -#define CRU_CPLL_CON3 REG(0x000c) -#define CRU_CPLL_CON4 REG(0x0010) -#define CRU_GPLL_CON0 REG(0x0020) -#define CRU_GPLL_CON1 REG(0x0024) -#define CRU_GPLL_CON2 REG(0x0028) -#define CRU_GPLL_CON3 REG(0x002c) -#define CRU_GPLL_CON4 REG(0x0030) -#define CRU_MODE_CON REG(0x0060) -#define CRU_CLKSEL_CON00 REG(0x0080) -#define CRU_CLKSEL_CON01 REG(0x0084) -#define CRU_CLKSEL_CON02 REG(0x0088) -#define CRU_CLKSEL_CON03 REG(0x008c) -#define CRU_CLKSEL_CON04 REG(0x0090) -#define CRU_CLKSEL_CON05 REG(0x0094) -#define CRU_CLKSEL_CON06 REG(0x0098) -#define CRU_CLKSEL_CON07 REG(0x009c) -#define CRU_CLKSEL_CON08 REG(0x00a0) -#define CRU_CLKSEL_CON09 REG(0x00a4) -#define CRU_CLKSEL_CON10 REG(0x00a8) -#define CRU_CLKSEL_CON11 REG(0x00ac) -#define CRU_CLKSEL_CON12 REG(0x00b0) -#define CRU_CLKSEL_CON13 REG(0x00b4) -#define CRU_CLKSEL_CON14 REG(0x00b8) -#define CRU_CLKSEL_CON15 REG(0x00bc) -#define CRU_CLKSEL_CON16 REG(0x00c0) -#define CRU_CLKSEL_CON17 REG(0x00c4) -#define CRU_CLKSEL_CON18 REG(0x00c8) -#define CRU_CLKSEL_CON20 REG(0x00d0) -#define CRU_CLKSEL_CON21 REG(0x00d4) -#define CRU_GATE_CON00 REG(0x0180) -#define CRU_GATE_CON01 REG(0x0184) -#define CRU_GATE_CON02 REG(0x0188) -#define CRU_GATE_CON03 REG(0x018c) -#define CRU_GATE_CON04 REG(0x0190) -#define CRU_GATE_CON05 REG(0x0194) -#define CRU_SOFTRST_CON00 REG(0x0200) -#define CRU_SOFTRST_CON01 REG(0x0204) -#define CRU_SOFTRST_CON02 REG(0x0208) -#define CRU_SOFTRST_CON04 REG(0x0210) -#define CRU_MAX_REGISTER CRU_SOFTRST_CON04 - -#define reset_to_cru(_rst) container_of(_rst, struct rk628_cru, rcdev) - -struct rk628_cru { - struct device *dev; - struct rk628 *parent; - struct regmap *regmap; - struct reset_controller_dev rcdev; - struct clk_onecell_data clk_data; -}; - -#define CNAME(x) "rk628_" x - -#define PNAME(x) static const char *const x[] - -PNAME(mux_cpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_cpll") }; -PNAME(mux_gpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_gpll") }; -PNAME(mux_cpll_gpll_mux_p) = { CNAME("clk_cpll_mux"), CNAME("clk_gpll_mux") }; -PNAME(mux_mclk_i2s_8ch_p) = { CNAME("clk_i2s_8ch_src"), - CNAME("clk_i2s_8ch_frac"), CNAME("i2s_mclkin"), - CNAME("xin_osc0_half") }; -PNAME(mux_i2s_mclkout_p) = { CNAME("mclk_i2s_8ch"), CNAME("xin_osc0_half") }; -PNAME(mux_clk_testout_p) = { CNAME("xin_osc0_func"), CNAME("xin_osc0_half"), - CNAME("clk_gpll"), CNAME("clk_gpll_mux"), - CNAME("clk_cpll"), CNAME("clk_gpll_mux"), - CNAME("pclk_logic"), CNAME("sclk_vop"), - CNAME("mclk_i2s_8ch"), CNAME("i2s_mclkout"), - CNAME("dummy"), CNAME("clk_hdmirx_aud"), - CNAME("clk_hdmirx_cec"), CNAME("clk_imodet"), - CNAME("clk_txesc"), CNAME("clk_gpio_db0") }; - -static const struct clk_pll_data rk628_clk_plls[] = { - RK628_PLL(CGU_CLK_CPLL, CNAME("clk_cpll"), CNAME("xin_osc0_func"), - CRU_CPLL_CON0, - 0), - RK628_PLL(CGU_CLK_GPLL, CNAME("clk_gpll"), CNAME("xin_osc0_func"), - CRU_GPLL_CON0, - 0), -}; - -static const struct clk_mux_data rk628_clk_muxes[] = { - MUX(CGU_CLK_CPLL_MUX, CNAME("clk_cpll_mux"), mux_cpll_osc_p, - CRU_MODE_CON, 0, 1, - 0), - MUX(CGU_CLK_GPLL_MUX, CNAME("clk_gpll_mux"), mux_gpll_osc_p, - CRU_MODE_CON, 2, 1, - CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT), -}; - -static const struct clk_gate_data rk628_clk_gates[] = { - GATE(CGU_PCLK_GPIO0, CNAME("pclk_gpio0"), CNAME("pclk_logic"), - CRU_GATE_CON01, 0, - 0), - GATE(CGU_PCLK_GPIO1, CNAME("pclk_gpio1"), CNAME("pclk_logic"), - CRU_GATE_CON01, 1, - 0), - GATE(CGU_PCLK_GPIO2, CNAME("pclk_gpio2"), CNAME("pclk_logic"), - CRU_GATE_CON01, 2, - 0), - GATE(CGU_PCLK_GPIO3, CNAME("pclk_gpio3"), CNAME("pclk_logic"), - CRU_GATE_CON01, 3, - 0), - - GATE(CGU_PCLK_TXPHY_CON, CNAME("pclk_txphy_con"), CNAME("pclk_logic"), - CRU_GATE_CON02, 3, - CLK_IGNORE_UNUSED), - GATE(CGU_PCLK_EFUSE, CNAME("pclk_efuse"), CNAME("pclk_logic"), - CRU_GATE_CON00, 5, - 0), - GATE(0, CNAME("pclk_i2c2apb"), CNAME("pclk_logic"), - CRU_GATE_CON00, 3, - CLK_IGNORE_UNUSED), - GATE(0, CNAME("pclk_cru"), CNAME("pclk_logic"), - CRU_GATE_CON00, 1, - CLK_IGNORE_UNUSED), - GATE(0, CNAME("pclk_adapter"), CNAME("pclk_logic"), - CRU_GATE_CON00, 7, - CLK_IGNORE_UNUSED), - GATE(0, CNAME("pclk_regfile"), CNAME("pclk_logic"), - CRU_GATE_CON00, 2, - CLK_IGNORE_UNUSED), - GATE(CGU_PCLK_DSI0, CNAME("pclk_dsi0"), CNAME("pclk_logic"), - CRU_GATE_CON02, 6, - 0), - GATE(CGU_PCLK_DSI1, CNAME("pclk_dsi1"), CNAME("pclk_logic"), - CRU_GATE_CON02, 7, - 0), - GATE(CGU_PCLK_CSI, CNAME("pclk_csi"), CNAME("pclk_logic"), - CRU_GATE_CON02, 8, - 0), - GATE(CGU_PCLK_HDMITX, CNAME("pclk_hdmitx"), CNAME("pclk_logic"), - CRU_GATE_CON02, 4, - 0), - GATE(CGU_PCLK_RXPHY, CNAME("pclk_rxphy"), CNAME("pclk_logic"), - CRU_GATE_CON02, 0, - 0), - GATE(CGU_PCLK_HDMIRX, CNAME("pclk_hdmirx"), CNAME("pclk_logic"), - CRU_GATE_CON02, 2, - 0), - GATE(CGU_PCLK_GVIHOST, CNAME("pclk_gvihost"), CNAME("pclk_logic"), - CRU_GATE_CON02, 5, - 0), - GATE(CGU_CLK_CFG_DPHY0, CNAME("clk_cfg_dphy0"), CNAME("xin_osc0_func"), - CRU_GATE_CON02, 13, - 0), - GATE(CGU_CLK_CFG_DPHY1, CNAME("clk_cfg_dphy1"), CNAME("xin_osc0_func"), - CRU_GATE_CON02, 14, - 0), - GATE(CGU_CLK_TXESC, CNAME("clk_txesc"), CNAME("xin_osc0_func"), - CRU_GATE_CON02, 12, - 0), -}; - -static const struct clk_composite_data rk628_clk_composites[] = { - COMPOSITE(CGU_CLK_IMODET, CNAME("clk_imodet"), mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON05, 5, 1, - CRU_CLKSEL_CON05, 0, 5, - CRU_GATE_CON02, 11, - 0), - COMPOSITE(CGU_CLK_HDMIRX_AUD, CNAME("clk_hdmirx_aud"), - mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON05, 15, 1, - CRU_CLKSEL_CON05, 6, 8, - CRU_GATE_CON02, 10, - CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT), - COMPOSITE_FRAC_NOMUX(CGU_CLK_HDMIRX_CEC, CNAME("clk_hdmirx_cec"), - CNAME("xin_osc0_func"), - CRU_CLKSEL_CON12, - CRU_GATE_CON01, 15, - 0), - COMPOSITE_FRAC(CGU_CLK_RX_READ, CNAME("clk_rx_read"), - mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON02, 8, 1, - CRU_CLKSEL_CON14, - CRU_GATE_CON00, 11, - 0), - COMPOSITE_FRAC(CGU_SCLK_VOP, CNAME("sclk_vop"), mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON02, 9, 1, - CRU_CLKSEL_CON13, - CRU_GATE_CON00, 13, - CLK_SET_RATE_NO_REPARENT), - COMPOSITE(CGU_PCLK_LOGIC, CNAME("pclk_logic"), mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON00, 7, 1, - CRU_CLKSEL_CON00, 0, 5, - CRU_GATE_CON00, 0, - 0), - COMPOSITE_NOMUX(CGU_CLK_GPIO_DB0, CNAME("clk_gpio_db0"), - CNAME("xin_osc0_func"), - CRU_CLKSEL_CON08, 0, 10, - CRU_GATE_CON01, 4, - 0), - COMPOSITE_NOMUX(CGU_CLK_GPIO_DB1, CNAME("clk_gpio_db1"), - CNAME("xin_osc0_func"), - CRU_CLKSEL_CON09, 0, 10, - CRU_GATE_CON01, 5, - 0), - COMPOSITE_NOMUX(CGU_CLK_GPIO_DB2, CNAME("clk_gpio_db2"), - CNAME("xin_osc0_func"), - CRU_CLKSEL_CON10, 0, 10, - CRU_GATE_CON01, 6, - 0), - COMPOSITE_NOMUX(CGU_CLK_GPIO_DB3, CNAME("clk_gpio_db3"), - CNAME("xin_osc0_func"), - CRU_CLKSEL_CON11, 0, 10, - CRU_GATE_CON01, 7, - 0), - COMPOSITE(CGU_CLK_I2S_8CH_SRC, CNAME("clk_i2s_8ch_src"), - mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON03, 13, 1, - CRU_CLKSEL_CON03, 8, 5, - CRU_GATE_CON03, 9, - 0), - COMPOSITE_FRAC_NOMUX(CGU_CLK_I2S_8CH_FRAC, CNAME("clk_i2s_8ch_frac"), - CNAME("clk_i2s_8ch_src"), - CRU_CLKSEL_CON04, - CRU_GATE_CON03, 10, - 0), - COMPOSITE_NODIV(CGU_MCLK_I2S_8CH, CNAME("mclk_i2s_8ch"), - mux_mclk_i2s_8ch_p, - CRU_CLKSEL_CON03, 14, 2, - CRU_GATE_CON03, 11, - CLK_SET_RATE_PARENT), - COMPOSITE_NODIV(CGU_I2S_MCLKOUT, CNAME("i2s_mclkout"), - mux_i2s_mclkout_p, - CRU_CLKSEL_CON03, 7, 1, - CRU_GATE_CON03, 12, - CLK_SET_RATE_PARENT), - COMPOSITE(CGU_BT1120DEC, CNAME("clk_bt1120dec"), mux_cpll_gpll_mux_p, - CRU_CLKSEL_CON02, 7, 1, - CRU_CLKSEL_CON02, 0, 5, - CRU_GATE_CON00, 12, - 0), - COMPOSITE(CGU_CLK_TESTOUT, CNAME("clk_testout"), mux_clk_testout_p, - CRU_CLKSEL_CON06, 0, 4, - CRU_CLKSEL_CON06, 8, 6, - CRU_GATE_CON04, 7, - 0), -}; - -static void rk628_clk_add_lookup(struct rk628_cru *cru, struct clk *clk, - unsigned int id) -{ - if (cru->clk_data.clks && id) - cru->clk_data.clks[id] = clk; -} - -static void rk628_clk_register_muxes(struct rk628_cru *cru) -{ - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rk628_clk_muxes); i++) { - const struct clk_mux_data *data = &rk628_clk_muxes[i]; - - clk = devm_clk_regmap_register_mux(cru->dev, data->name, - data->parent_names, - data->num_parents, - cru->regmap, data->reg, - data->shift, data->width, - data->flags); - if (IS_ERR(clk)) { - dev_err(cru->dev, "failed to register clock %s\n", - data->name); - continue; - } - - rk628_clk_add_lookup(cru, clk, data->id); - } -} - -static void rk628_clk_register_gates(struct rk628_cru *cru) -{ - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rk628_clk_gates); i++) { - const struct clk_gate_data *data = &rk628_clk_gates[i]; - - clk = devm_clk_regmap_register_gate(cru->dev, data->name, - data->parent_name, - cru->regmap, - data->reg, data->shift, - data->flags); - if (IS_ERR(clk)) { - dev_err(cru->dev, "failed to register clock %s\n", - data->name); - continue; - } - - rk628_clk_add_lookup(cru, clk, data->id); - } -} - -static void rk628_clk_register_composites(struct rk628_cru *cru) -{ - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rk628_clk_composites); i++) { - const struct clk_composite_data *data = - &rk628_clk_composites[i]; - - clk = devm_clk_regmap_register_composite(cru->dev, data->name, - data->parent_names, - data->num_parents, - cru->regmap, - data->mux_reg, - data->mux_shift, - data->mux_width, - data->div_reg, - data->div_shift, - data->div_width, - data->div_flags, - data->gate_reg, - data->gate_shift, - data->flags); - if (IS_ERR(clk)) { - dev_err(cru->dev, "failed to register clock %s\n", - data->name); - continue; - } - - rk628_clk_add_lookup(cru, clk, data->id); - } -} - -static void rk628_clk_register_plls(struct rk628_cru *cru) -{ - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rk628_clk_plls); i++) { - const struct clk_pll_data *data = &rk628_clk_plls[i]; - - clk = devm_clk_regmap_register_pll(cru->dev, data->name, - data->parent_name, - cru->regmap, - data->reg, - data->pd_shift, - data->dsmpd_shift, - data->lock_shift, - data->flags); - if (IS_ERR(clk)) { - dev_err(cru->dev, "failed to register clock %s\n", - data->name); - continue; - } - - rk628_clk_add_lookup(cru, clk, data->id); - } -} - -struct rk628_rgu_data { - unsigned int id; - unsigned int reg; - unsigned int bit; -}; - -#define RSTGEN(_id, _reg, _bit) \ - { \ - .id = (_id), \ - .reg = (_reg), \ - .bit = (_bit), \ - } - -static const struct rk628_rgu_data rk628_rgu_data[] = { - RSTGEN(RGU_LOGIC, CRU_SOFTRST_CON00, 0), - RSTGEN(RGU_CRU, CRU_SOFTRST_CON00, 1), - RSTGEN(RGU_REGFILE, CRU_SOFTRST_CON00, 2), - RSTGEN(RGU_I2C2APB, CRU_SOFTRST_CON00, 3), - RSTGEN(RGU_EFUSE, CRU_SOFTRST_CON00, 5), - RSTGEN(RGU_ADAPTER, CRU_SOFTRST_CON00, 7), - RSTGEN(RGU_CLK_RX, CRU_SOFTRST_CON00, 11), - RSTGEN(RGU_BT1120DEC, CRU_SOFTRST_CON00, 12), - RSTGEN(RGU_VOP, CRU_SOFTRST_CON00, 13), - - RSTGEN(RGU_GPIO0, CRU_SOFTRST_CON01, 0), - RSTGEN(RGU_GPIO1, CRU_SOFTRST_CON01, 1), - RSTGEN(RGU_GPIO2, CRU_SOFTRST_CON01, 2), - RSTGEN(RGU_GPIO3, CRU_SOFTRST_CON01, 3), - RSTGEN(RGU_GPIO_DB0, CRU_SOFTRST_CON01, 4), - RSTGEN(RGU_GPIO_DB1, CRU_SOFTRST_CON01, 5), - RSTGEN(RGU_GPIO_DB2, CRU_SOFTRST_CON01, 6), - RSTGEN(RGU_GPIO_DB3, CRU_SOFTRST_CON01, 7), - - RSTGEN(RGU_RXPHY, CRU_SOFTRST_CON02, 0), - RSTGEN(RGU_HDMIRX, CRU_SOFTRST_CON02, 2), - RSTGEN(RGU_TXPHY_CON, CRU_SOFTRST_CON02, 3), - RSTGEN(RGU_HDMITX, CRU_SOFTRST_CON02, 4), - RSTGEN(RGU_GVIHOST, CRU_SOFTRST_CON02, 5), - RSTGEN(RGU_DSI0, CRU_SOFTRST_CON02, 6), - RSTGEN(RGU_DSI1, CRU_SOFTRST_CON02, 7), - RSTGEN(RGU_CSI, CRU_SOFTRST_CON02, 8), - RSTGEN(RGU_TXDATA, CRU_SOFTRST_CON02, 9), - RSTGEN(RGU_DECODER, CRU_SOFTRST_CON02, 10), - RSTGEN(RGU_ENCODER, CRU_SOFTRST_CON02, 11), - RSTGEN(RGU_HDMIRX_PON, CRU_SOFTRST_CON02, 12), - RSTGEN(RGU_TXBYTEHS, CRU_SOFTRST_CON02, 13), - RSTGEN(RGU_TXESC, CRU_SOFTRST_CON02, 14), -}; - -static int rk628_rgu_update(struct rk628_cru *cru, unsigned long id, int assert) -{ - const struct rk628_rgu_data *data = &rk628_rgu_data[id]; - - return regmap_write(cru->regmap, data->reg, - BIT(data->bit + 16) | (assert << data->bit)); -} - -static int rk628_rgu_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct rk628_cru *cru = reset_to_cru(rcdev); - - return rk628_rgu_update(cru, id, 1); -} - -static int rk628_rgu_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct rk628_cru *cru = reset_to_cru(rcdev); - - return rk628_rgu_update(cru, id, 0); -} - -static struct reset_control_ops rk628_rgu_ops = { - .assert = rk628_rgu_assert, - .deassert = rk628_rgu_deassert, -}; - -static int rk628_reset_controller_register(struct rk628_cru *cru) -{ - struct device *dev = cru->dev; - - cru->rcdev.owner = THIS_MODULE; - cru->rcdev.nr_resets = ARRAY_SIZE(rk628_rgu_data); - cru->rcdev.of_node = dev->of_node; - cru->rcdev.ops = &rk628_rgu_ops; - - return devm_reset_controller_register(dev, &cru->rcdev); -} - -static const struct regmap_range rk628_cru_readable_ranges[] = { - regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4), - regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4), - regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON), - regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21), - regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05), - regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04), -}; - -static const struct regmap_access_table rk628_cru_readable_table = { - .yes_ranges = rk628_cru_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges), -}; - -static const struct regmap_config rk628_cru_regmap_config = { - .name = "cru", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = CRU_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_cru_readable_table, -}; - -static void rk628_cru_init(struct rk628_cru *cru) -{ - u32 val = 0; - u8 mcu_mode; - - regmap_read(cru->parent->grf, GRF_SYSTEM_STATUS0, &val); - mcu_mode = (val & I2C_ONLY_FLAG) ? 0 : 1; - if (mcu_mode) - return; - - /* clock switch and first set gpll almost 99MHz */ - regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff701d); - usleep_range(1000, 1100); - /* set clk_gpll_mux from gpll */ - regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0004); - usleep_range(1000, 1100); - /* set pclk_logic from clk_gpll_mux and set pclk div 4 */ - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0080); - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0083); - /* set cpll almost 400MHz */ - regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff3063); - usleep_range(1000, 1100); - /* set clk_cpll_mux from clk_cpll */ - regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0005); - /* set pclk use cpll, now div is 4 */ - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0003); - /* set pclk use cpll, now div is 12 */ - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b); - /* gpll 983.04MHz */ - regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff1028); - usleep_range(1000, 1100); - /* set pclk use gpll, nuw div is 0xb */ - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff008b); - /* set cpll 1188MHz */ - regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff1063); - usleep_range(1000, 1100); - /* set pclk use cpll, and set pclk 99MHz */ - regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b); -} - -static int rk628_cru_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct rk628_cru *cru; - struct clk **clk_table; - unsigned int i; - int ret; - - cru = devm_kzalloc(dev, sizeof(*cru), GFP_KERNEL); - if (!cru) - return -ENOMEM; - - cru->dev = dev; - cru->parent = rk628; - platform_set_drvdata(pdev, cru); - - cru->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_cru_regmap_config); - if (IS_ERR(cru->regmap)) { - ret = PTR_ERR(cru->regmap); - dev_err(dev, "failed to allocate register map: %d\n", ret); - return ret; - } - - rk628_cru_init(cru); - - clk_table = devm_kcalloc(dev, CGU_NR_CLKS, sizeof(struct clk *), - GFP_KERNEL); - if (!clk_table) - return -ENOMEM; - - for (i = 0; i < CGU_NR_CLKS; i++) - clk_table[i] = ERR_PTR(-ENOENT); - - cru->clk_data.clks = clk_table; - cru->clk_data.clk_num = CGU_NR_CLKS; - - rk628_clk_register_plls(cru); - rk628_clk_register_muxes(cru); - rk628_clk_register_gates(cru); - rk628_clk_register_composites(cru); - rk628_reset_controller_register(cru); - - clk_prepare_enable(clk_table[CGU_PCLK_LOGIC]); - - return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, - &cru->clk_data); -} - -static int rk628_cru_remove(struct platform_device *pdev) -{ - of_clk_del_provider(pdev->dev.of_node); - - return 0; -} - -static const struct of_device_id rk628_cru_of_match[] = { - { .compatible = "rockchip,rk628-cru", }, - {}, -}; -MODULE_DEVICE_TABLE(of, rk628_cru_of_match); - -static struct platform_driver rk628_cru_driver = { - .driver = { - .name = "rk628-cru", - .of_match_table = of_match_ptr(rk628_cru_of_match), - }, - .probe = rk628_cru_probe, - .remove = rk628_cru_remove, -}; -module_platform_driver(rk628_cru_driver); - -MODULE_AUTHOR("Wyon Bi "); -MODULE_DESCRIPTION("Rockchip RK628 CRU driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 62eba6cfd6e5..6472c537a716 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -165,7 +165,6 @@ config ROCKCHIP_DW_HDCP2 Designware HDCP2 Controller. source "drivers/gpu/drm/rockchip/rk618/Kconfig" -source "drivers/gpu/drm/rockchip/rk628/Kconfig" source "drivers/gpu/drm/rockchip/ebc-dev/Kconfig" endif diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 575f72b803cd..1cbe8bc70229 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -31,5 +31,4 @@ rockchipdrm-$(CONFIG_DRM_ROCKCHIP_VVOP) += rockchip_drm_vvop.o obj-$(CONFIG_ROCKCHIP_DW_HDCP2) += dw_hdcp2.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618/ -obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628/ obj-$(CONFIG_ROCKCHIP_EBC_DEV) += ebc-dev/ diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 67b2425b9b66..2a1cd92fd1b8 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -933,6 +933,8 @@ static const struct drm_prop_enum_list color_format_enum_list[] = { { RK_IF_FORMAT_YCBCR444, "ycbcr444" }, { RK_IF_FORMAT_YCBCR422, "ycbcr422" }, { RK_IF_FORMAT_YCBCR420, "ycbcr420" }, + { RK_IF_FORMAT_YCBCR_HQ, "ycbcr_high_subsampling" }, + { RK_IF_FORMAT_YCBCR_LQ, "ycbcr_low_subsampling" }, }; static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format) @@ -1360,7 +1362,7 @@ static int dw_dp_connector_atomic_check(struct drm_connector *conn, } if ((dp_new_state->color_format < RK_IF_FORMAT_RGB) || - (dp_new_state->color_format > RK_IF_FORMAT_YCBCR420)) { + (dp_new_state->color_format > RK_IF_FORMAT_YCBCR_LQ)) { dev_err(dp->dev, "set invalid color format:%d\n", dp_new_state->color_format); return -EINVAL; } @@ -3250,6 +3252,21 @@ static struct edid *dw_dp_bridge_get_edid(struct drm_bridge *bridge, return edid; } +static void dw_dp_swap_fmts(u32 *fmt, int count) +{ + int i; + u32 temp_fmt; + + if (!count) + return; + + for (i = 0; i < count / 2; i++) { + temp_fmt = fmt[i]; + fmt[i] = fmt[count - i - 1]; + fmt[count - i - 1] = temp_fmt; + } +} + static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -3314,7 +3331,11 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, continue; if (dp_state->bpc != 0) { - if ((fmt->bpc != dp_state->bpc) || + if (fmt->bpc != dp_state->bpc) + continue; + + if (dp_state->color_format != RK_IF_FORMAT_YCBCR_HQ && + dp_state->color_format != RK_IF_FORMAT_YCBCR_LQ && (fmt->color_format != BIT(dp_state->color_format))) continue; } @@ -3325,6 +3346,9 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, output_fmts[j++] = fmt->bus_format; } + if (dp_state->color_format == RK_IF_FORMAT_YCBCR_LQ) + dw_dp_swap_fmts(output_fmts, j); + *num_output_fmts = j; return output_fmts; diff --git a/drivers/gpu/drm/rockchip/rk628/Kconfig b/drivers/gpu/drm/rockchip/rk628/Kconfig deleted file mode 100644 index 41e1fbbe1e61..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -config DRM_ROCKCHIP_RK628 - tristate "Rockchip RK628 display bridge driver" - depends on DRM_ROCKCHIP - depends on MFD_RK628 - help - Rockchip RK628 display bridge chips driver. diff --git a/drivers/gpu/drm/rockchip/rk628/Makefile b/drivers/gpu/drm/rockchip/rk628/Makefile deleted file mode 100644 index 76d768d29776..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the Rockchip RK628 display bridge driver. -# - -obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \ - rk628_combtxphy.o \ - rk628_dsi.o \ - rk628_gvi.o \ - rk628_lvds.o \ - rk628_post_process.o \ - rk628_rgb.o \ - rk628_hdmi.o \ - rk628_hdmirx.o diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c deleted file mode 100644 index a83eeeaf935f..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c +++ /dev/null @@ -1,1030 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Algea Cao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct rk628_combrxphy { - struct device *dev; - struct rk628 *parent; - struct regmap *regmap; - struct clk *pclk; - struct reset_control *rstc; - bool is_cable_mode; -}; - -#define REG(x) ((x) + 0x10000) -#define COMBRXPHY_MAX_REGISTER REG(0x6790) - -#define MAX_ROUND 6 -#define MAX_DATA_NUM 16 -#define MAX_CHANNEL 3 -#define CLK_DET_TRY_TIMES 10 -#define CLK_STABLE_LOOP_CNT 10 -#define CLK_STABLE_THRESHOLD 6 - -static int debug; -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "debug level (0-1)"); - -static void rk628_combrxphy_set_data_of_round(u32 *data, u32 *data_in) -{ - if ((data != NULL) && (data_in != NULL)) { - data_in[0] = data[0]; - data_in[1] = data[7]; - data_in[2] = data[13]; - data_in[3] = data[14]; - data_in[4] = data[15]; - data_in[5] = data[1]; - data_in[6] = data[2]; - data_in[7] = data[3]; - data_in[8] = data[4]; - data_in[9] = data[5]; - data_in[10] = data[6]; - data_in[11] = data[8]; - data_in[12] = data[9]; - data_in[13] = data[10]; - data_in[14] = data[11]; - data_in[15] = data[12]; - } -} - -static void -rk628_combrxphy_max_zero_of_round(struct rk628_combrxphy *combrxphy, - u32 *data_in, u32 *max_zero, u32 *max_val, - int n, int ch) -{ - u32 i; - u32 cnt = 0; - u32 max_cnt = 0; - u32 max_v = 0; - - if (debug > 0) { - dev_info(combrxphy->dev, - "%s channel:%d, round:%d ====\n", __func__, ch, n); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - data_in, MAX_DATA_NUM * sizeof(u32), false); - } - - for (i = 0; i < MAX_DATA_NUM; i++) { - if (max_v < data_in[i]) - max_v = data_in[i]; - } - - for (i = 0; i < MAX_DATA_NUM; i++) { - if (data_in[i] == 0) - cnt = cnt + 200; - else if ((data_in[i] > 0) && (data_in[i] < 100)) - cnt = cnt + 100 - data_in[i]; - } - max_cnt = (cnt >= 3200) ? 0 : cnt; - - max_zero[n] = max_cnt; - max_val[n] = max_v; - dev_dbg(combrxphy->dev, - "channel:%d, round:%d, max_zero_cnt:%d, max_val:%#x", - ch, n, max_zero[n], max_val[n]); -} - -static int -rk628_combrxphy_chose_round_for_ch(struct rk628_combrxphy *combrxphy, - u32 *rd_max_zero, - u32 *rd_max_val, int ch) -{ - int i, rd = 0; - u32 max = 0; - u32 max_v = 0; - - if (debug > 0) { - dev_info(combrxphy->dev, - "%s max cnt of channel:%d ====\n", __func__, ch); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - rd_max_zero, MAX_ROUND * sizeof(u32), false); - - dev_info(combrxphy->dev, - "%s max value of channel:%d ====\n", __func__, ch); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - rd_max_val, MAX_ROUND * sizeof(u32), false); - } - - for (i = 0; i < MAX_ROUND; i++) { - if (rd_max_zero[i] > max) { - max = rd_max_zero[i]; - max_v = rd_max_val[i]; - rd = i; - } else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) { - max = rd_max_zero[i]; - max_v = rd_max_val[i]; - rd = i; - } - } - - dev_dbg(combrxphy->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd); - return rd; -} - -static void rk628_combrxphy_get_data_of_round(struct rk628_combrxphy - *combrxphy, u32 *data) -{ - u32 i; - - for (i = 0; i < MAX_DATA_NUM; i++) - regmap_read(combrxphy->regmap, REG(0x6740 + i * 4), &data[i]); -} - -static void -rk628_combrxphy_set_dc_gain(struct rk628_combrxphy *combrxphy, - u32 x, u32 y, u32 z) -{ - u32 val; - u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2; - - dev_dbg(combrxphy->dev, "channel dc gain ch0:%d, ch1:%d, ch2:%d\n", - x, y, z); - - dc_gain_ch0 = x & 0xf; - dc_gain_ch1 = y & 0xf; - dc_gain_ch2 = z & 0xf; - regmap_read(combrxphy->regmap, REG(0x661c), &val); - - val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) | - (dc_gain_ch2 << 4); - regmap_write(combrxphy->regmap, REG(0x661c), val); -} - -static void rk628_combrxphy_set_sample_edge_round(struct rk628_combrxphy - *combrxphy, u32 x, u32 y, u32 z) -{ - u32 val; - u32 equ_gain_ch0, equ_gain_ch1, equ_gain_ch2; - - dev_dbg(combrxphy->dev, "channel equ gain ch0:%d, ch1:%d, ch2:%d\n", - x, y, z); - - equ_gain_ch0 = (x & 0xf); - equ_gain_ch1 = (y & 0xf); - equ_gain_ch2 = (z & 0xf); - regmap_read(combrxphy->regmap, REG(0x6618), &val); - val = (val & 0xff00f0ff) | (equ_gain_ch1 << 20) | - (equ_gain_ch0 << 16) | (equ_gain_ch2 << 8); - regmap_write(combrxphy->regmap, REG(0x6618), val); -} - -static void rk628_combrxphy_start_sample_edge(struct rk628_combrxphy *combrxphy) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val &= 0xfffff1ff; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = (val & 0xfffff1ff) | (0x7 << 9); - regmap_write(combrxphy->regmap, REG(0x66f0), val); -} - -static void -rk628_combrxphy_set_sample_edge_mode(struct rk628_combrxphy *combrxphy, - int ch) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6634), &val); - val = val & (~(0xf << ((ch + 1) * 4))); - regmap_write(combrxphy->regmap, REG(0x6634), val); -} - -static void rk628_combrxphy_select_channel(struct rk628_combrxphy *combrxphy, - int ch) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6700), &val); - val = (val & 0xfffffffc) | (ch & 0x3); - regmap_write(combrxphy->regmap, REG(0x6700), val); -} - -static void rk628_combrxphy_cfg_6730(struct rk628_combrxphy *combrxphy) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6730), &val); - val = (val & 0xffff0000) | 0x1; - regmap_write(combrxphy->regmap, REG(0x6730), val); -} - -static void rk628_combrxphy_sample_edge_procedure_for_cable( - struct rk628_combrxphy *combrxphy, u32 cdr_mode) -{ - u32 n, ch; - u32 data[MAX_DATA_NUM]; - u32 data_in[MAX_DATA_NUM]; - u32 round_max_zero[MAX_CHANNEL][MAX_ROUND]; - u32 round_max_value[MAX_CHANNEL][MAX_ROUND]; - u32 ch_round[MAX_CHANNEL]; - u32 edge, dc_gain; - u32 rd_offset; - - /* Step1: set sample edge mode for channel 0~2 */ - for (ch = 0; ch < MAX_CHANNEL; ch++) - rk628_combrxphy_set_sample_edge_mode(combrxphy, ch); - - /* step2: once per round */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_cfg_6730(combrxphy); - } - - /* step3: config sample edge until the end of one frame - * (for example 1080p:2200*1125=32’h25c3f8) - */ - if (cdr_mode < 16) { - dc_gain = 0; - rd_offset = 0; - } else if (cdr_mode < 18) { - dc_gain = 1; - rd_offset = 0; - } else { - dc_gain = 3; - rd_offset = 2; - } - - /* When the pix clk is the same, the low frame rate resolution is used - * to calculate the sampling window (the frame rate is not less than - * 30). The sampling delay time is configured as 40ms. - */ - if (cdr_mode <= 1) { /* 27M vic17 720x576P50 */ - edge = 864 * 625; - } else if (cdr_mode <= 4) { /* 59.4M vic81 1680x720P30 */ - edge = 2640 * 750; - } else if (cdr_mode <= 7) { /* 74.25M vic34 1920x1080P30 */ - edge = 2200 * 1125; - } else if (cdr_mode <= 14) { /* 119M vic88 2560x1180P30 */ - edge = 3520 * 1125; - } else if (cdr_mode <= 16) { /* 148.5M vic31 1920x1080P50 */ - edge = 2640 * 1125; - } else if (cdr_mode <= 17) { /* 162M vic89 2560x1080P50 */ - edge = 3300 * 1125; - } else if (cdr_mode <= 18) { /* 297M vic95 3840x2160P30 */ - edge = 4400 * 2250; - } else { /* unkonw vic16 1920x1080P60 */ - edge = 2200 * 1125; - } - - dev_info(combrxphy->dev, - "cdr_mode:%d, dc_gain:%d, rd_offset:%d, edge:%#x\n", - cdr_mode, dc_gain, rd_offset, edge); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - regmap_write(combrxphy->regmap, REG(0x6708), edge); - } - - rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain); - for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) { - /* step4:set sample edge round value n,n=0(n=0~31) */ - rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n); - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - /* step7: get data of round n */ - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_get_data_of_round(combrxphy, data); - rk628_combrxphy_set_data_of_round(data, data_in); - /* step8: get the max constant value of round n */ - rk628_combrxphy_max_zero_of_round(combrxphy, data_in, - round_max_zero[ch], round_max_value[ch], - n - rd_offset, ch); - } - } - - /* step9: after finish round, get the max constant value and - * corresponding value n. - */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - ch_round[ch] = rk628_combrxphy_chose_round_for_ch(combrxphy, - round_max_zero[ch], round_max_value[ch], ch) - + rd_offset; - } - dev_info(combrxphy->dev, "last equ gain ch0:%d, ch1:%d, ch2:%d\n", - ch_round[0], ch_round[1], ch_round[2]); - - /* step10: write result to sample edge round value */ - rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0], - ch_round[1], ch_round[2]); - - /* do step5, step6 again */ - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); -} - -static void -rk628_combrxphy_sample_edge_procedure(struct rk628_combrxphy *combrxphy, - int f, u32 rd_offset) -{ - u32 n, ch; - u32 data[MAX_DATA_NUM]; - u32 data_in[MAX_DATA_NUM]; - u32 round_max_zero[MAX_CHANNEL][MAX_ROUND]; - u32 round_max_value[MAX_CHANNEL][MAX_ROUND]; - u32 ch_round[MAX_CHANNEL]; - u32 edge, dc_gain; - - dev_dbg(combrxphy->dev, "%s in!", __func__); - /* Step1: set sample edge mode for channel 0~2 */ - for (ch = 0; ch < MAX_CHANNEL; ch++) - rk628_combrxphy_set_sample_edge_mode(combrxphy, ch); - - dev_dbg(combrxphy->dev, "step1 set sample edge mode ok!"); - - /* step2: once per round */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_cfg_6730(combrxphy); - } - dev_dbg(combrxphy->dev, "step2 once per round ok!"); - - /* - * step3:config sample edge until the end of one frame - * (for example 1080p:2200*1125=32’h25c3f8) - */ - switch (f) { - case 27000: - edge = 858 * 525; - dc_gain = 0; - break; - case 64000: - edge = 1317 * 810; - dc_gain = 0; - break; - case 74250: - edge = 1650 * 750; - dc_gain = 0; - break; - case 148500: - edge = 2200 * 1125; - dc_gain = 1; - break; - case 297000: - dc_gain = 3; - edge = 4400 * 2250; - break; - case 594000: - dc_gain = 0xf; - edge = 4400 * 2250; - break; - default: - edge = 2200 * 1125; - dc_gain = 1; - break; - } - dev_dbg(combrxphy->dev, "===>>> f:%d, edge:%#x", f, edge); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - regmap_write(combrxphy->regmap, REG(0x6708), edge); - } - dev_dbg(combrxphy->dev, "step3 cfg sample edge ok!"); - - rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain); - - for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) { - /* step4:set sample edge round value n,n=0(n=0~31) */ - rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n); - dev_dbg(combrxphy->dev, "step4 ok!"); - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - dev_dbg(combrxphy->dev, "step5 ok!"); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - /* step7:get data of round n */ - rk628_combrxphy_select_channel(combrxphy, ch); - dev_dbg(combrxphy->dev, "step7 set ch ok!"); - rk628_combrxphy_get_data_of_round(combrxphy, data); - dev_dbg(combrxphy->dev, "step7 get data ok!"); - rk628_combrxphy_set_data_of_round(data, data_in); - dev_dbg(combrxphy->dev, "step7 set data ok!"); - rk628_combrxphy_max_zero_of_round(combrxphy, data_in, - round_max_zero[ch], - round_max_value[ch], - n - rd_offset, ch); - } - } - for (ch = 0; ch < MAX_CHANNEL; ch++) - ch_round[ch] = - rk628_combrxphy_chose_round_for_ch(combrxphy, - round_max_zero[ch], - round_max_value[ch], - ch) + rd_offset; - - /* - * step8:after finish round 31, get the max constant value and - * corresponding value n. - * write result to sample edge round value. - */ - rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0], - ch_round[1], ch_round[2]); - - /* do step5, step6 again */ - dev_dbg(combrxphy->dev, "do step5 step6 again!"); - rk628_combrxphy_start_sample_edge(combrxphy); - usleep_range(40*1000, 41*1000); -} - -static int rk628_combrxphy_try_clk_detect(struct rk628_combrxphy *combrxphy) -{ - u32 val, i; - int ret; - - ret = -1; - reset_control_assert(combrxphy->rstc); - usleep_range(10, 20); - reset_control_deassert(combrxphy->rstc); - usleep_range(10, 20); - - /* step1: set pin_rst_n to 1’b0.wait 1 period(1us).release reset */ - /* step2: select pll clock src and enable auto check */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - /* clear bit0 and bit3 */ - val = val & 0xfffffff6; - regmap_write(combrxphy->regmap, REG(0x6630), val); - /* step3: select hdmi mode and enable chip, read reg6654, - * make sure auto setup done. - */ - /* auto fsm reset related */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val = val | BIT(24); - regmap_write(combrxphy->regmap, REG(0x6630), val); - /* pull down ana rstn */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = val & 0xfffffeff; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - /* pull down dig rstn */ - regmap_read(combrxphy->regmap, REG(0x66f4), &val); - val = val & 0xfffffffe; - regmap_write(combrxphy->regmap, REG(0x66f4), val); - /* pull up ana rstn */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = val | 0x100; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - /* pull up dig rstn */ - regmap_read(combrxphy->regmap, REG(0x66f4), &val); - val = val | 0x1; - regmap_write(combrxphy->regmap, REG(0x66f4), val); - - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - /* set bit0 and bit2 to 1*/ - val = (val & 0xfffffff8) | 0x5; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - - /* auto fsm en = 0 */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - /* set bit0 and bit2 to 1*/ - val = (val & 0xfffffff8) | 0x4; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - - for (i = 0; i < 10; i++) { - usleep_range(500, 510); - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0xf0000000) == 0x80000000) { - ret = 0; - dev_info(combrxphy->dev, "clock detected!"); - break; - } - } - - return ret; -} - -static int -rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628_combrxphy *combrxphy, - int f) -{ - u32 val, val_a, val_b, data_a, data_b; - u32 i, j, count, ret; - u32 cdr_mode, cdr_data, pll_man; - u32 tmds_bitrate_per_lane; - u32 cdr_data_min, cdr_data_max; - - /* - * use the mode of automatic clock detection, only supports fixed TMDS - * frequency.Refer to register 0x6654[21:16]: - * 5'd31:Error mode - * 5'd30:manual mode detected - * 5'd18:rx3p clock = 297MHz - * 5'd17:rx3p clock = 162MHz - * 5'd16:rx3p clock = 148.5MHz - * 5'd15:rx3p clock = 135MHz - * 5'd14:rx3p clock = 119MHz - * 5'd13:rx3p clock = 108MHz - * 5'd12:rx3p clock = 101MHz - * 5'd11:rx3p clock = 92.8125MHz - * 5'd10:rx3p clock = 88.75MHz - * 5'd9:rx3p clock = 85.5MHz - * 5'd8:rx3p clock = 83.5MHz - * 5'd7:rx3p clock = 74.25MHz - * 5'd6:rx3p clock = 68.25MHz - * 5'd5:rx3p clock = 65MHz - * 5'd4:rx3p clock = 59.4MHz - * 5'd3:rx3p clock = 40MHz - * 5'd2:rx3p clock = 33.75MHz - * 5'd1:rx3p clock = 27MHz - * 5'd0:rx3p clock = 25.17MHz - */ - - const u32 cdr_mode_to_khz[] = { - 25170, 27000, 33750, 40000, 59400, 65000, 68250, - 74250, 83500, 85500, 88750, 92812, 101000, 108000, - 119000, 135000, 148500, 162000, 297000, - }; - - for (i = 0; i < CLK_DET_TRY_TIMES; i++) { - if (rk628_combrxphy_try_clk_detect(combrxphy) >= 0) - break; - usleep_range(100*1000, 100*1000); - } - regmap_read(combrxphy->regmap, REG(0x6654), &val); - dev_info(combrxphy->dev, "clk det over cnt:%d, reg_0x6654:%#x", i, val); - - regmap_read(combrxphy->regmap, REG(0x6620), &val); - if ((i == CLK_DET_TRY_TIMES) || - ((val & 0x7f000000) == 0) || - ((val & 0x007f0000) == 0) || - ((val & 0x00007f00) == 0) || - ((val & 0x0000007f) == 0)) { - dev_info(combrxphy->dev, - "clock detected failed, cfg resistance manual!"); - regmap_write(combrxphy->regmap, REG(0x6620), 0x66666666); - regmap_update_bits(combrxphy->regmap, REG(0x6604), BIT(31), - BIT(31)); - usleep_range(1000, 1100); - } - - /* step4: get cdr_mode and cdr_data */ - for (j = 0; j < CLK_STABLE_LOOP_CNT ; j++) { - cdr_data_min = 0xffffffff; - cdr_data_max = 0; - - for (i = 0; i < CLK_DET_TRY_TIMES; i++) { - regmap_read(combrxphy->regmap, REG(0x6654), &val); - cdr_data = val & 0xffff; - if (cdr_data <= cdr_data_min) - cdr_data_min = cdr_data; - if (cdr_data >= cdr_data_max) - cdr_data_max = cdr_data; - udelay(50); - } - - if (((cdr_data_max - cdr_data_min) <= CLK_STABLE_THRESHOLD) && - (cdr_data_min >= 60)) { - dev_info(combrxphy->dev, "clock stable!"); - break; - } - } - - if (j == CLK_STABLE_LOOP_CNT) { - regmap_read(combrxphy->regmap, REG(0x6630), &val_a); - regmap_read(combrxphy->regmap, REG(0x6608), &val_b); - dev_err(combrxphy->dev, - "err, clk not stable, reg_0x6630:%#x, reg_0x6608:%#x", - val_a, val_b); - - return -EINVAL; - } - - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0x1f0000) == 0x1f0000) { - regmap_read(combrxphy->regmap, REG(0x6630), &val_a); - regmap_read(combrxphy->regmap, REG(0x6608), &val_b); - dev_err(combrxphy->dev, - "clock error: 0x1f, reg_0x6630:%#x, reg_0x6608:%#x", - val_a, val_b); - - return -EINVAL; - } - - cdr_mode = (val >> 16) & 0x1f; - cdr_data = val & 0xffff; - dev_info(combrxphy->dev, "cdr_mode:%d, cdr_data:%d\n", cdr_mode, - cdr_data); - - /* step5: manually configure PLL - * cfg reg 66a8 tmds clock div2 for rgb/yuv444 as default - * reg 662c[16:8] pll_pre_div - */ - if (f <= 340000) { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } else { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } - - /* when tmds bitrate/lane <= 340M, bitrate/lane = pix_clk * 10 */ - tmds_bitrate_per_lane = cdr_mode_to_khz[cdr_mode] * 10; - if (tmds_bitrate_per_lane < 400000) - pll_man = 0x7960c; - else if (tmds_bitrate_per_lane < 600000) - pll_man = 0x7750c; - else if (tmds_bitrate_per_lane < 800000) - pll_man = 0x7964c; - else if (tmds_bitrate_per_lane < 1000000) - pll_man = 0x7754c; - else if (tmds_bitrate_per_lane < 1600000) - pll_man = 0x7a108; - else if (tmds_bitrate_per_lane < 2400000) - pll_man = 0x73588; - else if (tmds_bitrate_per_lane < 3400000) - pll_man = 0x7a108; - else - pll_man = 0x7f0c8; - - dev_info(combrxphy->dev, "cdr_mode:%d, pll_man:%#x\n", cdr_mode, - pll_man); - regmap_write(combrxphy->regmap, REG(0x6630), pll_man); - - /* step6: EQ and SAMPLE cfg */ - rk628_combrxphy_sample_edge_procedure_for_cable(combrxphy, cdr_mode); - - /* step7: Deassert fifo reset,enable fifo write and read */ - /* reset rx_infifo */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003); - /* rx_infofo wr/rd disable */ - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060); - /* deassert rx_infifo reset */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083); - /* enable rx_infofo wr/rd en */ - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060); - /* cfg 0x2260 high_8b to 0x66ac high_8b, low_8b to 0x66b0 low_8b */ - regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24), - UPDATE(0x22, 31, 24)); - usleep_range(5*1000, 6*1000); - - /* step8: check all 3 data channels alignment */ - count = 0; - for (i = 0; i < 100; i++) { - usleep_range(100, 110); - regmap_read(combrxphy->regmap, REG(0x66b4), &data_a); - regmap_read(combrxphy->regmap, REG(0x66b8), &data_b); - /* ch0 ch1 ch2 lock */ - if (((data_a & 0x00ff00ff) == 0x00ff00ff) && - ((data_b & 0xff) == 0xff)) { - count++; - } - } - - if (count >= 100) { - dev_info(combrxphy->dev, "channel alignment done"); - dev_info(combrxphy->dev, "rx initial done"); - ret = 0; - } else if (count > 0) { - dev_err(combrxphy->dev, "link not stable, count:%d of 100", - count); - ret = 0; - } else { - dev_err(combrxphy->dev, "channel alignment failed!"); - ret = -EINVAL; - } - - return ret; -} - -static int rk628_combrxphy_set_hdmi_mode(struct rk628_combrxphy *combrxphy, - int bus_width) -{ - u32 val, data_a, data_b, f, val2 = 0; - int i, ret, count; - u32 pll_man, rd_offset; - bool is_yuv420; - - is_yuv420 = bus_width & BIT(30); - - if (is_yuv420) - f = (bus_width & 0xffffff) / 2; - else - f = bus_width & 0xffffff; - - dev_dbg(combrxphy->dev, "f:%d\n", f); - - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val &= ~BIT(23); - val |= 0x18; - regmap_write(combrxphy->regmap, REG(0x6630), val); - - /* enable cal */ - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0x18000000; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - usleep_range(10*1000, 11*1000); - /* disable cal */ - val &= ~BIT(28); - val |= BIT(27); - regmap_write(combrxphy->regmap, REG(0x6610), val); - - /* save cal val */ - regmap_read(combrxphy->regmap, REG(0x6614), &val); - if (!(val & 0x3f00)) { - dev_err(combrxphy->dev, "resistor error\n"); - return -EINVAL; - } - - val &= 0x3f00; - val = val >> 8; - val2 |= 0x40404040; - val2 |= val << 24 | val << 16 | val << 8 | val; - - /* rtm inc */ - regmap_read(combrxphy->regmap, REG(0x6604), &val); - val |= BIT(31); - regmap_write(combrxphy->regmap, REG(0x6604), val); - - regmap_write(combrxphy->regmap, REG(0x6620), val2); - - /* rtm en bypass */ - regmap_read(combrxphy->regmap, REG(0x6600), &val); - val |= BIT(7); - regmap_write(combrxphy->regmap, REG(0x6600), val); - - /* rtm prot en bypass */ - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0x80f000; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - regmap_read(combrxphy->regmap, REG(0x661c), &val); - val |= 0x81000000; - regmap_write(combrxphy->regmap, REG(0x661c), val); - - /* enable pll */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val &= ~BIT(4); - val |= BIT(3); - regmap_write(combrxphy->regmap, REG(0x6630), val); - - /* equ en */ - regmap_read(combrxphy->regmap, REG(0x6618), &val); - val |= BIT(4); - regmap_write(combrxphy->regmap, REG(0x6618), val); - - regmap_read(combrxphy->regmap, REG(0x6614), &val); - val |= 0x10900000; - regmap_write(combrxphy->regmap, REG(0x6614), val); - - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0xf00; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val |= 0x870000; - regmap_write(combrxphy->regmap, REG(0x6630), val); - - udelay(10); - - /* get cdr_mode,make sure cdr_mode != 5’h1f */ - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0x1f0000) == 0x1f0000) - dev_err(combrxphy->dev, "error,clock error!"); - - /* manually configure PLL */ - if (f <= 340000) { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500); - if (is_yuv420) - regmap_write(combrxphy->regmap, REG(0x66a8), - 0x0000c000); - else - regmap_write(combrxphy->regmap, REG(0x66a8), - 0x0000c600); - } else { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } - - switch (f) { - case 27000: - case 64000: - case 74250: - rd_offset = 0; - pll_man = 0x7964c; - break; - case 148500: - pll_man = 0x7a1c8; - rd_offset = 0; - break; - case 297000: - pll_man = 0x7a108; - rd_offset = 2; - break; - case 594000: - pll_man = 0x7f0c8; - rd_offset = 4; - break; - default: - pll_man = 0x7964c; - rd_offset = 1; - break; - } - - pll_man |= BIT(23); - regmap_write(combrxphy->regmap, REG(0x6630), pll_man); - - /* EQ and SAMPLE cfg */ - rk628_combrxphy_sample_edge_procedure(combrxphy, f, rd_offset); - - /* Deassert fifo reset,enable fifo write and read */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003); - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060); - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083); - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060); - regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24), - UPDATE(0x22, 31, 24)); - usleep_range(10*1000, 11*1000); - - /* check all 3 data channels alignment */ - count = 0; - for (i = 0; i < 100; i++) { - udelay(100); - regmap_read(combrxphy->regmap, REG(0x66b4), &data_a); - regmap_read(combrxphy->regmap, REG(0x66b8), &data_b); - /* ch0 ch1 ch2 lock */ - if (((data_a & 0x00ff00ff) == 0x00ff00ff) && - ((data_b & 0xff) == 0xff)) - count++; - } - - if (count >= 100) { - dev_info(combrxphy->dev, "channel alignment done"); - ret = 0; - } else if (count > 0) { - dev_err(combrxphy->dev, "not stable, count:%d of 100", count); - ret = -EINVAL; - } else { - dev_err(combrxphy->dev, "channel alignment failed!"); - ret = -EINVAL; - } - - return ret; -} - -static int rk628_combrxphy_power_on(struct phy *phy) -{ - struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy); - int f = phy_get_bus_width(phy); - int ret; - - /* Bit31 is used to distinguish HDMI cable mode and direct - * connection mode. - * Bit31: 0 -direct connection mode; - * 1 -cable mode; - */ - combrxphy->is_cable_mode = (f & BIT(31)) ? true : false; - dev_dbg(combrxphy->dev, "%s\n", __func__); - clk_prepare_enable(combrxphy->pclk); - reset_control_assert(combrxphy->rstc); - udelay(10); - reset_control_deassert(combrxphy->rstc); - udelay(10); - - if (combrxphy->is_cable_mode) { - f = f & 0x7fffffff; - ret = rk628_combrxphy_set_hdmi_mode_for_cable(combrxphy, f); - } else { - ret = rk628_combrxphy_set_hdmi_mode(combrxphy, f); - } - - return ret; -} - -static int rk628_combrxphy_power_off(struct phy *phy) -{ - struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy); - - dev_dbg(combrxphy->dev, "%s\n", __func__); - reset_control_assert(combrxphy->rstc); - udelay(10); - clk_disable_unprepare(combrxphy->pclk); - - return 0; -} - -static const struct phy_ops rk628_combrxphy_ops = { - .power_on = rk628_combrxphy_power_on, - .power_off = rk628_combrxphy_power_off, - .owner = THIS_MODULE, -}; - -static const struct regmap_range rk628_combrxphy_readable_ranges[] = { - regmap_reg_range(REG(0x6600), REG(0x665b)), - regmap_reg_range(REG(0x66a0), REG(0x66db)), - regmap_reg_range(REG(0x66f0), REG(0x66ff)), - regmap_reg_range(REG(0x6700), REG(0x6790)), -}; - -static const struct regmap_access_table rk628_combrxphy_readable_table = { - .yes_ranges = rk628_combrxphy_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges), -}; - -static const struct regmap_config rk628_combrxphy_regmap_cfg = { - .name = "combrxphy", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = COMBRXPHY_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_combrxphy_readable_table, -}; - -static int rk628_combrxphy_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct rk628_combrxphy *combrxphy; - struct phy_provider *phy_provider; - struct phy *phy; - int ret; - - if (!of_device_is_available(dev->of_node)) - return -ENODEV; - - combrxphy = devm_kzalloc(dev, sizeof(*combrxphy), GFP_KERNEL); - if (!combrxphy) - return -ENOMEM; - - combrxphy->dev = dev; - combrxphy->parent = rk628; - platform_set_drvdata(pdev, combrxphy); - - combrxphy->pclk = devm_clk_get(dev, "pclk"); - if (IS_ERR(combrxphy->pclk)) { - ret = PTR_ERR(combrxphy->pclk); - dev_err(dev, "failed to get pclk: %d\n", ret); - return ret; - } - - combrxphy->rstc = of_reset_control_get(dev->of_node, NULL); - if (IS_ERR(combrxphy->rstc)) { - ret = PTR_ERR(combrxphy->rstc); - dev_err(dev, "failed to get reset control: %d\n", ret); - return ret; - } - - combrxphy->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_combrxphy_regmap_cfg); - if (IS_ERR(combrxphy->regmap)) { - ret = PTR_ERR(combrxphy->regmap); - dev_err(dev, "failed to allocate host register map: %d\n", ret); - return ret; - } - - phy = devm_phy_create(dev, NULL, &rk628_combrxphy_ops); - if (IS_ERR(phy)) { - ret = PTR_ERR(phy); - dev_err(dev, "failed to create phy: %d\n", ret); - return ret; - } - - phy_set_drvdata(phy, combrxphy); - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) { - ret = PTR_ERR(phy_provider); - dev_err(dev, "failed to register phy provider: %d\n", ret); - return ret; - } - - return 0; -} - -static const struct of_device_id rk628_combrxphy_of_match[] = { - { .compatible = "rockchip,rk628-combrxphy", }, - {} -}; -MODULE_DEVICE_TABLE(of, rk628_combrxphy_of_match); - -static struct platform_driver rk628_combrxphy_driver = { - .driver = { - .name = "rk628-combrxphy", - .of_match_table = of_match_ptr(rk628_combrxphy_of_match), - }, - .probe = rk628_combrxphy_probe, -}; -module_platform_driver(rk628_combrxphy_driver); - -MODULE_AUTHOR("Algea Cao "); -MODULE_DESCRIPTION("Rockchip RK628 HDMI Combo RX PHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c deleted file mode 100644 index cbe7923139b7..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Wyon Bi - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk628_combtxphy.h" - -#define REG(x) ((x) + 0x90000) - -#define COMBTXPHY_CON0 REG(0x0000) -#define SW_TX_IDLE_MASK GENMASK(29, 20) -#define SW_TX_IDLE(x) UPDATE(x, 29, 20) -#define SW_TX_PD_MASK GENMASK(17, 8) -#define SW_TX_PD(x) UPDATE(x, 17, 8) -#define SW_BUS_WIDTH_MASK GENMASK(6, 5) -#define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5) -#define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5) -#define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5) -#define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5) -#define SW_PD_PLL_MASK BIT(4) -#define SW_PD_PLL BIT(4) -#define SW_GVI_LVDS_EN_MASK BIT(3) -#define SW_GVI_LVDS_EN BIT(3) -#define SW_MIPI_DSI_EN_MASK BIT(2) -#define SW_MIPI_DSI_EN BIT(2) -#define SW_MODULEB_EN_MASK BIT(1) -#define SW_MODULEB_EN BIT(1) -#define SW_MODULEA_EN_MASK BIT(0) -#define SW_MODULEA_EN BIT(0) -#define COMBTXPHY_CON1 REG(0x0004) -#define COMBTXPHY_CON2 REG(0x0008) -#define COMBTXPHY_CON3 REG(0x000c) -#define COMBTXPHY_CON4 REG(0x0010) -#define COMBTXPHY_CON5 REG(0x0014) -#define SW_RATE(x) UPDATE(x, 26, 24) -#define SW_REF_DIV(x) UPDATE(x, 20, 16) -#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10) -#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0) -#define COMBTXPHY_CON6 REG(0x0018) -#define COMBTXPHY_CON7 REG(0x001c) -#define SW_TX_RTERM_MASK GENMASK(22, 20) -#define SW_TX_RTERM(x) UPDATE(x, 22, 20) -#define SW_TX_MODE_MASK GENMASK(17, 16) -#define SW_TX_MODE(x) UPDATE(x, 17, 16) -#define SW_TX_CTL_CON5_MASK BIT(10) -#define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10) -#define SW_TX_CTL_CON4_MASK GENMASK(9, 8) -#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8) -#define BYPASS_095V_LDO_MASK BIT(3) -#define BYPASS_095V_LDO(x) UPDATE(x, 3, 3) -#define TX_COM_VOLT_ADJ_MASK GENMASK(2, 0) -#define TX_COM_VOLT_ADJ(x) UPDATE(x, 2, 0) -#define COMBTXPHY_CON8 REG(0x0020) -#define COMBTXPHY_CON9 REG(0x0024) -#define SW_DSI_FSET_EN_MASK BIT(29) -#define SW_DSI_FSET_EN BIT(29) -#define SW_DSI_RCAL_EN_MASK BIT(28) -#define SW_DSI_RCAL_EN BIT(28) -#define COMBTXPHY_CON10 REG(0x0028) -#define TX9_CKDRV_EN BIT(9) -#define TX8_CKDRV_EN BIT(8) -#define TX7_CKDRV_EN BIT(7) -#define TX6_CKDRV_EN BIT(6) -#define TX5_CKDRV_EN BIT(5) -#define TX4_CKDRV_EN BIT(4) -#define TX3_CKDRV_EN BIT(3) -#define TX2_CKDRV_EN BIT(2) -#define TX1_CKDRV_EN BIT(1) -#define TX0_CKDRV_EN BIT(0) -#define COMBTXPHY_MAX_REGISTER COMBTXPHY_CON10 - -struct rk628_combtxphy { - struct device *dev; - struct rk628 *parent; - struct regmap *grf; - struct regmap *regmap; - struct clk *pclk; - struct clk *ref_clk; - struct reset_control *rstc; - unsigned int flags; - - u16 frac_div; - u8 ref_div; - u8 fb_div; - u8 rate_div; - u8 division_mode; -}; - -static int rk628_combtxphy_dsi_power_on(struct rk628_combtxphy *combtxphy) -{ - u32 val; - int ret; - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK | - SW_MIPI_DSI_EN_MASK, - SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN); - - if (combtxphy->flags & COMBTXPHY_MODULEA_EN) - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_MODULEA_EN_MASK, SW_MODULEA_EN); - if (combtxphy->flags & COMBTXPHY_MODULEB_EN) - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_MODULEB_EN_MASK, SW_MODULEB_EN); - - regmap_write(combtxphy->regmap, COMBTXPHY_CON5, - SW_REF_DIV(combtxphy->ref_div - 1) | - SW_PLL_FB_DIV(combtxphy->fb_div) | - SW_PLL_FRAC_DIV(combtxphy->frac_div) | - SW_RATE(combtxphy->rate_div / 2)); - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_PD_PLL, 0); - - ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS, - val, val & DPHY_PHYLOCK, 0, 1000); - if (ret < 0) { - dev_err(combtxphy->dev, "phy is not lock\n"); - return ret; - } - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON9, - SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK, - SW_DSI_FSET_EN | SW_DSI_RCAL_EN); - - usleep_range(200, 400); - - return 0; -} - -static int rk628_combtxphy_lvds_power_on(struct rk628_combtxphy *combtxphy) -{ - u32 val; - int ret; - - /* Adjust terminal resistance 133 ohm, bypass 0.95v ldo for driver. */ - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON7, - SW_TX_RTERM_MASK | SW_TX_MODE_MASK | - BYPASS_095V_LDO_MASK | TX_COM_VOLT_ADJ_MASK, - SW_TX_RTERM(6) | SW_TX_MODE(3) | - BYPASS_095V_LDO(1) | TX_COM_VOLT_ADJ(0)); - - regmap_write(combtxphy->regmap, COMBTXPHY_CON10, - TX7_CKDRV_EN | TX2_CKDRV_EN); - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK | - SW_MIPI_DSI_EN_MASK, - SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN); - - if (combtxphy->flags & COMBTXPHY_MODULEA_EN) - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_MODULEA_EN_MASK, SW_MODULEA_EN); - if (combtxphy->flags & COMBTXPHY_MODULEB_EN) - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_MODULEB_EN_MASK, SW_MODULEB_EN); - - regmap_write(combtxphy->regmap, COMBTXPHY_CON5, - SW_REF_DIV(combtxphy->ref_div - 1) | - SW_PLL_FB_DIV(combtxphy->fb_div) | - SW_PLL_FRAC_DIV(combtxphy->frac_div) | - SW_RATE(combtxphy->rate_div / 2)); - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_PD_PLL, 0); - - ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS, - val, val & DPHY_PHYLOCK, 0, 1000); - if (ret < 0) { - dev_info(combtxphy->dev, "phy is not lock\n"); - return ret; - } - - usleep_range(100, 200); - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_TX_IDLE_MASK | SW_TX_PD_MASK, 0); - - return 0; -} - -static int rk628_combtxphy_gvi_power_on(struct rk628_combtxphy *combtxphy) -{ - int ref_div = 0; - - if (combtxphy->ref_div % 2) { - ref_div = combtxphy->ref_div - 1; - } else { - ref_div = BIT(4); - ref_div |= combtxphy->ref_div / 2 - 1; - } - regmap_write(combtxphy->regmap, COMBTXPHY_CON5, - SW_REF_DIV(ref_div) | - SW_PLL_FB_DIV(combtxphy->fb_div) | - SW_PLL_FRAC_DIV(combtxphy->frac_div) | - SW_RATE(combtxphy->rate_div / 2)); - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK | - SW_MIPI_DSI_EN_MASK | - SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK, - SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN | - SW_MODULEB_EN | SW_MODULEA_EN); - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_PD_PLL | SW_TX_PD_MASK, 0); - usleep_range(100, 200); - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_TX_IDLE_MASK, 0); - - return 0; -} - -int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode) -{ - struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy); - - combtxphy->division_mode = mode; - - return 0; -} -EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode); - -static int rk628_combtxphy_power_on(struct phy *phy) -{ - struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy); - enum phy_mode mode = phy_get_mode(phy); - - clk_prepare_enable(combtxphy->pclk); - reset_control_assert(combtxphy->rstc); - udelay(10); - reset_control_deassert(combtxphy->rstc); - udelay(10); - - regcache_mark_dirty(combtxphy->regmap); - regcache_sync(combtxphy->regmap); - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK, - SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL); - - switch (mode) { - case PHY_MODE_MIPI_DPHY: - regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON, - SW_TXPHY_REFCLK_SEL_MASK, - SW_TXPHY_REFCLK_SEL(0)); - return rk628_combtxphy_dsi_power_on(combtxphy); - case PHY_MODE_LVDS: - regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON, - SW_TXPHY_REFCLK_SEL_MASK, - SW_TXPHY_REFCLK_SEL(1)); - return rk628_combtxphy_lvds_power_on(combtxphy); - default: - regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON, - SW_TXPHY_REFCLK_SEL_MASK, - SW_TXPHY_REFCLK_SEL(2)); - return rk628_combtxphy_gvi_power_on(combtxphy); - } - - return 0; -} - -static int rk628_combtxphy_power_off(struct phy *phy) -{ - struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy); - - regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0, - SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK | - SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK, - SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL); - - clk_disable_unprepare(combtxphy->pclk); - - return 0; -} - -static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode, - int submode) -{ - struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy); - unsigned int bus_width = phy_get_bus_width(phy); - unsigned int frac_rate, fin = 24; - unsigned long fvco, fpfd; - - switch (mode) { - case PHY_MODE_MIPI_DPHY: - { - unsigned int fhsc = bus_width >> 8; - unsigned int flags = bus_width & 0xff; - - fhsc = fin * (fhsc / fin); - - if (fhsc < 80 || fhsc > 1500) - return -EINVAL; - else if (fhsc < 375) - combtxphy->rate_div = 4; - else if (fhsc < 750) - combtxphy->rate_div = 2; - else - combtxphy->rate_div = 1; - - combtxphy->flags = flags; - - fvco = fhsc * 2 * combtxphy->rate_div; - combtxphy->ref_div = 1; - combtxphy->fb_div = fvco / 8 / fin; - frac_rate = fvco - (fin * 8 * combtxphy->fb_div); - - if (frac_rate) { - frac_rate <<= 10; - frac_rate /= fin * 8; - combtxphy->frac_div = frac_rate; - } else { - combtxphy->frac_div = 0; - } - - fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div); - fvco *= 8; - fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div); - fhsc = fvco / 2 / combtxphy->rate_div; - phy_set_bus_width(phy, fhsc); - break; - } - case PHY_MODE_LVDS: - { - unsigned int flags = bus_width & 0xff; - unsigned int rate = (bus_width >> 8) * 7; - - combtxphy->flags = flags; - combtxphy->ref_div = 1; - combtxphy->fb_div = 14; - combtxphy->frac_div = 0; - - if (rate < 500) - combtxphy->rate_div = 4; - else if (rate < 1000) - combtxphy->rate_div = 2; - else - combtxphy->rate_div = 1; - break; - } - default: - { - unsigned int i, delta_freq, best_delta_freq, fb_div; - unsigned long ref_clk; - unsigned long long pre_clk; - - if (bus_width < 500000 || bus_width > 4000000) - return -EINVAL; - else if (bus_width < 1000000) - combtxphy->rate_div = 4; - else if (bus_width < 2000000) - combtxphy->rate_div = 2; - else - combtxphy->rate_div = 1; - fvco = bus_width * combtxphy->rate_div; - ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */ - if (combtxphy->division_mode) - ref_clk /= 2; - - if (!ref_clk) - return -EINVAL; - - /* - * the reference clock at PFD(FPFD = ref_clk / ref_div) about - * 25MHz is recommende, FPFD must range from 16MHz to 35MHz, - * here to find the best rev_div. - */ - best_delta_freq = ref_clk; - for (i = 1; i <= 32; i++) { - fpfd = ref_clk / i; - delta_freq = abs(fpfd - 25000); - if (delta_freq < best_delta_freq) { - best_delta_freq = delta_freq; - combtxphy->ref_div = i; - } - } - - /* - * ref_clk / ref_div * 8 * fb_div = FVCO - */ - pre_clk = (unsigned long long)fvco / 8 * combtxphy->ref_div * 1024; - do_div(pre_clk, ref_clk); - fb_div = pre_clk / 1024; - - /* - * get the actually frequence - */ - bus_width = ref_clk / combtxphy->ref_div * 8; - bus_width *= fb_div; - bus_width /= combtxphy->rate_div; - - combtxphy->frac_div = 0; - combtxphy->fb_div = fb_div; - - phy_set_bus_width(phy, bus_width); - break; - } - } - - return 0; -} - -static const struct phy_ops rk628_combtxphy_ops = { - .set_mode = rk628_combtxphy_set_mode, - .power_on = rk628_combtxphy_power_on, - .power_off = rk628_combtxphy_power_off, - .owner = THIS_MODULE, -}; - -static const struct regmap_range rk628_combtxphy_readable_ranges[] = { - regmap_reg_range(COMBTXPHY_CON0, COMBTXPHY_CON10), -}; - -static const struct regmap_access_table rk628_combtxphy_readable_table = { - .yes_ranges = rk628_combtxphy_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges), -}; - -static const struct regmap_config rk628_combtxphy_regmap_cfg = { - .name = "combtxphy", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .cache_type = REGCACHE_RBTREE, - .max_register = COMBTXPHY_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_combtxphy_readable_table, -}; - -static int rk628_combtxphy_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct rk628_combtxphy *combtxphy; - struct phy_provider *phy_provider; - struct phy *phy; - int ret; - - combtxphy = devm_kzalloc(dev, sizeof(*combtxphy), GFP_KERNEL); - if (!combtxphy) - return -ENOMEM; - - combtxphy->dev = dev; - combtxphy->parent = rk628; - combtxphy->grf = rk628->grf; - platform_set_drvdata(pdev, combtxphy); - - combtxphy->pclk = devm_clk_get(dev, "pclk"); - if (IS_ERR(combtxphy->pclk)) - return PTR_ERR(combtxphy->pclk); - - combtxphy->ref_clk = devm_clk_get(dev, "ref_clk"); - if (IS_ERR(combtxphy->ref_clk)) { - dev_err(dev, "fail to get ref clk\n"); - return PTR_ERR(combtxphy->ref_clk); - } - - combtxphy->rstc = of_reset_control_get(dev->of_node, NULL); - if (IS_ERR(combtxphy->rstc)) { - ret = PTR_ERR(combtxphy->rstc); - dev_err(dev, "failed to get reset control: %d\n", ret); - return ret; - } - - combtxphy->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_combtxphy_regmap_cfg); - if (IS_ERR(combtxphy->regmap)) { - ret = PTR_ERR(combtxphy->regmap); - dev_err(dev, "failed to allocate register map: %d\n", ret); - return ret; - } - - phy = devm_phy_create(dev, NULL, &rk628_combtxphy_ops); - if (IS_ERR(phy)) { - ret = PTR_ERR(phy); - dev_err(dev, "failed to create phy: %d\n", ret); - return ret; - } - - phy_set_drvdata(phy, combtxphy); - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) { - ret = PTR_ERR(phy_provider); - dev_err(dev, "failed to register phy provider: %d\n", ret); - return ret; - } - - return 0; -} - -static const struct of_device_id rk628_combtxphy_of_match[] = { - { .compatible = "rockchip,rk628-combtxphy", }, - {} -}; -MODULE_DEVICE_TABLE(of, rk628_combtxphy_of_match); - -static struct platform_driver rk628_combtxphy_driver = { - .driver = { - .name = "rk628-combtxphy", - .of_match_table = of_match_ptr(rk628_combtxphy_of_match), - }, - .probe = rk628_combtxphy_probe, -}; -module_platform_driver(rk628_combtxphy_driver); - -MODULE_AUTHOR("Wyon Bi "); -MODULE_DESCRIPTION("Rockchip RK628 GVI/LVDS/MIPI Combo TX PHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h deleted file mode 100644 index 40d785eecd67..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - */ - -#ifndef RK628_COMBTXPHY_H_ -#define RK628_COMBTXPHY_H_ - -#include - -int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode); - -#endif diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c b/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c deleted file mode 100644 index 766f156efb98..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c +++ /dev/null @@ -1,1395 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Wyon Bi - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include