From f6739bf8ea58c30860eb427bba1e7a3f749aebf3 Mon Sep 17 00:00:00 2001 From: Qiufang Dai Date: Fri, 11 May 2018 17:31:59 +0800 Subject: [PATCH] clk: add g12b.c for g12b new clocks PD#165090: add g12b.c for new clocks, include sys1_pll Change-Id: If9234037eab5439cf1abfbcecc70c9f4eab6c954 Signed-off-by: Qiufang Dai Signed-off-by: Hong Guo --- .../bindings/clock/amlogic,meson-clkc.txt | 3 + MAINTAINERS | 5 + .../arm64/boot/dts/amlogic/g12b_a311d_skt.dts | 52 ++- arch/arm64/boot/dts/amlogic/mesong12b.dtsi | 11 +- drivers/amlogic/clk/Makefile | 1 + drivers/amlogic/clk/g12a/g12a.c | 159 +------- drivers/amlogic/clk/g12a/g12a.h | 7 +- drivers/amlogic/clk/g12a/g12a_ao.c | 1 + drivers/amlogic/clk/g12b/Makefile | 5 + drivers/amlogic/clk/g12b/g12b.c | 345 ++++++++++++++++++ include/dt-bindings/clock/amlogic,g12a-clkc.h | 6 +- 11 files changed, 431 insertions(+), 164 deletions(-) create mode 100644 drivers/amlogic/clk/g12b/Makefile create mode 100644 drivers/amlogic/clk/g12b/g12b.c diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt index c974ab005c78..a65f692d7821 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt @@ -14,6 +14,9 @@ Required Properties: "amlogic,txlx-aoclkc" - for txlx ao clock "amlogic,g12a-clkc" - for g12a ee clock "amlogic,g12a-aoclkc" - for g12a ao clock + "amlogic,g12b-clkc-1" - for g12b ee part1 clock + "amlogic,g12b-clkc-2" - for g12b ee part2 clock + "amlogic,g12b-aoclkc" - for g12b ao clock - reg: physical base address of the clock controller and length of memory mapped region. diff --git a/MAINTAINERS b/MAINTAINERS index 341483acef45..79178dcd8ab8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14491,3 +14491,8 @@ F: arch/arm64/boot/dts/amlogic/g12b-sched-energy.dtsi AMLOGIC G12B skt dts M: Qiufang Dai F: arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts + +AMLOGIC G12B clock +M: Qiufang Dai +F: drivers/amlogic/clk/g12b/* + diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts index 5ef8978a4f06..63e148362a70 100644 --- a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts @@ -387,11 +387,61 @@ }; }; + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + opp10 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <981000>; + }; + }; + cpufreq-meson { compatible = "amlogic, cpufreq-meson"; pinctrl-names = "default"; pinctrl-0 = <&pwm_ao_d_pins3>; - status = "okay"; + status = "disable"; }; diff --git a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi index a487166826fa..c9b3468b22fe 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi @@ -697,7 +697,7 @@ }; aoclkc: clock-controller@0 { - compatible = "amlogic,g12a-aoclkc"; + compatible = "amlogic,g12b-aoclkc"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0x320>; }; @@ -796,9 +796,14 @@ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; clkc: clock-controller@0 { - compatible = "amlogic,g12a-clkc"; + compatible = "amlogic,g12b-clkc-1"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x320>; + reg = <0x0 0x0 0x0 0x3dc>; + }; + clkc_b: clock-controller@1 { + compatible = "amlogic,g12b-clkc-2"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3dc>; }; };/* end of hiubus*/ diff --git a/drivers/amlogic/clk/Makefile b/drivers/amlogic/clk/Makefile index 28a1fd9eeca7..6af6c252595a 100644 --- a/drivers/amlogic/clk/Makefile +++ b/drivers/amlogic/clk/Makefile @@ -15,5 +15,6 @@ obj-$(CONFIG_AMLOGIC_GX_CLK) += gxl/ obj-$(CONFIG_AMLOGIC_GX_CLK) += axg/ obj-$(CONFIG_AMLOGIC_GX_CLK) += txlx/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a/ +obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b/ obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/ diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c index 86a4a40f4796..ebf7c4a653dd 100644 --- a/drivers/amlogic/clk/g12a/g12a.c +++ b/drivers/amlogic/clk/g12a/g12a.c @@ -103,34 +103,6 @@ static struct meson_clk_pll g12a_sys_pll = { }, }; -static struct meson_clk_pll g12b_sys1_pll = { - .m = { - .reg_off = HHI_SYS1_PLL_CNTL0, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_SYS1_PLL_CNTL0, - .shift = 10, - .width = 5, - }, - .od = { - .reg_off = HHI_SYS1_PLL_CNTL0, - .shift = 16, - .width = 3, - }, - .rate_table = g12a_pll_rate_table, - .rate_count = ARRAY_SIZE(g12a_pll_rate_table), - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "sys1_pll", - .ops = &meson_g12a_pll_ops, - .parent_names = (const char *[]){ "xtal" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - static struct meson_clk_pll g12a_gp0_pll = { .m = { .reg_off = HHI_GP0_PLL_CNTL0, @@ -462,123 +434,7 @@ static struct clk_gate g12a_mipi_bandgap_gate = { }, }; #endif -/* - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL - * post-dividers and should be modelled with their respective PLLs via the - * forthcoming coordinated clock rates feature - */ - #if 0 -static u32 mux_table_cpu_px0[] = { 0, 1, 2 }; -static u32 mux_table_cpu_px[] = { 0, 1 }; -static struct clk_mux g12a_cpu_fixedpll_p00 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x3, - .shift = 0, - .table = mux_table_cpu_px0, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p00", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "xtal", "fclk_div2", - "fclk_div3"}, - .num_parents = 3, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_divider g12a_cpu_fixedpll_p01 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .shift = 4, - .width = 6, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p01", - .ops = &clk_divider_ops, - .parent_names = (const char *[]){ "cpu_fixedpll_p00" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_mux g12a_cpu_fixedpll_p0 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x1, - .shift = 2, - .table = mux_table_cpu_px, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p0", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "cpu_fixedpll_p00", - "cpu_fixedpll_p01"}, - .num_parents = 2, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), - }, -}; - -static struct clk_mux g12a_cpu_fixedpll_p10 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x3, - .shift = 16, - .table = mux_table_cpu_px0, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p10", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "xtal", "fclk_div2", - "fclk_div3"}, - .num_parents = 3, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_divider g12a_cpu_fixedpll_p11 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .shift = 20, - .width = 6, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p11", - .ops = &clk_divider_ops, - .parent_names = (const char *[]){ "cpu_fixedpll_p10" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_mux g12a_cpu_fixedpll_p1 = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x1, - .shift = 18, - .table = mux_table_cpu_px, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p1", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "cpu_fixedpll_p10", - "cpu_fixedpll_p11"}, - .num_parents = 2, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), - }, -}; - -static struct clk_mux g12a_cpu_fixedpll_p = { - .reg = (void *)HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x1, - .shift = 10, - .table = mux_table_cpu_px, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "cpu_fixedpll_p", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "cpu_fixedpll_p0", - "cpu_fixedpll_p1"}, - .num_parents = 2, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; -#endif static u32 mux_table_cpu_p[] = { 0, 1, 2 }; static u32 mux_table_cpu_px[] = { 0, 1 }; static struct meson_cpu_mux_divider g12a_cpu_fclk_p = { @@ -647,6 +503,7 @@ static struct meson_clk_cpu g12a_cpu_clk = { }, }; + static u32 mux_table_clk81[] = { 6, 5, 7 }; static struct clk_mux g12a_mpeg_clk_sel = { @@ -780,7 +637,6 @@ static MESON_GATE(g12a_ao_i2c, HHI_GCLK_AO, 4); static struct clk_hw *g12a_clk_hws[] = { [CLKID_SYS_PLL] = &g12a_sys_pll.hw, - [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw, [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, @@ -890,7 +746,6 @@ static struct clk_hw *g12a_clk_hws[] = { static struct meson_clk_pll *const g12a_clk_plls[] = { &g12a_fixed_pll, &g12a_sys_pll, - &g12b_sys1_pll, &g12a_gp0_pll, &g12a_hifi_pll, &g12a_pcie_pll, @@ -987,10 +842,11 @@ static void __init g12a_clkc_init(struct device_node *np) struct clk *parent_clk; /* Generic clocks and PLLs */ - clk_base = of_iomap(np, 0); + if (!clk_base) + clk_base = of_iomap(np, 0); + if (!clk_base) { pr_err("%s: Unable to map clk base\n", __func__); - /* return -ENXIO; */ return; } /* pr_debug("%s: iomap clk_base ok!", __func__); */ @@ -1033,11 +889,6 @@ static void __init g12a_clkc_init(struct device_node *np) } } - if (clks == NULL) { - pr_err("%s: error: not kzalloc clks in aoclk!", __func__); - return; - } - clk_data.clks = clks; clk_data.clk_num = NR_CLKS; /* @@ -1100,5 +951,5 @@ iounmap: } CLK_OF_DECLARE(g12a, "amlogic,g12a-clkc", g12a_clkc_init); - +CLK_OF_DECLARE(g12b, "amlogic,g12b-clkc-1", g12a_clkc_init); diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h index 2e4fa81a679e..9cc75b595eaa 100644 --- a/drivers/amlogic/clk/g12a/g12a.h +++ b/drivers/amlogic/clk/g12a/g12a.h @@ -44,12 +44,8 @@ #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ -#if 0 -#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ +#define HHI_APICALGDC_CNTL 0x168 /* 0x5a offset in data sheet */ -#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ -#define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in data sheet */ -#endif #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ @@ -70,6 +66,7 @@ #define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ #define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ +#define HHI_SYS_CPUB_CLK_CNTL 0x208 /* 0x82 offset in data sheet */ #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ diff --git a/drivers/amlogic/clk/g12a/g12a_ao.c b/drivers/amlogic/clk/g12a/g12a_ao.c index 594aaf0ced41..ccba986d7950 100644 --- a/drivers/amlogic/clk/g12a/g12a_ao.c +++ b/drivers/amlogic/clk/g12a/g12a_ao.c @@ -140,5 +140,6 @@ static void __init g12a_aoclkc_init(struct device_node *np) } CLK_OF_DECLARE(g12a, "amlogic,g12a-aoclkc", g12a_aoclkc_init); +CLK_OF_DECLARE(g12b, "amlogic,g12b-aoclkc", g12a_aoclkc_init); diff --git a/drivers/amlogic/clk/g12b/Makefile b/drivers/amlogic/clk/g12b/Makefile new file mode 100644 index 000000000000..19a8a161ce24 --- /dev/null +++ b/drivers/amlogic/clk/g12b/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Meson G12A clk +# + +obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b.o diff --git a/drivers/amlogic/clk/g12b/g12b.c b/drivers/amlogic/clk/g12b/g12b.c new file mode 100644 index 000000000000..e2e6840c12ad --- /dev/null +++ b/drivers/amlogic/clk/g12b/g12b.c @@ -0,0 +1,345 @@ +/* + * drivers/amlogic/clk/g12b/g12b.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "../g12a/g12a.h" + +static struct meson_clk_pll g12b_sys1_pll = { + .m = { + .reg_off = HHI_SYS1_PLL_CNTL0, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_SYS1_PLL_CNTL0, + .shift = 10, + .width = 5, + }, + .od = { + .reg_off = HHI_SYS1_PLL_CNTL0, + .shift = 16, + .width = 3, + }, + .rate_table = g12a_pll_rate_table, + .rate_count = ARRAY_SIZE(g12a_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "sys1_pll", + .ops = &meson_g12a_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static u32 mux_table_cpu_p[] = { 0, 1, 2 }; +static u32 mux_table_cpu_px[] = { 0, 1 }; + +static struct meson_cpu_mux_divider g12b_cpu_fclk_p = { + .reg = (void *)HHI_SYS_CPUB_CLK_CNTL, + .cpu_fclk_p00 = { + .mask = 0x3, + .shift = 0, + .width = 2, + }, + .cpu_fclk_p0 = { + .mask = 0x1, + .shift = 2, + .width = 1, + }, + .cpu_fclk_p10 = { + .mask = 0x3, + .shift = 16, + .width = 2, + }, + .cpu_fclk_p1 = { + .mask = 0x1, + .shift = 18, + .width = 1, + }, + .cpu_fclk_p = { + .mask = 0x1, + .shift = 10, + .width = 1, + }, + .cpu_fclk_p01 = { + .shift = 4, + .width = 6, + }, + .cpu_fclk_p11 = { + .shift = 20, + .width = 6, + }, + .table = mux_table_cpu_p, + .rate_table = fclk_pll_rate_table, + .rate_count = ARRAY_SIZE(fclk_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cpub_fixedpll_p", + .ops = &meson_fclk_cpu_ops, + .parent_names = (const char *[]){ "xtal", "fclk_div2", + "fclk_div3"}, + .num_parents = 3, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct meson_clk_cpu g12b_cpu_clk = { + .reg_off = HHI_SYS_CPUB_CLK_CNTL, + .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, + .mux.reg = (void *)HHI_SYS_CPUB_CLK_CNTL, + .mux.shift = 11, + .mux.mask = 0x1, + .mux.lock = &clk_lock, + .mux.table = mux_table_cpu_px, + .mux.hw.init = &(struct clk_init_data){ + .name = "cpub_clk", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "cpub_fixedpll_p", + "sys1_pll"}, + .num_parents = 2, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static const char * const gdc_parent_names[] = { "xtal", + "gp0_pll", "hifi_pll", "fclk_div2p5", "fclk_div3", "fclk_div4", + "fclk_div5", "fclk_div7"}; + +static struct clk_mux cts_gdc_core_clk_mux = { + .reg = (void *)HHI_APICALGDC_CNTL, + .mask = 0x7, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cts_gdc_core_clk_mux", + .ops = &clk_mux_ops, + .parent_names = gdc_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider cts_gdc_core_clk_div = { + .reg = (void *)HHI_APICALGDC_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cts_gdc_core_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "cts_gdc_core_clk_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate cts_gdc_core_clk_gate = { + .reg = (void *)HHI_APICALGDC_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "cts_gdc_core_clk_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "cts_gdc_core_clk_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux cts_gdc_axi_clk_mux = { + .reg = (void *)HHI_APICALGDC_CNTL, + .mask = 0x7, + .shift = 25, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cts_gdc_axi_clk_mux", + .ops = &clk_mux_ops, + .parent_names = gdc_parent_names, + .num_parents = 8, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_divider cts_gdc_axi_clk_div = { + .reg = (void *)HHI_APICALGDC_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "cts_gdc_axi_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "cts_gdc_axi_clk_mux" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_gate cts_gdc_axi_clk_gate = { + .reg = (void *)HHI_APICALGDC_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "cts_gdc_axi_clk_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "cts_gdc_axi_clk_div" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_hw *g12b_clk_hws[] = { + [CLKID_SYS1_PLL - CLKID_G12B_ADD_BASE] = &g12b_sys1_pll.hw, + [CLKID_CPUB_FCLK_P - CLKID_G12B_ADD_BASE] = &g12b_cpu_fclk_p.hw, + [CLKID_CPUB_CLK - CLKID_G12B_ADD_BASE] = &g12b_cpu_clk.mux.hw, +}; + +static struct meson_clk_pll *const g12b_clk_plls[] = { + &g12b_sys1_pll, +}; +#if 0 +static struct clk_gate *g12b_clk_gates[] = { +}; +#endif +static void __init g12b_clkc_init(struct device_node *np) +{ + int ret = 0, clkid, i; + struct clk_hw *parent_hw; + struct clk *parent_clk; + + /* Generic clocks and PLLs */ + if (!clk_base) + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%s: Unable to map clk base\n", __func__); + /* return -ENXIO; */ + return; + } + + g12b_cpu_clk.base = clk_base; + g12b_cpu_fclk_p.reg = clk_base + (u64)g12b_cpu_fclk_p.reg; + g12b_cpu_clk.mux.reg = clk_base + (u64)g12b_cpu_clk.mux.reg; + + cts_gdc_core_clk_mux.reg = clk_base + (u64)(cts_gdc_core_clk_mux.reg); + cts_gdc_core_clk_gate.reg = clk_base + (u64)(cts_gdc_core_clk_gate.reg); + cts_gdc_core_clk_div.reg = clk_base + (u64)(cts_gdc_core_clk_div.reg); + + cts_gdc_axi_clk_mux.reg = clk_base + (u64)(cts_gdc_axi_clk_mux.reg); + cts_gdc_axi_clk_gate.reg = clk_base + (u64)(cts_gdc_axi_clk_gate.reg); + cts_gdc_axi_clk_div.reg = clk_base + (u64)(cts_gdc_axi_clk_div.reg); +#if 0 + /* Populate base address for gates */ + for (i = 0; i < ARRAY_SIZE(g12b_clk_gates); i++) + g12b_clk_gates[i]->reg = clk_base + + (u64)g12b_clk_gates[i]->reg; +#endif + /* Populate base address for PLLs */ + for (i = 0; i < ARRAY_SIZE(g12b_clk_plls); i++) + g12b_clk_plls[i]->base = clk_base; + + if (!clks) { + clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL); + if (!clks) { + pr_err("%s: alloc clks fail!", __func__); + return; + } + } + + /* + * register all clks + */ + for (clkid = 0; clkid < ARRAY_SIZE(g12b_clk_hws); clkid++) { + if (g12b_clk_hws[clkid]) { + clks[clkid + CLKID_G12B_ADD_BASE] + = clk_register(NULL, g12b_clk_hws[clkid]); + if (IS_ERR(clks[clkid + CLKID_G12B_ADD_BASE])) { + pr_err("%s: failed to register %s\n", __func__, + clk_hw_get_name(g12b_clk_hws[clkid])); + goto iounmap; + } + } + } + + clks[CLKID_GDC_CORE_CLK_COMP] = clk_register_composite(NULL, + "cts_gdc_core_clk_composite", + gdc_parent_names, 8, + &cts_gdc_core_clk_mux.hw, + &clk_mux_ops, + &cts_gdc_core_clk_div.hw, + &clk_divider_ops, + &cts_gdc_core_clk_gate.hw, + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_GDC_CORE_CLK_COMP])) + panic("%s: %d register cts_gdc_core_clk_composite error\n", + __func__, __LINE__); + + clks[CLKID_GDC_AXI_CLK_COMP] = clk_register_composite(NULL, + "cts_gdc_axi_clk_composite", + gdc_parent_names, 8, + &cts_gdc_axi_clk_mux.hw, + &clk_mux_ops, + &cts_gdc_axi_clk_div.hw, + &clk_divider_ops, + &cts_gdc_axi_clk_gate.hw, + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_GDC_AXI_CLK_COMP])) + panic("%s: %d register cts_gdc_axi_clk_composite error\n", + __func__, __LINE__); + + pr_debug("%s: register all clk ok!", __func__); + /* + * Register CPU clk notifier + * + * FIXME this is wrong for a lot of reasons. First, the muxes should be + * struct clk_hw objects. Second, we shouldn't program the muxes in + * notifier handlers. The tricky programming sequence will be handled + * by the forthcoming coordinated clock rates mechanism once that + * feature is released. + * + * Furthermore, looking up the parent this way is terrible. At some + * point we will stop allocating a default struct clk when registering + * a new clk_hw, and this hack will no longer work. Releasing the ccr + * feature before that time solves the problem :-) + */ + parent_hw = clk_hw_get_parent(&g12b_cpu_clk.mux.hw); + parent_clk = parent_hw->clk; + ret = clk_notifier_register(parent_clk, &g12b_cpu_clk.clk_nb); + if (ret) { + pr_err("%s: failed to register clock notifier for cpu_clk\n", + __func__); + goto iounmap; + } + pr_debug("%s: cpu clk register notifier ok!", __func__); + return; + +iounmap: + iounmap(clk_base); + pr_info("%s: %d: ret: %d\n", __func__, __LINE__, ret); + /* return; */ +} + +CLK_OF_DECLARE(g12b, "amlogic,g12b-clkc-2", g12b_clkc_init); + + diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h index 1440a3b10ef7..97bce55b6017 100644 --- a/include/dt-bindings/clock/amlogic,g12a-clkc.h +++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h @@ -260,8 +260,12 @@ /*G12B clk*/ #define CLKID_G12B_ADD_BASE (CLKID_MISC_BASE + 9) #define CLKID_SYS1_PLL (CLKID_G12B_ADD_BASE + 0) +#define CLKID_CPUB_FCLK_P (CLKID_G12B_ADD_BASE + 1) +#define CLKID_CPUB_CLK (CLKID_G12B_ADD_BASE + 2) +#define CLKID_GDC_CORE_CLK_COMP (CLKID_G12B_ADD_BASE + 3) +#define CLKID_GDC_AXI_CLK_COMP (CLKID_G12B_ADD_BASE + 4) -#define CLKID_AO_BASE (CLKID_G12B_ADD_BASE + 1) +#define CLKID_AO_BASE (CLKID_G12B_ADD_BASE + 5) #define CLKID_AO_CLK81 (CLKID_AO_BASE + 0) #define CLKID_SARADC_MUX (CLKID_AO_BASE + 1) #define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)