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media: rockchip: fix ispp scl isr at power on

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Change-Id: I4b02c29eb2f0b08c134be2efe91c4ea9ed9c532a
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2020-04-18 10:21:45 +08:00
committed by Tao Huang
parent eb3ea2ff89
commit f6ae766bfe
5 changed files with 36 additions and 14 deletions
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3
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -423,6 +423,9 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
writel(0x7FFFFF7F, dev->base_addr + CSI2RX_MASK_STAT);
}
if (IS_HDR_RDBK(dev->hdr.op_mode))
isp_set_bits(dev->base_addr + CTRL_SWS_CFG,
0, SW_MPIP_DROP_FRM_DIS);
dev->csi_dev.is_first = true;
kfifo_reset(&dev->csi_dev.rdbk_kfifo);
return ret;

3
drivers/media/platform/rockchip/isp/mpfbc.c
View File

@@ -266,8 +266,7 @@ static int mpfbc_stop(struct rkisp_mpfbc_device *mpfbc_dev)
int ret;
mpfbc_dev->stopping = true;
writel(SW_MPFBC_YUV_MODE(1),
base + ISP_MPFBC_BASE);
isp_clear_bits(base + ISP_MPFBC_BASE, SW_MPFBC_EN);
hdr_stop_dmatx(dev);
ret = wait_event_timeout(mpfbc_dev->done,
!mpfbc_dev->en,

16
drivers/media/platform/rockchip/ispp/ispp.c
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/iommu.h>
#include <linux/pm_runtime.h>
@@ -323,6 +324,7 @@ static int rkispp_sd_s_power(struct v4l2_subdev *sd, int on)
{
struct rkispp_subdev *ispp_sdev = v4l2_get_subdevdata(sd);
struct rkispp_device *ispp_dev = ispp_sdev->dev;
void __iomem *base = ispp_dev->base_addr;
struct iommu_domain *domain;
int ret;
@@ -338,10 +340,16 @@ static int rkispp_sd_s_power(struct v4l2_subdev *sd, int on)
return ret;
}
atomic_set(&ispp_sdev->frm_sync_seq, 0);
writel(0xfffffff, ispp_dev->base_addr + RKISPP_CTRL_INT_MSK);
writel(SW_SHP_DMA_DIS,
ispp_dev->base_addr + RKISPP_SHARP_CORE_CTRL);
writel(GATE_DIS_NR, ispp_dev->base_addr + RKISPP_CTRL_CLKGATE);
writel(SW_SCL_BYPASS, base + RKISPP_SCL0_CTRL);
writel(SW_SCL_BYPASS, base + RKISPP_SCL1_CTRL);
writel(SW_SCL_BYPASS, base + RKISPP_SCL2_CTRL);
writel(OTHER_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
writel(SW_SHP_DMA_DIS, base + RKISPP_SHARP_CORE_CTRL);
writel(SW_FEC2DDR_DIS, base + RKISPP_FEC_CORE_CTRL);
writel(0xfffffff, base + RKISPP_CTRL_INT_MSK);
writel(GATE_DIS_ALL, base + RKISPP_CTRL_CLKGATE);
//usleep_range(1000, 1200);
//writel(0, base + RKISPP_CTRL_CLKGATE);
if (ispp_dev->inp == INP_ISP) {
struct v4l2_subdev_format fmt;
struct v4l2_subdev_selection sel;

16
drivers/media/platform/rockchip/ispp/regs.h
View File

@@ -19,6 +19,7 @@
#define RKISPP_CTRL_INT_STA (RKISPP_CTRL + 0x0028)
#define RKISPP_CTRL_INT_SET (RKISPP_CTRL + 0x002C)
#define RKISPP_CTRL_INT_CLR (RKISPP_CTRL + 0x0030)
#define RKISPP_QUICK_DIF (RKISPP_CTRL + 0x0034)
#define RKISPP_CTRL_SYS_STATUS (RKISPP_CTRL + 0x003C)
#define RKISPP_CTRL_QUICK_FRM_NUM (RKISPP_CTRL + 0x0040)
#define RKISPP_CTRL_SYS_CTL_STA0 (RKISPP_CTRL + 0x0054)
@@ -338,9 +339,16 @@
/* ISPP_CTRL_QUICK */
#define GLB_QUICK_MODE_MASK GENMASK(9, 8)
#define SW_PP_FBC_MODE_DIS BIT(30)
#define SW_PP_MMU_PLUS_DIS BIT(29)
#define SW_PP2ISP_HOLD_SEL BIT(28)
#define GLB_FEC2SCL_EN BIT(11)
#define GLB_NR_SD32_TNR BIT(10)
#define GLB_QUICK_MODE(a) (((a) & 0x3) << 8)
#define GLB_NOC_HURRY(a) (((a) & 0x3) << 4)
#define GLB_TNR_RDY_DIS BIT(3)
#define GLB_TNR2NR_RDY_MODE BIT(2)
#define GLB_DIRECT_MODE BIT(1)
#define GLB_QUICK_EN BIT(0)
/* ISPP_CTRL_RESET */
@@ -353,10 +361,11 @@
#define GLB_SOFT_RST_ALL BIT(0)
/* ISPP_CLKGATE */
#define GATE_DIS_ALL 0xff
#define GATE_DIS_GLOBAL_RAM_CLK BIT(7)
#define GATE_DIS_SWS BIT(6)
#define GATE_DIS_FEC BIT(5)
#define GATE_DIS_SCL BTI(4)
#define GATE_DIS_SCL BIT(4)
#define GATE_DIS_SHP BIT(3)
#define GATE_DIS_NR BIT(2)
#define GATE_DIS_TNR BIT(1)
@@ -387,6 +396,11 @@
#define FRAME_INT BIT(1)
#define QUICK_INT BIT(0)
/* ISPP_QUICK_DIF */
#define GLB_TNR2NR_DIF(a) (((a) & 0xff) << 16)
#define GLB_ISP2NR_DIF(a) (((a) & 0xff) << 8)
#define GLB_NR2FEC_DIF(a) ((a) & 0xff)
/* TNR CTRL */
#define SW_TNR_WR_FORMAT_MASK GENMASK(7, 4)
#define SW_TNR_RD_FORMAT_MASK GENMASK(3, 0)

12
drivers/media/platform/rockchip/ispp/stream.c
View File

@@ -868,6 +868,7 @@ static int config_mb(struct rkispp_stream *stream)
limit_range | stream->out_cap_fmt.wr_fmt << 4);
writel((stream->out_fmt.height << 16) | stream->out_fmt.width,
base + RKISPP_FEC_PIC_SIZE);
rkispp_clear_bits(base + RKISPP_FEC_CORE_CTRL, SW_FEC2DDR_DIS);
}
if (stream->out_cap_fmt.wr_fmt & FMT_YUYV)
mult = 2;
@@ -1190,16 +1191,13 @@ static void rkispp_stream_stop(struct rkispp_stream *stream)
wait = true;
}
if (dev->inp == INP_ISP &&
atomic_read(&dev->stream_vdev.refcnt) == 1) {
atomic_read(&dev->stream_vdev.refcnt) == 1)
v4l2_subdev_call(&dev->ispp_sdev.sd,
video, s_stream, false);
rkispp_clear_bits(dev->base_addr + RKISPP_CTRL_QUICK,
GLB_QUICK_EN);
}
if (wait) {
ret = wait_event_timeout(stream->done,
!stream->streaming,
msecs_to_jiffies(100));
msecs_to_jiffies(1000));
if (!ret)
v4l2_warn(&dev->v4l2_dev,
"waiting on event ret:%d\n", ret);
@@ -1269,8 +1267,6 @@ static int start_isp(struct rkispp_device *dev)
ret = config_modules(dev);
if (ret)
return ret;
rkispp_set_bits(dev->base_addr + RKISPP_CTRL_QUICK,
0, GLB_QUICK_EN);
writel(ALL_FORCE_UPD, dev->base_addr + RKISPP_CTRL_UPDATE);
if (vdev->is_update_manual)
i = (vdev->module_ens & ISPP_MODULE_FEC) ?
@@ -1281,6 +1277,8 @@ static int start_isp(struct rkispp_device *dev)
stream = &vdev->stream[i];
rkispp_frame_end(stream);
}
rkispp_set_bits(dev->base_addr + RKISPP_CTRL_QUICK,
0, GLB_QUICK_EN);
return v4l2_subdev_call(&dev->ispp_sdev.sd,
video, s_stream, true);
}