From f6b6c4c402e99de5e9deb89343b5b963405f6ca2 Mon Sep 17 00:00:00 2001
From: Zhenke Fan <fanzy.fan@rock-chips.com>
Date: Thu, 25 Jun 2020 14:35:00 +0800
Subject: [PATCH] media: i2c: gc4c33: modify dpcc to adjust single and multiple
 bad point

Signed-off-by: Zhenke Fan <fanzy.fan@rock-chips.com>
Change-Id: Iaf12ded3604ec26e9b61833e1fd4004e03acb110
---
 drivers/media/i2c/gc4c33.c            | 36 ++++++++++++++++++++-------
 include/uapi/linux/rk-camera-module.h | 11 +++++++-
 2 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/drivers/media/i2c/gc4c33.c b/drivers/media/i2c/gc4c33.c
index 546a551fdd11..51bce5117207 100644
--- a/drivers/media/i2c/gc4c33.c
+++ b/drivers/media/i2c/gc4c33.c
@@ -88,6 +88,8 @@
 #define OF_CAMERA_HDR_MODE		"rockchip,camera-hdr-mode"
 #define GC4C33_NAME			"gc4c33"
 
+#define GC4C33_ENABLE_DPCC
+#define GC4C33_ENABLE_OTP
 //#define GC4C33_ENABLE_HIGHLIGHT
 
 static const char * const gc4c33_supply_names[] = {
@@ -507,7 +509,6 @@ static const struct regval gc4c33_linear10bit_2560x1440_regs[] = {
 	{0x00c8, 0x15},
 	{0x00df, 0x0a},
 	{0x00de, 0xfe},
-	{0x00aa, 0x3a},
 	{0x00c0, 0x0a},
 	{0x031c, 0x80},
 	{0x031f, 0x10},
@@ -560,10 +561,6 @@ static const struct regval gc4c33_linear10bit_2560x1440_regs[] = {
 	{0x00e9, 0x00},
 	{0x00ea, 0xf0},
 	{0x00ef, 0x04},
-	{0x00a1, 0x05},
-	{0x00a2, 0x05},
-	{0x00a7, 0x00},
-	{0x00a8, 0x20},
 	{0x00a9, 0x20},
 	{0x00b3, 0x00},
 	{0x00b4, 0x10},
@@ -585,7 +582,7 @@ static const struct regval gc4c33_linear10bit_2560x1440_regs[] = {
 	{0x0115, 0x12},
 	{0x0103, 0x00},
 	{0x0104, 0x20},
-	{0x00aa, 0x3a},
+	{0x00aa, 0x38},
 	{0x00a7, 0x18},
 	{0x00a8, 0x10},
 	{0x00a1, 0xFF},
@@ -1427,22 +1424,23 @@ static int gc4c33_set_dpcc_cfg(struct gc4c33 *gc4c33,
 {
 	int ret = 0;
 
+#ifdef GC4C33_ENABLE_DPCC
 	if (dpcc->enable) {
 		ret = gc4c33_write_reg(gc4c33->client,
 				       GC4C33_REG_DPCC_ENABLE,
 				       GC4C33_REG_VALUE_08BIT,
-				       0x3a);
+				       0x38 | (dpcc->enable & 0x03));
 
 		ret |= gc4c33_write_reg(gc4c33->client,
 					GC4C33_REG_DPCC_SINGLE,
 					GC4C33_REG_VALUE_08BIT,
-					255 - dpcc->cur_dpcc *
+					255 - dpcc->cur_single_dpcc *
 					255 / dpcc->total_dpcc);
 
 		ret |= gc4c33_write_reg(gc4c33->client,
 					GC4C33_REG_DPCC_DOUBLE,
 					GC4C33_REG_VALUE_08BIT,
-					255 - dpcc->cur_dpcc *
+					255 - dpcc->cur_multiple_dpcc *
 					255 / dpcc->total_dpcc);
 	} else {
 		ret = gc4c33_write_reg(gc4c33->client,
@@ -1460,6 +1458,22 @@ static int gc4c33_set_dpcc_cfg(struct gc4c33 *gc4c33,
 					GC4C33_REG_VALUE_08BIT,
 					0xff);
 	}
+#else
+	ret = gc4c33_write_reg(gc4c33->client,
+			       GC4C33_REG_DPCC_ENABLE,
+			       GC4C33_REG_VALUE_08BIT,
+			       0x38);
+
+	ret |= gc4c33_write_reg(gc4c33->client,
+				GC4C33_REG_DPCC_SINGLE,
+				GC4C33_REG_VALUE_08BIT,
+				0xff);
+
+	ret |= gc4c33_write_reg(gc4c33->client,
+				GC4C33_REG_DPCC_DOUBLE,
+				GC4C33_REG_VALUE_08BIT,
+				0xff);
+#endif
 
 	return ret;
 }
@@ -1681,6 +1695,7 @@ static long gc4c33_compat_ioctl32(struct v4l2_subdev *sd,
 }
 #endif
 
+#ifdef GC4C33_ENABLE_OTP
 static int gc4c33_sensor_dpc_otp_dd(struct gc4c33 *gc4c33)
 {
 	u32 num = 0;
@@ -1783,6 +1798,7 @@ static int gc4c33_sensor_dpc_otp_dd(struct gc4c33 *gc4c33)
 
 	return ret;
 }
+#endif
 
 static int __gc4c33_start_stream(struct gc4c33 *gc4c33)
 {
@@ -1792,9 +1808,11 @@ static int __gc4c33_start_stream(struct gc4c33 *gc4c33)
 	if (ret)
 		return ret;
 
+#ifdef GC4C33_ENABLE_OTP
 	ret = gc4c33_sensor_dpc_otp_dd(gc4c33);
 	if (ret)
 		return ret;
+#endif
 
 	/* In case these controls are set before streaming */
 	mutex_unlock(&gc4c33->mutex);
diff --git a/include/uapi/linux/rk-camera-module.h b/include/uapi/linux/rk-camera-module.h
index eaa9dbb9c175..464c2e1ab498 100644
--- a/include/uapi/linux/rk-camera-module.h
+++ b/include/uapi/linux/rk-camera-module.h
@@ -244,9 +244,18 @@ struct rkmodule_lvds_cfg {
 	struct rkmodule_sync_code blk;
 } __attribute__ ((packed));
 
+/**
+ * struct rkmodule_dpcc_cfg
+ * enable: 0 -> disable dpcc, 1 -> enable multiple,
+ *         2 -> enable single, 3 -> enable all;
+ * cur_single_dpcc: the strength of single dpcc;
+ * cur_multiple_dpcc: the strength of multiple dpcc;
+ * total_dpcc: the max strength;
+ */
 struct rkmodule_dpcc_cfg {
 	__u32 enable;
-	__u32 cur_dpcc;
+	__u32 cur_single_dpcc;
+	__u32 cur_multiple_dpcc;
 	__u32 total_dpcc;
 } __attribute__ ((packed));