From f71b1f1b7052fb045f56976920e1a919b74cd6cb Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 10 Jan 2022 19:37:43 +0800 Subject: [PATCH] drm/rockchip: vop2: Reset axi clk in vop2_initial We notice a pd0 off timeout at system resume. This because we set pd_off_imd before vop suspend. but this will case VOP POWER_CTRL regisert record some wrong state, and will lead a POWER_CTRL register value change unexpectedly. So we reset axi clk to clear this state at vop2_inital to avoid the wrong register state. [35.874922] [drm:vop2_crtc_atomic_enable] Update mode to 1080x1920p60, type: 16 for vp3 dclk: 132000000 [35.875412] [drm:vop2_crtc_atomic_enable] dclk_out3 div: 0 dclk_core3 div: 0 [35.875424] [drm:vop2_crtc_atomic_enable] set dclk_vop3 to 33000000, get 33000000 [35.885838] <>[gt1x_request_event_handler:1093] Request Reset. [35.885866] <>[gt1x_reset_guitar:784] GTP RESET! [36.073639] [drm:dw_mipi_dsi2_encoder_enable] final DSI-Link bandwidth: 880 x 4 Mbps [36.141834] [drm:vop2_wait_power_domain_off] *ERROR* wait pd0 off timeout Fixes: 8684b9914503("drm/rockchip: vop2: power off all vop pd when enter suspend mode") Signed-off-by: Andy Yan Change-Id: I974573163e35e10dc0748aadc4966219465ed603 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 839c4986fd9b..d370dbd343ed 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3226,6 +3226,18 @@ static void vop2_initial(struct drm_crtc *crtc) return; } + /* + * we should rest axi to clear register state + * when set pd_off_imd in vop2_power_off_all_pd, + * otherwise the bit0/1/2 of POWER_CTRL register + * will auto cleared after we clear pd_off_imd + * in the following. + */ + if (vop2->version == VOP_VERSION_RK3588) { + if (!vp->loader_protect) + vop2_clk_reset(vop2->axi_rst); + } + if (vop2_soc_is_rk3566()) VOP_CTRL_SET(vop2, otp_en, 1);