From f736a39fb8c47638c45c7ad04fce8e42970de50b Mon Sep 17 00:00:00 2001
From: Hongming Zou <hongming.zou@rock-chips.com>
Date: Sun, 27 Apr 2025 10:56:37 +0800
Subject: [PATCH] ARM: dts: rockchip: update the init values of the ili9881d
 screen for all platforms that use it
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Modify the delay value of the screen wake-up from sleep mode
register from 0 to 150 ms

Modify the delay value of the screen display enable register
from 1 to 20 ms

The reason for the modification：

When the U-Boot display feature is disabled, the default
configuration may cause screen display failures

Change-Id: Icfdca35d9262b640ac0b26b2f9adab04e7a960b0
Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com>
---
 arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts | 4 ++--
 arch/arm/boot/dts/rk3506b-test2-v10.dts    | 4 ++--
 arch/arm/boot/dts/rv1126-evb-v10.dtsi      | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
index 57e797782d2f..61eeb4057997 100644
--- a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
+++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
@@ -435,8 +435,8 @@
 					15 00 02 d2 32
 					15 00 02 d3 00
 					39 00 04 ff 98 81 00
-					05 00 01 11
-					05 01 01 29
+					05 96 01 11
+					05 14 01 29
 				];
 			};
 		};
diff --git a/arch/arm/boot/dts/rk3506b-test2-v10.dts b/arch/arm/boot/dts/rk3506b-test2-v10.dts
index d310900872c2..822d39efcb82 100644
--- a/arch/arm/boot/dts/rk3506b-test2-v10.dts
+++ b/arch/arm/boot/dts/rk3506b-test2-v10.dts
@@ -433,8 +433,8 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
-			05 01 01 29
+			05 96 01 11
+			05 14 01 29
 		];
 
 		disp_timings0: display-timings {
diff --git a/arch/arm/boot/dts/rv1126-evb-v10.dtsi b/arch/arm/boot/dts/rv1126-evb-v10.dtsi
index 6098ea28eba7..ccc53ad4451d 100644
--- a/arch/arm/boot/dts/rv1126-evb-v10.dtsi
+++ b/arch/arm/boot/dts/rv1126-evb-v10.dtsi
@@ -430,8 +430,8 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
-			05 01 01 29
+			05 96 01 11
+			05 14 01 29
 		];
 
 		display-timings {