From f7645e0726c0ecd93d79727115fc9d12c01aa589 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Sat, 23 Jul 2022 17:33:17 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: assign vop aclk rate in vop node In common case, the 500MHz vop aclk rate can satisfy the vop request. For some high pixel clock case(8K@60Hz, 4K@120Hz, etc),the vop aclk should enhance to 800MHz to avoid abnormal display issue. When display a high pxel clock timing from bootloader to kernel, the bootloader will set the vop aclk rate to 800MHz. The vop driver in kernel will also set the vop aclk rate to 800MHz. But the clock driver will set the vop aclk rate to 800MHz before the vop driver. The vop aclk rate will change as: 800MHz->500MHz->800MHz, which will cause a flicker. To fix this issue, remove the vop aclk rate assign in clock controller node, and define it in vop node. Signed-off-by: Zhang Yubing Change-Id: I785fe464bba79bb2bcd63a8588d847edecef5a17 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 747c0656667a..9da438cde34e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2256,7 +2256,7 @@ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = @@ -2266,7 +2266,7 @@ <400000000>, <500000000>, <800000000>, <100000000>, <400000000>, <100000000>, - <200000000>, <500000000>, + <200000000>, <375000000>, <150000000>, <200000000>; }; @@ -3707,6 +3707,8 @@ "dclk_src_vp0", "dclk_src_vp1", "dclk_src_vp2"; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <500000000>; resets = <&cru SRST_A_VOP>, <&cru SRST_H_VOP>, <&cru SRST_D_VOP0>,