From f76c21e3bb0835d161aabfddff3b905ea6064f15 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 28 Mar 2020 15:56:21 +0800 Subject: [PATCH] ARM: dts: rockchip: rv11xx-evb-v10: enable cpu tsadc and npu tsadc Change-Id: I899fdaef6f43421f395c03f99a37bd1ffbc17b40 Signed-off-by: Elaine Zhang --- arch/arm/boot/dts/rv11xx-evb-v10.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/rv11xx-evb-v10.dtsi b/arch/arm/boot/dts/rv11xx-evb-v10.dtsi index e51bcb568420..eee86576a98e 100644 --- a/arch/arm/boot/dts/rv11xx-evb-v10.dtsi +++ b/arch/arm/boot/dts/rv11xx-evb-v10.dtsi @@ -188,6 +188,15 @@ cpu-supply = <&vdd_arm>; }; +&cpu_tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadcm0_pins>; + pinctrl-1 = <&tsadc_shutorg>; + status = "okay"; +}; + &display_subsystem { status = "okay"; }; @@ -792,6 +801,15 @@ status = "okay"; }; +&npu_tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadcm0_pins>; + pinctrl-1 = <&tsadc_shutorg>; + status = "okay"; +}; + &optee { status = "disabled"; };