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clk: imx: fracn-gppll: correct PLL initialization flow

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[ Upstream commit 557be501c38e1864b948fc6ccdf4b035d610a2ea ]

Per i.MX93 Reference Mannual 22.4 Initialization information
1. Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI]
   as per Integer mode.
2. Wait for 5 μs.
3. Program the following field in CTRL register.
   Set CTRL[POWERUP] to 1'b1 to enable PLL block.
4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK]
   is 1'b1 and pll_lock output signal is 1'b1.
5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock.

So move the CLKMUX_EN operation after PLL locked.

Fixes: 1b26cb8a77 ("clk: imx: support fracn gppll")
Co-developed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-2-89152574d1d7@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Peng Fan
2024-10-27 20:00:08 +08:00
committed by Greg Kroah-Hartman
parent c92515247f
commit f7aee64ed7
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/imx/clk-fracn-gppll.c
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@@ -299,13 +299,13 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
val |= POWERUP_MASK; val |= POWERUP_MASK;
writel_relaxed(val, pll->base + PLL_CTRL); writel_relaxed(val, pll->base + PLL_CTRL);
val |= CLKMUX_EN;
writel_relaxed(val, pll->base + PLL_CTRL);
ret = clk_fracn_gppll_wait_lock(pll); ret = clk_fracn_gppll_wait_lock(pll);
if (ret) if (ret)
return ret; return ret;
val |= CLKMUX_EN;
writel_relaxed(val, pll->base + PLL_CTRL);
val &= ~CLKMUX_BYPASS; val &= ~CLKMUX_BYPASS;
writel_relaxed(val, pll->base + PLL_CTRL); writel_relaxed(val, pll->base + PLL_CTRL);