From f807c08d2be8a7bb8d98a9c559d5ffcd383bcc88 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 11 Nov 2020 14:25:03 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: setting npll to 1.2G when clk init Signed-off-by: Elaine Zhang Change-Id: If088d432552d186866dd53211c5a2126870f62a4 --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index c0435c7e7c0b..20925e9205af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -541,7 +541,8 @@ <&cru ACLK_BUS>, <&cru PCLK_BUS>, <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>; + <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, + <&cru PLL_NPLL>; assigned-clock-rates = <32768>, <100000000>, <100000000>, <1000000000>, @@ -549,7 +550,8 @@ <150000000>, <100000000>, <300000000>, <200000000>, <150000000>, <100000000>, - <300000000>, <150000000>; + <300000000>, <150000000>, + <1200000000>; assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; };