From 54eb2c5f7f4c2133d812aae7bf1efa0f8108a08b Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Wed, 20 Feb 2019 08:46:54 +0900 Subject: [PATCH] ODROID-N2: clk: add 2.004GHz cpu freq for A73 core and change the max Change-Id: I99274d1084fc20a277a26669024391132da010f8 --- arch/arm64/boot/dts/amlogic/meson64_odroidn2.dts | 2 +- drivers/amlogic/clk/g12a/g12a.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson64_odroidn2.dts b/arch/arm64/boot/dts/amlogic/meson64_odroidn2.dts index ccdcede35298..d428391f5b55 100644 --- a/arch/arm64/boot/dts/amlogic/meson64_odroidn2.dts +++ b/arch/arm64/boot/dts/amlogic/meson64_odroidn2.dts @@ -433,7 +433,7 @@ opp-microvolt = <1022000>; }; opp12 { - opp-hz = /bits/ 64 <1992000000>; + opp-hz = /bits/ 64 <2004000000>; opp-microvolt = <1022000>; }; }; diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h index 3d3257505d11..40b9174e5a13 100644 --- a/drivers/amlogic/clk/g12a/g12a.h +++ b/drivers/amlogic/clk/g12a/g12a.h @@ -159,6 +159,7 @@ static const struct pll_rate_table g12a_pll_rate_table[] = { PLL_RATE(1968000000ULL, 164, 1, 1), /*DCO=3936M*/ PLL_RATE(1980000000ULL, 165, 1, 1), /*DCO=3960M*/ PLL_RATE(1992000000ULL, 166, 1, 1), /*DCO=3984M*/ + PLL_RATE(2004000000ULL, 167, 1, 1), /*DCO=4008M*/ PLL_RATE(2016000000ULL, 168, 1, 1), /*DCO=4032M*/ PLL_RATE(2100000000ULL, 175, 1, 1), /*DCO=4200M*/ PLL_RATE(2196000000ULL, 183, 1, 1), /*DCO=4392M*/