From f869a01da60e4b6eee97be1a7210780bc11fec3c Mon Sep 17 00:00:00 2001 From: hongmin hua Date: Mon, 4 Dec 2017 19:46:55 +0800 Subject: [PATCH] cec: set reg map before irq enable PD#158921: cec: change the order of irq in probe Change-Id: I8099e918a06c9d741de890b773ec6ca47ab44aba Signed-off-by: hongmin hua --- arch/arm64/boot/dts/amlogic/mesontxlx.dtsi | 18 ++++- drivers/amlogic/cec/hdmi_ao_cec.c | 90 ++++++++++++++++------ drivers/amlogic/cec/hdmi_ao_cec.h | 5 +- 3 files changed, 87 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/mesontxlx.dtsi b/arch/arm64/boot/dts/amlogic/mesontxlx.dtsi index 27a2af0e80ae..26c67a8ee99a 100644 --- a/arch/arm64/boot/dts/amlogic/mesontxlx.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesontxlx.dtsi @@ -904,11 +904,18 @@ hdmitx_aocec: ao_cec { mux { - groups = "ao_cec_ao7", - "ao_cec_ao8"; + groups = "ao_cec_ao7"; function = "ao_cec"; }; }; + + hdmitx_aocec1: ao_cec1 { + mux { + groups = "ao_cec_ao8"; + function = "ao_cec"; + }; + }; + hdmitx_aocecb: ao_cecb { mux { groups = "ao_cec_b_ao7"; @@ -916,6 +923,13 @@ }; }; + hdmitx_aocecb1: ao_cecb1 { + mux { + groups = "ao_cec_b_ao8"; + function = "ao_cec_b"; + }; + }; + remote_pins:remote_pin { mux { groups = "remote_in"; diff --git a/drivers/amlogic/cec/hdmi_ao_cec.c b/drivers/amlogic/cec/hdmi_ao_cec.c index 0492296f89f9..f9a77d3d2f39 100644 --- a/drivers/amlogic/cec/hdmi_ao_cec.c +++ b/drivers/amlogic/cec/hdmi_ao_cec.c @@ -279,6 +279,7 @@ static unsigned int hdmirx_cec_read(unsigned int reg) return hdmirx_rd_dwc(reg); } +/*only for ee cec*/ static void hdmirx_cec_write(unsigned int reg, unsigned int value) { /* @@ -528,12 +529,50 @@ static void ao_cecb_init(void) cec_set_reg_bits(AO_CECB_GEN_CNTL, 0, 0, 1); /* Enable all AO_CECB interrupt sources */ - writel(CECB_IRQ_EN_MASK, cec_dev->cec_reg + AO_CECB_INTR_MASKN); - CEC_INFO("enable:int mask:0x%x\n", - readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN)); + cec_irq_enable(true); hdmirx_cec_write(DWC_CEC_WKUPCTRL, 0); } +void eecec_irq_enable(bool enable) +{ + if (cec_dev->cpu_type < MESON_CPU_MAJOR_ID_TXLX) { + if (enable) + hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, + EE_CEC_IRQ_EN_MASK); + else { + hdmirx_cec_write(DWC_AUD_CEC_ICLR, + (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | + EE_CEC_IRQ_EN_MASK)); + hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, + hdmirx_cec_read(DWC_AUD_CEC_IEN) & + ~EE_CEC_IRQ_EN_MASK); + hdmirx_cec_write(DWC_AUD_CEC_IEN_CLR, + (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | + EE_CEC_IRQ_EN_MASK)); + } + CEC_INFO("ee enable:int mask:0x%x\n", + hdmirx_cec_read(DWC_AUD_CEC_IEN)); + } else { + if (enable) + writel(CECB_IRQ_EN_MASK, + cec_dev->cec_reg + AO_CECB_INTR_MASKN); + else + writel(readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN) + & ~CECB_IRQ_EN_MASK, + cec_dev->cec_reg + AO_CECB_INTR_MASKN); + CEC_INFO("ao move enable:int mask:0x%x\n", + readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN)); + } +} + +void cec_irq_enable(bool enable) +{ + if (ee_cec) + eecec_irq_enable(enable); + else + aocec_irq_enable(enable); +} + int cecrx_hw_init(void) { unsigned int data32; @@ -562,7 +601,7 @@ int cecrx_hw_init(void) hdmirx_set_bits_top(TOP_EDID_GEN_CNTL, EDID_AUTO_CEC_EN, 11, 1); /* enable all cec irq */ - hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, EE_CEC_IRQ_EN_MASK); + cec_irq_enable(true); /* clear all wake up source */ hdmirx_cec_write(DWC_CEC_WKUPCTRL, 0); /* cec enable */ @@ -638,10 +677,13 @@ static int dump_cecrx_reg(char *b) /*--------------------- END of EE CEC --------------------*/ -static void cec_enable_irq(void) +void aocec_irq_enable(bool enable) { - cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3); - CEC_INFO("enable:int mask:0x%x\n", + if (enable) + cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3); + else + cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x0, 0, 3); + CEC_INFO("ao enable:int mask:0x%x\n", readl(cec_dev->cec_reg + AO_CEC_INTR_MASKN)); } @@ -696,7 +738,7 @@ static void cec_hw_reset(void) cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); /* Enable all AO_CEC interrupt sources */ - cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3); + cec_irq_enable(true); cec_logicaddr_set(cec_dev->cec_info.log_addr); @@ -1112,7 +1154,7 @@ void ao_cec_init(void) cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); /* Enable all AO_CEC interrupt sources */ - cec_enable_irq(); + cec_irq_enable(true); } void cec_arbit_bit_time_set(unsigned int bit_set, @@ -2361,6 +2403,7 @@ static int aml_cec_probe(struct platform_device *pdev) cec_dev->dev_type = DEV_TYPE_PLAYBACK; cec_dev->dbg_dev = &pdev->dev; cec_dev->tx_dev = get_hdmitx_device(); + cec_dev->cpu_type = get_cpu_type(); phy_addr_test = 0; /* cdev registe */ @@ -2439,17 +2482,6 @@ static int aml_cec_probe(struct platform_device *pdev) else ee_cec = 0; CEC_INFO("using EE cec:%d\n", ee_cec); - - /* irq set */ - irq_idx = of_irq_get(node, 0); - cec_dev->irq_cec = irq_idx; - if (of_get_property(node, "interrupt-names", NULL)) { - r = of_property_read_string(node, "interrupt-names", &irq_name); - if (!r) - r = request_irq(irq_idx, - ee_cec ? &cecrx_isr : &cec_isr_handler, - IRQF_SHARED, irq_name, (void *)cec_dev); - } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) { base = ioremap(res->start, res->end - res->start); @@ -2521,6 +2553,22 @@ static int aml_cec_probe(struct platform_device *pdev) CEC_INFO("not find cec_version\n"); cec_dev->cec_info.cec_version = CEC_VERSION_20; } + + /* irq set */ + cec_irq_enable(false); + irq_idx = of_irq_get(node, 0); + cec_dev->irq_cec = irq_idx; + if (of_get_property(node, "interrupt-names", NULL)) { + r = of_property_read_string(node, "interrupt-names", &irq_name); + if (!r && !ee_cec) { + r = request_irq(irq_idx, &cec_isr_handler, IRQF_SHARED, + irq_name, (void *)cec_dev); + } + if (!r && ee_cec) { + r = request_irq(irq_idx, &cecrx_isr, IRQF_SHARED, + irq_name, (void *)cec_dev); + } + } #endif if (!ee_cec) { @@ -2533,7 +2581,6 @@ static int aml_cec_probe(struct platform_device *pdev) } } - #ifdef CONFIG_HAS_EARLYSUSPEND aocec_suspend_handler.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; aocec_suspend_handler.suspend = aocec_early_suspend; @@ -2543,7 +2590,6 @@ static int aml_cec_probe(struct platform_device *pdev) #endif hrtimer_init(&start_bit_check, CLOCK_MONOTONIC, HRTIMER_MODE_REL); start_bit_check.function = cec_line_check; - /*cec_dev->cpu_type = get_cpu_type();*/ /* for init */ cec_pre_init(); queue_delayed_work(cec_dev->cec_thread, &cec_dev->cec_work, 0); diff --git a/drivers/amlogic/cec/hdmi_ao_cec.h b/drivers/amlogic/cec/hdmi_ao_cec.h index cb95e1541f63..86ef110ed3d1 100644 --- a/drivers/amlogic/cec/hdmi_ao_cec.h +++ b/drivers/amlogic/cec/hdmi_ao_cec.h @@ -18,7 +18,7 @@ #ifndef __AO_CEC_H__ #define __AO_CEC_H__ -#define CEC_DRIVER_VERSION "2017/12/11\n" +#define CEC_DRIVER_VERSION "2017/01/23\n" #define CEC_FRAME_DELAY msecs_to_jiffies(400) #define CEC_DEV_NAME "cec" @@ -223,7 +223,6 @@ #define TOP_HPD_PWR5V 0x002 #define TOP_ARCTX_CNTL 0x010 - #define TOP_CLK_CNTL 0x001 #define TOP_EDID_GEN_CNTL 0x004 #define TOP_EDID_ADDR_CEC 0x005 @@ -371,6 +370,8 @@ void cecrx_irq_handle(void); void cec_logicaddr_set(int l_add); void cec_arbit_bit_time_set(unsigned int bit_set, unsigned int time_set, unsigned int flag); +void cec_irq_enable(bool enable); +void aocec_irq_enable(bool enable); #endif #ifdef CONFIG_AMLOGIC_MEDIA_TVIN_HDMI