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PCI/PM: Increase wait time after resume

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[ Upstream commit e8b908146d ]

PCIe r6.0 sec 6.6.1 prescribes that a device must be able to respond to
config requests within 1.0 s (PCI_RESET_WAIT) after exiting conventional
reset and this same delay is prescribed when coming out of D3cold (as that
involves reset too).

A device that requires more than 1 second to initialize after reset may
respond to config requests with Request Retry Status completions (sec
2.3.1), and we accommodate that in Linux with a 60 second cap
(PCIE_RESET_READY_POLL_MS).

Previously we waited up to PCIE_RESET_READY_POLL_MS only in the reset code
path, not in the resume path.  However, a device has surfaced, namely Intel
Titan Ridge xHCI, which requires a longer delay also in the resume code
path.

Make the resume code path to use this same extended delay as the reset
path.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216728
Link: https://lore.kernel.org/r/20230404052714.51315-2-mika.westerberg@linux.intel.com
Reported-by: Chris Chiu <chris.chiu@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lukas Wunner <lukas@wunner.de>
Stable-dep-of: 3e40aa29d47e ("PCI: Wait for Link before restoring Downstream Buses")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Mika Westerberg
2023-04-04 08:27:13 +03:00
committed by Greg Kroah-Hartman
parent 3dba83d3c8
commit f88f1145e1
1 changed files with 2 additions and 1 deletions
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3
drivers/pci/pci-driver.c
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@@ -579,7 +579,8 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)
{
pci_bridge_wait_for_secondary_bus(pci_dev, "resume", PCI_RESET_WAIT);
pci_bridge_wait_for_secondary_bus(pci_dev, "resume",
PCIE_RESET_READY_POLL_MS);
/*
* When powering on a bridge from D3cold, the whole hierarchy may be
* powered on into D0uninitialized state, resume them to give them a