From 1049814eba16b163d281fe4de51dc97eef947184 Mon Sep 17 00:00:00 2001 From: Wei Dun Date: Fri, 15 Aug 2025 18:16:37 +0800 Subject: [PATCH 01/14] media: rockchp: vpss: remove 16-byte alignment enforcement for input/output stride Change-Id: I7e0cd8a7e9dc194d8acc936ed9b0395ae8e8383a Signed-off-by: Wei Dun --- .../platform/rockchip/vpss/vpss_offline_v20.c | 77 +++---------------- 1 file changed, 11 insertions(+), 66 deletions(-) diff --git a/drivers/media/platform/rockchip/vpss/vpss_offline_v20.c b/drivers/media/platform/rockchip/vpss/vpss_offline_v20.c index 2802a156befb..f8fc1068f3d0 100644 --- a/drivers/media/platform/rockchip/vpss/vpss_offline_v20.c +++ b/drivers/media/platform/rockchip/vpss/vpss_offline_v20.c @@ -960,12 +960,15 @@ static int read_config(struct rkvpss_offline_dev *ofl, u32 in_ctrl, in_size, in_c_offs, unite_r_offs, val, mask, unite_off = 0, enlarge = 0, header_size = 0, payload_size = 0; + if (!IS_ALIGNED(cfg->input.stride, 4)) { + v4l2_err(&ofl->v4l2_dev, "input stride %d is not 4-byte aligned\n", cfg->input.stride); + return -EINVAL; + } + in_c_offs = 0; in_ctrl = 0; switch (cfg->input.format) { case V4L2_PIX_FMT_NV16: - if (cfg->input.stride < ALIGN(cfg->input.width, 16)) - cfg->input.stride = ALIGN(cfg->input.width, 16); in_c_offs = cfg->input.ver_stride ? cfg->input.stride * cfg->input.ver_stride : cfg->input.stride * cfg->input.height; @@ -974,8 +977,6 @@ static int read_config(struct rkvpss_offline_dev *ofl, unite_off = 8; break; case V4L2_PIX_FMT_NV12: - if (cfg->input.stride < ALIGN(cfg->input.width, 16)) - cfg->input.stride = ALIGN(cfg->input.width, 16); in_c_offs = cfg->input.ver_stride ? cfg->input.stride * cfg->input.ver_stride : cfg->input.stride * cfg->input.height; @@ -984,8 +985,6 @@ static int read_config(struct rkvpss_offline_dev *ofl, unite_off = 8; break; case V4L2_PIX_FMT_NV61: - if (cfg->input.stride < ALIGN(cfg->input.width, 16)) - cfg->input.stride = ALIGN(cfg->input.width, 16); in_c_offs = cfg->input.ver_stride ? cfg->input.stride * cfg->input.ver_stride : cfg->input.stride * cfg->input.height; @@ -994,8 +993,6 @@ static int read_config(struct rkvpss_offline_dev *ofl, unite_off = 8; break; case V4L2_PIX_FMT_NV21: - if (cfg->input.stride < ALIGN(cfg->input.width, 16)) - cfg->input.stride = ALIGN(cfg->input.width, 16); in_c_offs = cfg->input.ver_stride ? cfg->input.stride * cfg->input.ver_stride : cfg->input.stride * cfg->input.height; @@ -1004,58 +1001,42 @@ static int read_config(struct rkvpss_offline_dev *ofl, unite_off = 8; break; case V4L2_PIX_FMT_RGB565: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_BGR565; unite_off = 16; break; case V4L2_PIX_FMT_RGB565X: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_BGR565 | RKVPSS_MI_RD_RB_SWAP; unite_off = 16; break; case V4L2_PIX_FMT_RGB24: - if (cfg->input.stride < ALIGN(cfg->input.width * 3, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 3, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_BGR888; unite_off = 24; break; case V4L2_PIX_FMT_BGR24: - if (cfg->input.stride < ALIGN(cfg->input.width * 3, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 3, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_BGR888 | RKVPSS_MI_RD_RB_SWAP; unite_off = 24; break; case V4L2_PIX_FMT_XRGB32: - if (cfg->input.stride < ALIGN(cfg->input.width * 4, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 4, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_ABGR888; unite_off = 32; break; case V4L2_PIX_FMT_XBGR32: - if (cfg->input.stride < ALIGN(cfg->input.width * 4, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 4, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_ABGR888 | RKVPSS_MI_RD_RB_SWAP; unite_off = 32; break; case V4L2_PIX_FMT_RGBX32: - if (cfg->input.stride < ALIGN(cfg->input.width * 4, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 4, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_ABGR888 | RKVPSS_MI_RD_ALPHA_SWAP; unite_off = 32; break; case V4L2_PIX_FMT_BGRX32: - if (cfg->input.stride < ALIGN(cfg->input.width * 4, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 4, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS_MI_RD_INPUT_ABGR888 | RKVPSS_MI_RD_RB_SWAP @@ -1093,43 +1074,31 @@ static int read_config(struct rkvpss_offline_dev *ofl, in_ctrl |= RKVPSS_MI_RD_INPUT_422SP | RKVPSS_MI_RD_FBCD_YUV444_EN; break; case V4L2_PIX_FMT_TILE420: - if (cfg->input.stride < ALIGN(cfg->input.width * 6, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 6, 16); in_c_offs = 0; in_size = cfg->input.stride * (cfg->input.height / 4); in_ctrl |= RKVPSS_MI_RD_INPUT_420SP; break; case V4L2_PIX_FMT_TILE422: - if (cfg->input.stride < ALIGN(cfg->input.width * 8, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 8, 16); in_c_offs = 0; in_size = cfg->input.stride * (cfg->input.height / 4); in_ctrl |= RKVPSS_MI_RD_INPUT_422SP; break; case V4L2_PIX_FMT_UYVY: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS2X_MI_RD_INPUT_UYVY; //unite_off todo break; case V4L2_PIX_FMT_VYUY: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS2X_MI_RD_INPUT_UYVY | RKVPSS_MI_RD_UV_SWAP; //unite_off todo break; case V4L2_PIX_FMT_YUYV: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS2X_MI_RD_INPUT_UYVY | RKVPSS_MI_RD_RB_SWAP; //unite_off todo break; case V4L2_PIX_FMT_YVYU: - if (cfg->input.stride < ALIGN(cfg->input.width * 2, 16)) - cfg->input.stride = ALIGN(cfg->input.width * 2, 16); in_size = cfg->input.stride * cfg->input.height; in_ctrl |= RKVPSS2X_MI_RD_INPUT_UYVY | RKVPSS_MI_RD_RB_SWAP | RKVPSS_MI_RD_UV_SWAP; //unite_off todo @@ -1398,6 +1367,12 @@ static int write_config(struct rkvpss_offline_dev *ofl, continue; ch_en = true; + if (!IS_ALIGNED(cfg->output[i].stride, 4)) { + v4l2_err(&ofl->v4l2_dev, "output stride %d is not 4-byte aligned for ch%d\n", + cfg->output[i].stride, i); + return -EINVAL; + } + if (cfg->output[i].aspt.enable) { w = cfg->output[i].aspt.width; h = cfg->output[i].aspt.height; @@ -1410,36 +1385,24 @@ static int write_config(struct rkvpss_offline_dev *ofl, switch (cfg->output[i].format) { case V4L2_PIX_FMT_RGB565: - if (cfg->output[i].stride < ALIGN(w * 2, 16)) - cfg->output[i].stride = ALIGN(w * 2, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_RGB565 | RKVPSS_MI_CHN_WR_RB_SWAP; break; case V4L2_PIX_FMT_RGB24: - if (cfg->output[i].stride < ALIGN(w * 3, 16)) - cfg->output[i].stride = ALIGN(w * 3, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_RGB888 | RKVPSS_MI_CHN_WR_RB_SWAP; break; case V4L2_PIX_FMT_RGB565X: - if (cfg->output[i].stride < ALIGN(w * 2, 16)) - cfg->output[i].stride = ALIGN(w * 2, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_RGB565; break; case V4L2_PIX_FMT_BGR24: - if (cfg->output[i].stride < ALIGN(w * 3, 16)) - cfg->output[i].stride = ALIGN(w * 3, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_RGB888; break; case V4L2_PIX_FMT_XBGR32: - if (cfg->output[i].stride < ALIGN(w * 4, 16)) - cfg->output[i].stride = ALIGN(w * 4, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_ARGB888 | RKVPSS2X_CH1_WR_RGB888_ALPHA(cfg->output[i].alpha); break; case V4L2_PIX_FMT_XRGB32: - if (cfg->output[i].stride < ALIGN(w * 4, 16)) - cfg->output[i].stride = ALIGN(w * 4, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_ARGB888 | RKVPSS_MI_CHN_WR_RB_SWAP | RKVPSS2X_CH1_WR_RGB888_ALPHA(cfg->output[i].alpha); @@ -1455,61 +1418,43 @@ static int write_config(struct rkvpss_offline_dev *ofl, } switch (cfg->output[i].format) { case V4L2_PIX_FMT_UYVY: - if (cfg->output[i].stride < ALIGN(w * 2, 16)) - cfg->output[i].stride = ALIGN(w * 2, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_422P | RKVPSS_MI_CHN_WR_OUTPUT_YUV422; out_ch[i].size = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_NV16: - if (cfg->output[i].stride < ALIGN(w, 16)) - cfg->output[i].stride = ALIGN(w, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_42XSP | RKVPSS_MI_CHN_WR_OUTPUT_YUV422; out_ch[i].size = cfg->output[i].stride * h * 2; out_ch[i].c_offs = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_NV12: - if (cfg->output[i].stride < ALIGN(w, 16)) - cfg->output[i].stride = ALIGN(w, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_42XSP | RKVPSS_MI_CHN_WR_OUTPUT_YUV420; out_ch[i].size = cfg->output[i].stride * h * 3 / 2; out_ch[i].c_offs = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_GREY: - if (cfg->output[i].stride < ALIGN(w, 16)) - cfg->output[i].stride = ALIGN(w, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_42XSP | RKVPSS_MI_CHN_WR_OUTPUT_YUV400; out_ch[i].size = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_VYUY: - if (cfg->output[i].stride < ALIGN(w * 2, 16)) - cfg->output[i].stride = ALIGN(w * 2, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_422P | RKVPSS_MI_CHN_WR_OUTPUT_YUV422; out_ch[i].size = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_NV61: - if (cfg->output[i].stride < ALIGN(w, 16)) - cfg->output[i].stride = ALIGN(w, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_42XSP | RKVPSS_MI_CHN_WR_OUTPUT_YUV422; out_ch[i].size = cfg->output[i].stride * h * 2; out_ch[i].c_offs = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_NV21: - if (cfg->output[i].stride < ALIGN(w, 16)) - cfg->output[i].stride = ALIGN(w, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_42XSP | RKVPSS_MI_CHN_WR_OUTPUT_YUV420; out_ch[i].size = cfg->output[i].stride * h * 3 / 2; out_ch[i].c_offs = cfg->output[i].stride * h; break; case V4L2_PIX_FMT_TILE420: - if (cfg->output[i].stride < ALIGN(w * 6, 16)) - cfg->output[i].stride = ALIGN(w * 6, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_YUV420; out_ch[i].size = cfg->output[i].stride * (h / 4); out_ch[i].c_offs = 0; break; case V4L2_PIX_FMT_TILE422: - if (cfg->output[i].stride < ALIGN(w * 8, 16)) - cfg->output[i].stride = ALIGN(w * 8, 16); out_ch[i].ctrl |= RKVPSS_MI_CHN_WR_OUTPUT_YUV422; out_ch[i].size = cfg->output[i].stride * (h / 4); out_ch[i].c_offs = 0; From 879a729b8e0f4fad568fd565975dfa34bee53025 Mon Sep 17 00:00:00 2001 From: Simon Xue Date: Mon, 18 Aug 2025 10:34:48 +0800 Subject: [PATCH 02/14] soc: rockchip: decompress: remove unused code Change-Id: I878281c56ad9895989c04ed1cec5bfcf16f61fb4 Signed-off-by: Simon Xue --- drivers/soc/rockchip/rockchip_decompress.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/soc/rockchip/rockchip_decompress.c b/drivers/soc/rockchip/rockchip_decompress.c index 15b4f6601a8e..0b929516ad41 100644 --- a/drivers/soc/rockchip/rockchip_decompress.c +++ b/drivers/soc/rockchip/rockchip_decompress.c @@ -516,7 +516,7 @@ static int __init rockchip_decom_probe(struct platform_device *pdev) rk_dec->regs = devm_ioremap_resource(dev, res); if (IS_ERR(rk_dec->regs)) { ret = PTR_ERR(rk_dec->regs); - goto disable_clk; + return ret; } dev_set_drvdata(dev, rk_dec); @@ -536,7 +536,7 @@ static int __init rockchip_decom_probe(struct platform_device *pdev) dev_name(dev), rk_dec); if (ret < 0) { dev_err(dev, "failed to attach decompress irq\n"); - goto disable_clk; + return ret; } #ifdef CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST @@ -554,11 +554,6 @@ static int __init rockchip_decom_probe(struct platform_device *pdev) pm_runtime_get_sync(dev); #endif return 0; - -disable_clk: - clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks); - - return ret; } #ifndef CONFIG_ROCKCHIP_THUNDER_BOOT From 9ea89e99814133af156bfd741dcbfe136cee9cd8 Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Fri, 15 Aug 2025 15:52:01 +0800 Subject: [PATCH 03/14] arm64: configs: rv1126b_defconfig enable CONFIG_ROCKCHIP_DVBM Signed-off-by: Weiwen Chen Change-Id: I317e67b6869542b2be70d4080979fc651970e412 --- arch/arm64/configs/rv1126b_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/rv1126b_defconfig b/arch/arm64/configs/rv1126b_defconfig index 85b593fd9387..c649afc8aefe 100644 --- a/arch/arm64/configs/rv1126b_defconfig +++ b/arch/arm64/configs/rv1126b_defconfig @@ -226,6 +226,7 @@ CONFIG_ROCKCHIP_MULTI_RGA=y CONFIG_ROCKCHIP_RGA_PROC_FS=y # CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set CONFIG_ROCKCHIP_MPP_OSAL=y +CONFIG_ROCKCHIP_DVBM=y CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_PCM_TIMER is not set @@ -292,7 +293,6 @@ CONFIG_STAGING=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCMI=y CONFIG_ROCKCHIP_CLK_OUT=y -# CONFIG_ROCKCHIP_CLK_PVTM is not set CONFIG_ROCKCHIP_CLK_PVTPLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_ROCKCHIP=y From f70f311a71635253caba3853f2d2d25383278de0 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 14 Jul 2025 15:13:34 +0800 Subject: [PATCH 04/14] drm/rockchip: vop2: add support disable-writeback property Sometimes we want to disable the writeback function, which can be achieved by adding the following configuration at the DTS: &vop { rockchip,disable-writeback; }; Signed-off-by: Sandy Huang Change-Id: I221f6cb801c46392a545d3d37d9c27ed985d1679 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 27 +++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 0ead76c1ac89..11c9fbac60f7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -965,6 +965,9 @@ struct vop2 { */ bool report_post_buf_empty; + /* disable vop writeback */ + bool disable_wb; + bool loader_protect; bool aclk_rate_reset; @@ -3978,6 +3981,9 @@ static void vop2_wb_commit(struct drm_crtc *crtc) uint32_t fifo_throd; uint8_t r2y; + if (!vop2->wb.regs) + return; + if (!conn_state) return; wb_state = to_wb_state(conn_state); @@ -4699,9 +4705,10 @@ static void vop2_initial(struct drm_crtc *crtc) rk3588_vop2_regsbak(vop2); else memcpy(vop2->regsbak, vop2->base_res.regs, vop2->len); - - VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd); - VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe); + if (vop2->wb.regs) { + VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd); + VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe); + } vop2_wb_cfg_done(vp); if (is_vop3(vop2)) { @@ -13441,9 +13448,11 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_stat struct drm_writeback_connector *wb_conn = &wb->conn; struct drm_connector_state *conn_state = wb_conn->base.state; bool wb_mode = conn_state && conn_state->writeback_job && conn_state->writeback_job->fb; - bool wb_oneframe_mode = VOP_MODULE_GET(vop2, wb, one_frame_mode); bool dovi_mode = vop2_is_dovi_mode(vp) && vp->enabled_win_mask; + bool wb_oneframe_mode = false; + if (vop2->wb.regs) + wb_oneframe_mode = VOP_MODULE_GET(vop2, wb, one_frame_mode); #if defined(CONFIG_ROCKCHIP_DRM_DEBUG) if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP || vp->rockchip_crtc.vop_dump_times > 0) { @@ -14141,8 +14150,12 @@ static void vop2_wb_handler(struct vop2_video_port *vp) uint8_t wb_en; uint8_t wb_vp_id; uint8_t i; - bool wb_oneframe_mode = VOP_MODULE_GET(vop2, wb, one_frame_mode); + bool wb_oneframe_mode; + if (!vop2->wb.regs) + return; + + wb_oneframe_mode = VOP_MODULE_GET(vop2, wb, one_frame_mode); wb_en = VOP_MODULE_GET(vop2, wb, enable); wb_vp_id = VOP_MODULE_GET(vop2, wb, vp_id); if (wb_vp_id != vp->id) @@ -16318,6 +16331,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) vop2->skip_ref_fb = of_property_read_bool(dev->of_node, "skip-ref-fb"); vop2->report_iommu_fault = of_property_read_bool(dev->of_node, "rockchip,report-iommu-fault"); vop2->report_post_buf_empty = of_property_read_bool(dev->of_node, "rockchip,report-post-buf-empty"); + vop2->disable_wb = of_property_read_bool(dev->of_node, "rockchip,disable-writeback"); if (!is_vop3(vop2) || vop2->version == VOP_VERSION_RK3528 || vop2->version == VOP_VERSION_RK3562) vop2->merge_irq = true; @@ -16556,7 +16570,8 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return ret; vop2_clk_init(vop2); vop2_cubic_lut_init(vop2); - vop2_wb_connector_init(vop2, registered_num_crtcs); + if (!vop2->disable_wb) + vop2_wb_connector_init(vop2, registered_num_crtcs); rockchip_drm_dma_init_device(drm_dev, vop2->dev); pm_runtime_enable(&pdev->dev); rockchip_vop2_devfreq_init(vop2); From 48ae95492817d99af11db3fc7e563a88e23b5d03 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 12 Feb 2025 12:29:32 +0800 Subject: [PATCH 05/14] drm/rockchip: dsi2: add support support vrr by changing dclk in auto mode Auto-Calculation mode Allows IPI frames to change dynamically with the controller adapting the output frames in vrr mode. Signed-off-by: Guochun Huang Change-Id: Ibcdc520db4b5546ca5877eb02145a5fac7ab7a2c --- .../gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 4db0bd1314bc..f66bb94ad0cb 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -293,6 +293,9 @@ struct dw_mipi_dsi2 { bool support_psr; bool enabled; + + unsigned int min_refresh_rate; + unsigned int max_refresh_rate; }; static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host) @@ -1143,6 +1146,18 @@ dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder, s->color_encoding = DRM_COLOR_YCBCR_BT709; s->color_range = DRM_COLOR_YCBCR_FULL_RANGE; + if (dsi2->auto_calc_mode && dsi2->max_refresh_rate && dsi2->min_refresh_rate) { + int refresh_rate; + + refresh_rate = drm_mode_vrefresh(&crtc_state->adjusted_mode); + if (refresh_rate > dsi2->max_refresh_rate || refresh_rate < dsi2->min_refresh_rate) + return -EINVAL; + + s->max_refresh_rate = dsi2->max_refresh_rate; + s->min_refresh_rate = dsi2->min_refresh_rate; + s->vrr_type = ROCKCHIP_VRR_DCLK_MODE; + } + if (dw_mipi_dsi2_is_cmd_mode(dsi2)) { s->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; s->soft_te = dsi2->te_gpio ? true : false; @@ -1997,9 +2012,18 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev) dsi2->pdata = of_device_get_match_data(dev); platform_set_drvdata(pdev, dsi2); - if (device_property_read_bool(dev, "auto-calculation-mode")) + if (device_property_read_bool(dev, "auto-calculation-mode")) { dsi2->auto_calc_mode = true; + device_property_read_u32(dev, "min-refresh-rate", &dsi2->min_refresh_rate); + device_property_read_u32(dev, "max-refresh-rate", &dsi2->max_refresh_rate); + + if (dsi2->max_refresh_rate <= dsi2->min_refresh_rate) { + dsi2->min_refresh_rate = 0; + dsi2->max_refresh_rate = 0; + } + } + if (device_property_read_bool(dev, "disable-hold-mode")) dsi2->disable_hold_mode = true; From 7006cfe4d3884d5444b9c164211c8bd526077093 Mon Sep 17 00:00:00 2001 From: LongChang Ma Date: Sat, 16 Aug 2025 15:11:24 +0800 Subject: [PATCH 06/14] media: i2c: format sc635hai code to kernel style Signed-off-by: LongChang Ma Change-Id: Ifd860772ed214bb55cdcc5ec3af5b8ed46a33632 --- drivers/media/i2c/sc635hai.c | 280 +++++++++++++++++------------------ 1 file changed, 140 insertions(+), 140 deletions(-) diff --git a/drivers/media/i2c/sc635hai.c b/drivers/media/i2c/sc635hai.c index 39af548b8b82..1bca634be43c 100644 --- a/drivers/media/i2c/sc635hai.c +++ b/drivers/media/i2c/sc635hai.c @@ -1153,7 +1153,7 @@ static const char *const sc635hai_test_pattern_menu[] = { static int sc635hai_write_reg(struct i2c_client *client, u16 reg, - u32 len, u32 val) + u32 len, u32 val) { u32 buf_i, val_i; u8 buf[6]; @@ -1180,20 +1180,20 @@ static int sc635hai_write_reg(struct i2c_client *client, u16 reg, } static int sc635hai_write_array(struct i2c_client *client, - const struct regval *regs) + const struct regval *regs) { u32 i; int ret = 0; for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) ret = sc635hai_write_reg(client, regs[i].addr, - SC635HAI_REG_VALUE_08BIT, regs[i].val); + SC635HAI_REG_VALUE_08BIT, regs[i].val); return ret; } static int sc635hai_read_reg(struct i2c_client *client, u16 reg, unsigned int len, - u32 *val) + u32 *val) { struct i2c_msg msgs[2]; u8 *data_be_p; @@ -1302,44 +1302,44 @@ static int sc635hai_set_gain_reg(struct sc635hai *sc635hai, u32 gain, int mode) if (mode == SC635HAI_LGAIN) { ret = sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_DIG_GAIN, - SC635HAI_REG_VALUE_08BIT, - coarse_dgain); - ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_DIG_FINE_GAIN, + SC635HAI_REG_DIG_GAIN, SC635HAI_REG_VALUE_08BIT, - fine_dgain); + coarse_dgain); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_ANA_GAIN, - SC635HAI_REG_VALUE_08BIT, - coarse_again); + SC635HAI_REG_DIG_FINE_GAIN, + SC635HAI_REG_VALUE_08BIT, + fine_dgain); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_ANA_FINE_GAIN, - SC635HAI_REG_VALUE_08BIT, - fine_again); + SC635HAI_REG_ANA_GAIN, + SC635HAI_REG_VALUE_08BIT, + coarse_again); + ret |= sc635hai_write_reg(sc635hai->client, + SC635HAI_REG_ANA_FINE_GAIN, + SC635HAI_REG_VALUE_08BIT, + fine_again); } else { ret = sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SDIG_GAIN, - SC635HAI_REG_VALUE_08BIT, - coarse_dgain); - ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SDIG_FINE_GAIN, + SC635HAI_REG_SDIG_GAIN, SC635HAI_REG_VALUE_08BIT, - fine_dgain); + coarse_dgain); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SANA_GAIN, - SC635HAI_REG_VALUE_08BIT, - coarse_again); + SC635HAI_REG_SDIG_FINE_GAIN, + SC635HAI_REG_VALUE_08BIT, + fine_dgain); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SANA_FINE_GAIN, - SC635HAI_REG_VALUE_08BIT, - fine_again); + SC635HAI_REG_SANA_GAIN, + SC635HAI_REG_VALUE_08BIT, + coarse_again); + ret |= sc635hai_write_reg(sc635hai->client, + SC635HAI_REG_SANA_FINE_GAIN, + SC635HAI_REG_VALUE_08BIT, + fine_again); } return ret; } static int sc635hai_set_hdrae(struct sc635hai *sc635hai, - struct preisp_hdrae_exp_s *ae) + struct preisp_hdrae_exp_s *ae) { int ret = 0; u32 l_exp_time, m_exp_time, s_exp_time; @@ -1392,25 +1392,25 @@ static int sc635hai_set_hdrae(struct sc635hai *sc635hai, s_exp_time = 184; ret = sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_H, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_H(l_exp_time)); - ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_M, + SC635HAI_REG_EXPOSURE_H, SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_M(l_exp_time)); + SC635HAI_FETCH_EXP_H(l_exp_time)); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_L, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_L(l_exp_time)); + SC635HAI_REG_EXPOSURE_M, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_M(l_exp_time)); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SEXPOSURE_M, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_M(s_exp_time)); + SC635HAI_REG_EXPOSURE_L, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_L(l_exp_time)); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_SEXPOSURE_L, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_L(s_exp_time)); + SC635HAI_REG_SEXPOSURE_M, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_M(s_exp_time)); + ret |= sc635hai_write_reg(sc635hai->client, + SC635HAI_REG_SEXPOSURE_L, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_L(s_exp_time)); ret |= sc635hai_set_gain_reg(sc635hai, l_a_gain, SC635HAI_LGAIN); ret |= sc635hai_set_gain_reg(sc635hai, s_a_gain, SC635HAI_SGAIN); @@ -1418,7 +1418,7 @@ static int sc635hai_set_hdrae(struct sc635hai *sc635hai, } static int sc635hai_get_reso_dist(const struct sc635hai_mode *mode, - struct v4l2_mbus_framefmt *framefmt) + struct v4l2_mbus_framefmt *framefmt) { return abs(mode->width - framefmt->width) + abs(mode->height - framefmt->height); @@ -1449,8 +1449,8 @@ sc635hai_find_best_fit(struct sc635hai *sc635hai, struct v4l2_subdev_format *fmt } static int sc635hai_set_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_format *fmt) + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) { struct sc635hai *sc635hai = to_sc635hai(sd); const struct sc635hai_mode *mode; @@ -1498,8 +1498,8 @@ static int sc635hai_set_fmt(struct v4l2_subdev *sd, } static int sc635hai_get_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_format *fmt) + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) { struct sc635hai *sc635hai = to_sc635hai(sd); const struct sc635hai_mode *mode = sc635hai->cur_mode; @@ -1529,8 +1529,8 @@ static int sc635hai_get_fmt(struct v4l2_subdev *sd, } static int sc635hai_enum_mbus_code(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_mbus_code_enum *code) + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) { if (code->index >= ARRAY_SIZE(bus_code)) return -EINVAL; @@ -1540,8 +1540,8 @@ static int sc635hai_enum_mbus_code(struct v4l2_subdev *sd, } static int sc635hai_enum_frame_sizes(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_frame_size_enum *fse) + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) { struct sc635hai *sc635hai = to_sc635hai(sd); @@ -1565,19 +1565,19 @@ static int sc635hai_enable_test_pattern(struct sc635hai *sc635hai, u32 pattern) int ret = 0; ret = sc635hai_read_reg(sc635hai->client, SC635HAI_REG_TEST_PATTERN, - SC635HAI_REG_VALUE_08BIT, &val); + SC635HAI_REG_VALUE_08BIT, &val); if (pattern) val |= SC635HAI_TEST_PATTERN_BIT_MASK; else val &= ~SC635HAI_TEST_PATTERN_BIT_MASK; ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_TEST_PATTERN, - SC635HAI_REG_VALUE_08BIT, val); + SC635HAI_REG_VALUE_08BIT, val); return ret; } static int sc635hai_g_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_frame_interval *fi) + struct v4l2_subdev_frame_interval *fi) { struct sc635hai *sc635hai = to_sc635hai(sd); const struct sc635hai_mode *mode = sc635hai->cur_mode; @@ -1614,7 +1614,7 @@ static const struct sc635hai_mode *sc635hai_find_mode(struct sc635hai *sc635hai, } static int sc635hai_s_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_frame_interval *fi) + struct v4l2_subdev_frame_interval *fi) { struct sc635hai *sc635hai = to_sc635hai(sd); const struct sc635hai_mode *mode = NULL; @@ -1662,8 +1662,8 @@ static int sc635hai_s_frame_interval(struct v4l2_subdev *sd, } static int sc635hai_g_mbus_config(struct v4l2_subdev *sd, - unsigned int pad_id, - struct v4l2_mbus_config *config) + unsigned int pad_id, + struct v4l2_mbus_config *config) { struct sc635hai *sc635hai = to_sc635hai(sd); u8 lanes = sc635hai->bus_cfg.bus.mipi_csi2.num_data_lanes; @@ -1675,7 +1675,7 @@ static int sc635hai_g_mbus_config(struct v4l2_subdev *sd, } static void sc635hai_get_module_inf(struct sc635hai *sc635hai, - struct rkmodule_inf *inf) + struct rkmodule_inf *inf) { memset(inf, 0, sizeof(*inf)); strscpy(inf->base.sensor, SC635HAI_NAME, sizeof(inf->base.sensor)); @@ -1861,8 +1861,8 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) usleep_range(4000, 5000); /* mipi clk on */ ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_MIPI_CTRL, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MIPI_CTRL_ON); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MIPI_CTRL_ON); /* adjust timing */ ret |= sc635hai_adjust_time(sc635hai); @@ -1872,8 +1872,8 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) /* Check if the current mode is HDR and cam sw info is available */ if (sc635hai->cur_mode->hdr_mode != NO_HDR && sc635hai->cam_sw_inf) { ret = sc635hai_ioctl(&sc635hai->subdev, - PREISP_CMD_SET_HDRAE_EXP, - &sc635hai->cam_sw_inf->hdr_ae); + PREISP_CMD_SET_HDRAE_EXP, + &sc635hai->cam_sw_inf->hdr_ae); if (ret) { dev_err(&sc635hai->client->dev, "Failed init exp fail in hdr mode\n"); @@ -1885,8 +1885,8 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) /* stream on */ ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MODE_STREAMING); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MODE_STREAMING); dev_info(&sc635hai->client->dev, "quickstream, streaming on: exit hw standby mode\n"); } else { @@ -1895,12 +1895,12 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) /* stream off */ ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MODE_SW_STANDBY); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MODE_SW_STANDBY); /* mipi clk off */ ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_MIPI_CTRL, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MIPI_CTRL_OFF); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MIPI_CTRL_OFF); sc635hai->is_standby = true; /* pwnd gpio pull down */ @@ -1912,20 +1912,20 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) } else { /* software standby */ if (stream) { ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_MIPI_CTRL, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MIPI_CTRL_ON); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MIPI_CTRL_ON); ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MODE_STREAMING); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MODE_STREAMING); dev_info(&sc635hai->client->dev, "quickstream, streaming on: exit soft standby mode\n"); } else { ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MODE_SW_STANDBY); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MODE_SW_STANDBY); ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_MIPI_CTRL, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_MIPI_CTRL_OFF); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_MIPI_CTRL_OFF); dev_info(&sc635hai->client->dev, "quickstream, streaming off: enter soft standby mode\n"); } @@ -1946,7 +1946,7 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) #ifdef CONFIG_COMPAT static long sc635hai_compat_ioctl32(struct v4l2_subdev *sd, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { void __user *up = compat_ptr(arg); struct rkmodule_inf *inf; @@ -2072,7 +2072,7 @@ static int __sc635hai_start_stream(struct sc635hai *sc635hai) return ret; if (sc635hai->has_init_exp && sc635hai->cur_mode->hdr_mode != NO_HDR) { ret = sc635hai_ioctl(&sc635hai->subdev, PREISP_CMD_SET_HDRAE_EXP, - &sc635hai->init_hdrae_exp); + &sc635hai->init_hdrae_exp); if (ret) { dev_err(&sc635hai->client->dev, "init exp fail in hdr mode\n"); @@ -2091,7 +2091,7 @@ static int __sc635hai_stop_stream(struct sc635hai *sc635hai) if (sc635hai->is_thunderboot) sc635hai->is_first_streamoff = true; return sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, SC635HAI_MODE_SW_STANDBY); + SC635HAI_REG_VALUE_08BIT, SC635HAI_MODE_SW_STANDBY); } /* Calculate the delay in us by clock rate and clock cycles */ @@ -2252,7 +2252,7 @@ static int sc635hai_s_power(struct v4l2_subdev *sd, int on) if (!sc635hai->is_thunderboot) { ret = sc635hai_write_array(sc635hai->client, - sc635hai->cur_mode->global_reg_list); + sc635hai->cur_mode->global_reg_list); if (ret) { v4l2_err(sd, "could not set init registers\n"); pm_runtime_put_noidle(&client->dev); @@ -2294,7 +2294,7 @@ static int __maybe_unused sc635hai_resume(struct device *dev) if (sc635hai->has_init_exp && sc635hai->cur_mode != NO_HDR) { // hdr mode ret = sc635hai_ioctl(&sc635hai->subdev, PREISP_CMD_SET_HDRAE_EXP, - &sc635hai->cam_sw_inf->hdr_ae); + &sc635hai->cam_sw_inf->hdr_ae); if (ret) { dev_err(&sc635hai->client->dev, "set exp fail in hdr mode\n"); return ret; @@ -2370,8 +2370,8 @@ static int sc635hai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) #endif static int sc635hai_enum_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_frame_interval_enum *fie) + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) { struct sc635hai *sc635hai = to_sc635hai(sd); @@ -2434,13 +2434,13 @@ static void sc635hai_modify_fps_info(struct sc635hai *sc635hai) const struct sc635hai_mode *mode = sc635hai->cur_mode; sc635hai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / - sc635hai->cur_vts; + sc635hai->cur_vts; } static int sc635hai_set_ctrl(struct v4l2_ctrl *ctrl) { struct sc635hai *sc635hai = container_of(ctrl->handler, - struct sc635hai, ctrl_handler); + struct sc635hai, ctrl_handler); struct i2c_client *client = sc635hai->client; s64 max; int ret = 0; @@ -2472,17 +2472,17 @@ static int sc635hai_set_ctrl(struct v4l2_ctrl *ctrl) if (sc635hai->cur_mode->hdr_mode == NO_HDR) { /* 4 least significant bits of expsoure are fractional part */ ret = sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_H, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_H(ctrl->val)); - ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_M, + SC635HAI_REG_EXPOSURE_H, SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_M(ctrl->val)); + SC635HAI_FETCH_EXP_H(ctrl->val)); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_EXPOSURE_L, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_EXP_L(ctrl->val)); + SC635HAI_REG_EXPOSURE_M, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_M(ctrl->val)); + ret |= sc635hai_write_reg(sc635hai->client, + SC635HAI_REG_EXPOSURE_L, + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_EXP_L(ctrl->val)); } break; case V4L2_CID_ANALOGUE_GAIN: @@ -2493,17 +2493,17 @@ static int sc635hai_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_VBLANK: dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); ret = sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_VTS_H, - SC635HAI_REG_VALUE_08BIT, - 0x00); - ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_VTS_M, + SC635HAI_REG_VTS_H, SC635HAI_REG_VALUE_08BIT, - (ctrl->val + sc635hai->cur_mode->height) >> 8); + 0x00); ret |= sc635hai_write_reg(sc635hai->client, - SC635HAI_REG_VTS_L, - SC635HAI_REG_VALUE_08BIT, - (ctrl->val + sc635hai->cur_mode->height) & 0xff); + SC635HAI_REG_VTS_M, + SC635HAI_REG_VALUE_08BIT, + (ctrl->val + sc635hai->cur_mode->height) >> 8); + ret |= sc635hai_write_reg(sc635hai->client, + SC635HAI_REG_VTS_L, + SC635HAI_REG_VALUE_08BIT, + (ctrl->val + sc635hai->cur_mode->height) & 0xff); sc635hai->cur_vts = ctrl->val + sc635hai->cur_mode->height; if (sc635hai->cur_vts != sc635hai->cur_mode->vts_def) sc635hai_modify_fps_info(sc635hai); @@ -2513,17 +2513,17 @@ static int sc635hai_set_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_HFLIP: ret = sc635hai_read_reg(sc635hai->client, SC635HAI_FLIP_MIRROR_REG, - SC635HAI_REG_VALUE_08BIT, &val); + SC635HAI_REG_VALUE_08BIT, &val); ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_FLIP_MIRROR_REG, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_MIRROR(val, ctrl->val)); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_MIRROR(val, ctrl->val)); break; case V4L2_CID_VFLIP: ret = sc635hai_read_reg(sc635hai->client, SC635HAI_FLIP_MIRROR_REG, - SC635HAI_REG_VALUE_08BIT, &val); + SC635HAI_REG_VALUE_08BIT, &val); ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_FLIP_MIRROR_REG, - SC635HAI_REG_VALUE_08BIT, - SC635HAI_FETCH_FLIP(val, ctrl->val)); + SC635HAI_REG_VALUE_08BIT, + SC635HAI_FETCH_FLIP(val, ctrl->val)); break; default: dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", @@ -2560,9 +2560,9 @@ static int sc635hai_initialize_controls(struct sc635hai *sc635hai) handler->lock = &sc635hai->mutex; sc635hai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, - V4L2_CID_LINK_FREQ, - ARRAY_SIZE(link_freq_menu_items) - 1, - 0, link_freq_menu_items); + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, + 0, link_freq_menu_items); if (sc635hai->link_freq) sc635hai->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; @@ -2572,45 +2572,45 @@ static int sc635hai_initialize_controls(struct sc635hai *sc635hai) mode->bpp * 2 * lanes; if (lanes == 2) { sc635hai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, - 0, PIXEL_RATE_WITH_540M_10BIT_2L, - 1, dst_pixel_rate); + 0, PIXEL_RATE_WITH_540M_10BIT_2L, + 1, dst_pixel_rate); } else if (lanes == 4) { if (mode->hdr_mode == NO_HDR) sc635hai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, - 0, PIXEL_RATE_WITH_540M_10BIT_4L, - 1, dst_pixel_rate); + 0, PIXEL_RATE_WITH_540M_10BIT_4L, + 1, dst_pixel_rate); else if (mode->hdr_mode == HDR_X2) sc635hai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, - 0, PIXEL_RATE_WITH_540M_10BIT_4L, - 1, dst_pixel_rate); + 0, PIXEL_RATE_WITH_540M_10BIT_4L, + 1, dst_pixel_rate); } __v4l2_ctrl_s_ctrl(sc635hai->link_freq, dst_link_freq); h_blank = mode->hts_def - mode->width; sc635hai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, - h_blank, h_blank, 1, h_blank); + h_blank, h_blank, 1, h_blank); if (sc635hai->hblank) sc635hai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; vblank_def = mode->vts_def - mode->height; sc635hai->vblank = v4l2_ctrl_new_std(handler, &sc635hai_ctrl_ops, - V4L2_CID_VBLANK, vblank_def, - SC635HAI_VTS_MAX - mode->height, - 1, vblank_def); + V4L2_CID_VBLANK, vblank_def, + SC635HAI_VTS_MAX - mode->height, + 1, vblank_def); exposure_max = mode->vts_def - 8; sc635hai->exposure = v4l2_ctrl_new_std(handler, &sc635hai_ctrl_ops, - V4L2_CID_EXPOSURE, SC635HAI_EXPOSURE_MIN, - exposure_max, SC635HAI_EXPOSURE_STEP, - mode->exp_def); //Set default exposure + V4L2_CID_EXPOSURE, SC635HAI_EXPOSURE_MIN, + exposure_max, SC635HAI_EXPOSURE_STEP, + mode->exp_def); //Set default exposure sc635hai->anal_gain = v4l2_ctrl_new_std(handler, &sc635hai_ctrl_ops, - V4L2_CID_ANALOGUE_GAIN, SC635HAI_GAIN_MIN, - SC635HAI_GAIN_MAX, SC635HAI_GAIN_STEP, - SC635HAI_GAIN_DEFAULT); //Set default gain + V4L2_CID_ANALOGUE_GAIN, SC635HAI_GAIN_MIN, + SC635HAI_GAIN_MAX, SC635HAI_GAIN_STEP, + SC635HAI_GAIN_DEFAULT); //Set default gain sc635hai->test_pattern = v4l2_ctrl_new_std_menu_items(handler, - &sc635hai_ctrl_ops, - V4L2_CID_TEST_PATTERN, - ARRAY_SIZE(sc635hai_test_pattern_menu) - 1, - 0, 0, sc635hai_test_pattern_menu); + &sc635hai_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(sc635hai_test_pattern_menu) - 1, + 0, 0, sc635hai_test_pattern_menu); v4l2_ctrl_new_std(handler, &sc635hai_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); v4l2_ctrl_new_std(handler, &sc635hai_ctrl_ops, @@ -2636,7 +2636,7 @@ err_free_handler: } static int sc635hai_check_sensor_id(struct sc635hai *sc635hai, - struct i2c_client *client) + struct i2c_client *client) { struct device *dev = &sc635hai->client->dev; u32 id = 0; @@ -2648,7 +2648,7 @@ static int sc635hai_check_sensor_id(struct sc635hai *sc635hai, } ret = sc635hai_read_reg(client, SC635HAI_REG_CHIP_ID, - SC635HAI_REG_VALUE_16BIT, &id); + SC635HAI_REG_VALUE_16BIT, &id); if (id != CHIP_ID) { dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); return -ENODEV; @@ -2725,7 +2725,7 @@ static int sc635hai_find_modes(struct sc635hai *sc635hai) } dev_info(dev, "Detect sc635hai lane: %d\n", - sc635hai->bus_cfg.bus.mipi_csi2.num_data_lanes); + sc635hai->bus_cfg.bus.mipi_csi2.num_data_lanes); if (sc635hai->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) { sc635hai->supported_modes = supported_modes_4lane; sc635hai->cfg_num = ARRAY_SIZE(supported_modes_4lane); @@ -2758,12 +2758,12 @@ static int sc635hai_setup_clocks_and_gpios(struct sc635hai *sc635hai) } sc635hai->reset_gpio = devm_gpiod_get(dev, "reset", - sc635hai->is_thunderboot ? GPIOD_ASIS : GPIOD_OUT_LOW); + sc635hai->is_thunderboot ? GPIOD_ASIS : GPIOD_OUT_LOW); if (IS_ERR(sc635hai->reset_gpio)) dev_warn(dev, "Failed to get reset-gpios\n"); sc635hai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", - sc635hai->is_thunderboot ? GPIOD_ASIS : GPIOD_OUT_LOW); + sc635hai->is_thunderboot ? GPIOD_ASIS : GPIOD_OUT_LOW); if (IS_ERR(sc635hai->pwdn_gpio)) dev_warn(dev, "Failed to get pwdn-gpios\n"); @@ -2788,7 +2788,7 @@ static int sc635hai_setup_clocks_and_gpios(struct sc635hai *sc635hai) } static int sc635hai_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct device *dev = &client->dev; struct sc635hai *sc635hai; From 8102cff13b8fbd36b4a7981a7e45664990574399 Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Fri, 15 Aug 2025 17:40:19 +0800 Subject: [PATCH 07/14] arm64: dts: rockchip: add rv1126b-evb2-v12.dts Signed-off-by: Jkand Huang Change-Id: Icd714daf4f2f016a22de0be706c49a78ae0de70f --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rv1126b-evb2-v12.dts | 35 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rv1126b-evb2-v12.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b8205753db22..c757d718a7ac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-dv.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v12.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-iotest-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v12.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v12.dts new file mode 100644 index 000000000000..a4c35728b027 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v12.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126b-evb2-v10.dts" + +/ { + model = "Rockchip RV1126B EVB2 V12 Board"; + compatible = "rockchip,rv1126b-evb2-v12", "rockchip,rv1126b"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + mmc-hs200-1_8v; + rockchip,default-sample-phase = <90>; + no-sdio; + no-sd; + status = "okay"; +}; + +&fspi0 { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; From b89a90f1e7f583e4408818542511d9201ea3d523 Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Fri, 15 Aug 2025 17:46:08 +0800 Subject: [PATCH 08/14] ARM: dts: rockchip: add rv1126b-evb2-v12.dts Signed-off-by: Jkand Huang Change-Id: I47d836591258eed1b1785e5d3bc14638ed957ebb --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rv1126b-evb2-v12.dts | 6 ++++++ 2 files changed, 7 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126b-evb2-v12.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aeaf80fab463..2022c7096cef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1198,6 +1198,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb \ rv1126b-evb2-v10-tb-400w-emmc.dtb \ rv1126b-evb2-v10-tb-400w-spi-nor.dtb \ + rv1126b-evb2-v12.dtb \ rv1126b-evb2-v12-aov-dual-cam.dtb \ rv1126b-evb3-v10.dtb \ rv1126b-evb4-v10.dtb \ diff --git a/arch/arm/boot/dts/rv1126b-evb2-v12.dts b/arch/arm/boot/dts/rv1126b-evb2-v12.dts new file mode 100644 index 000000000000..10b09a81a895 --- /dev/null +++ b/arch/arm/boot/dts/rv1126b-evb2-v12.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rv1126b-evb2-v12.dts" From 20b16eb9194c6dcaef5da731fc2bae5f7e435138 Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Sat, 16 Aug 2025 09:55:07 +0800 Subject: [PATCH 09/14] ARM: configs: rv1126b-ipc: Enable CONFIG_EXT4_FS Signed-off-by: Jkand Huang Change-Id: I2a4b2653e4cdd84972ce810c3c77459e421c311b --- arch/arm/configs/rv1126b-ipc.config | 115 ++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm/configs/rv1126b-ipc.config b/arch/arm/configs/rv1126b-ipc.config index 80900a2ccda4..1a8136bda6aa 100644 --- a/arch/arm/configs/rv1126b-ipc.config +++ b/arch/arm/configs/rv1126b-ipc.config @@ -1,3 +1,6 @@ +CONFIG_CRC16=y +CONFIG_CRYPTO=y +CONFIG_EXT4_FS=y CONFIG_JFFS2_FS=y CONFIG_MMC=y CONFIG_MSDOS_PARTITION=y @@ -85,16 +88,124 @@ CONFIG_VIDEO_SC850SL=m # CONFIG_BMI088_ACCEL is not set # CONFIG_BMI160_SPI is not set # CONFIG_BSD_DISKLABEL is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ARIA is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S_ARM is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_HCTR2 is not set +# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_ARM is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA256_ARM is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA512_ARM is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_ZSTD is not set # CONFIG_DM9051 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_AT25 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_USE_FOR_EXT2=y # CONFIG_EZX_PCAP is not set CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_FAT_FS=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y # CONFIG_FXLS8962AF_SPI is not set # CONFIG_FXOS8700_SPI is not set # CONFIG_GPIO_74X164 is not set @@ -108,6 +219,8 @@ CONFIG_FAT_FS=y # CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_ICM42670_SPI is not set # CONFIG_INV_MPU6050_SPI is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y @@ -322,6 +435,8 @@ CONFIG_SPI_ROCKCHIP_SFC=y # CONFIG_TI_TSC2046 is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_MS41908 is not set +# CONFIG_VIDEO_MS41968 is not set # CONFIG_VIDEO_ROCKCHIP_PREISP is not set # CONFIG_VIDEO_S5C73M3 is not set CONFIG_ZLIB_DEFLATE=y From 140ea84b907d711b051a003a82b83c36bfc7fd8c Mon Sep 17 00:00:00 2001 From: Jkand Huang Date: Sat, 16 Aug 2025 10:10:23 +0800 Subject: [PATCH 10/14] ARM: configs: rv1126b-ipc: Enable CONFIG_BLK_DEV_INITRD Signed-off-by: Jkand Huang Change-Id: Idda6d0e3a9e3325479a814dd786d508ac65cc858 --- arch/arm/configs/rv1126b-ipc.config | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/configs/rv1126b-ipc.config b/arch/arm/configs/rv1126b-ipc.config index 1a8136bda6aa..cf7e9d9fe42f 100644 --- a/arch/arm/configs/rv1126b-ipc.config +++ b/arch/arm/configs/rv1126b-ipc.config @@ -1,3 +1,4 @@ +CONFIG_BLK_DEV_INITRD=y CONFIG_CRC16=y CONFIG_CRYPTO=y CONFIG_EXT4_FS=y @@ -190,6 +191,7 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_XXHASH is not set # CONFIG_CRYPTO_ZSTD is not set +CONFIG_DECOMPRESS_GZIP=y # CONFIG_DM9051 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_AT25 is not set @@ -216,6 +218,8 @@ CONFIG_FS_MBCACHE=y # CONFIG_GPIO_XRA1403 is not set # CONFIG_HI8435 is not set # CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_INITRAMFS_FORCE is not set +CONFIG_INITRAMFS_SOURCE="" # CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_ICM42670_SPI is not set # CONFIG_INV_MPU6050_SPI is not set @@ -333,6 +337,13 @@ CONFIG_NET_VENDOR_ADI=y # CONFIG_PWRSEQ_EMMC is not set # CONFIG_PWRSEQ_SIMPLE is not set # CONFIG_QCA7000_SPI is not set +# CONFIG_RD_BZIP2 is not set +CONFIG_RD_GZIP=y +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_ZSTD is not set CONFIG_REGMAP_SPI=y # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set From e3b0712bc56410c945c450be57e7e06087764630 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Mon, 18 Aug 2025 17:27:42 +0800 Subject: [PATCH 11/14] drm/rockchip: dw_hdmi: Fix the error in the judgment condition for the dsc 1/3 compression rate Fixes: dbcc3c130c50 ("drm/rockchip: dw_hdmi: Do not enable DSC when the DSC compression ratio is below 0.375.") Change-Id: Ib94677b9e0588a944feb5e5506eaa9dcbf96bf35 Signed-off-by: Algea Cao --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index dd2aa4004cf5..e34174fa19c5 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -1051,7 +1051,7 @@ static bool rockchip_hdmi_check_dsc_rate_supported(struct rockchip_hdmi *hdmi, /* compression ratio needs to be greater than 0.375. */ dsc_rate = DIV_ROUND_UP_ULL(data_rate * 9, 24); - if ((data_rate > frl_rate) && (dsc_rate > dsc_frl_rate)) + if ((data_rate > frl_rate) && (dsc_rate < dsc_frl_rate)) return true; return false; From 80afdafe540bad89b1c9fd6d60bc916b8306c8b4 Mon Sep 17 00:00:00 2001 From: LongChang Ma Date: Sat, 16 Aug 2025 15:10:09 +0800 Subject: [PATCH 12/14] media: i2c: add support sc635hai sync mode Signed-off-by: LongChang Ma Change-Id: Id27d5d230553664cce978fd9920c04a804811233 --- drivers/media/i2c/sc635hai.c | 91 ++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/sc635hai.c b/drivers/media/i2c/sc635hai.c index 1bca634be43c..b8da0310042c 100644 --- a/drivers/media/i2c/sc635hai.c +++ b/drivers/media/i2c/sc635hai.c @@ -222,10 +222,36 @@ struct sc635hai { struct cam_sw_info *cam_sw_inf; struct v4l2_fwnode_endpoint bus_cfg; struct rk_light_param light_param; + enum rkmodule_sync_mode sync_mode; }; #define to_sc635hai(sd) container_of(sd, struct sc635hai, subdev) +/* sync mode regs*/ +static __maybe_unused const struct regval sc635hai_interal_sync_master_start_regs[] = { + {0x3222, 0x00}, //Slave mode en,0: master mode;1:slave mode + {0x300a, 0x24}, //Bit[2]: FSYNC output en; FSYNC as output PAD + {0x3032, 0xb0}, + {REG_NULL, 0x00}, +}; + +static __maybe_unused const struct regval sc635hai_interal_sync_master_stop_regs[] = { + {REG_NULL, 0x00}, +}; + +static __maybe_unused const struct regval sc635hai_interal_sync_slave_start_regs[] = { + {0x3222, 0x01}, //Slave mode en,0: master mode;1:slave mode + {0x3224, 0xd2}, //trigger by fync + {0x3230, 0x00}, //Rows Before Read + {0x3231, 0x04}, //Rows Before Read + {0x300a, 0x60}, //Bit[6]: EFSYNC output en; EFSYNC as input PAD + {REG_NULL, 0x00}, +}; + +static __maybe_unused const struct regval sc635hai_interal_sync_slave_stop_regs[] = { + {REG_NULL, 0x00}, +}; + /* * Xclk 24Mhz */ @@ -1782,6 +1808,7 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) int cur_best_fit = -1; int cur_best_fit_dist = -1; int cur_dist, cur_fps, dst_fps; + u32 *sync_mode = NULL; switch (cmd) { case RKMODULE_GET_MODULE_INFO: @@ -1935,6 +1962,21 @@ static long sc635hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) setting = (struct rk_sensor_setting *)arg; ret = sc635hai_set_setting(sc635hai, setting); break; + case RKMODULE_GET_SYNC_MODE: + sync_mode = (u32 *)arg; + *sync_mode = sc635hai->sync_mode; + break; + case RKMODULE_SET_SYNC_MODE: + sync_mode = (u32 *)arg; + if (sync_mode) { + sc635hai->sync_mode = *sync_mode; + dev_info(&sc635hai->client->dev, "set sync mode is: %s\n", + ((*sync_mode == EXTERNAL_MASTER_MODE) || + (*sync_mode == SLAVE_MODE)) ? "secondary" : "primary"); + } else { + dev_info(&sc635hai->client->dev, "set sync mode is: NO_SYNC_MODE\n"); + } + break; default: ret = -ENOIOCTLCMD; break; @@ -1956,6 +1998,7 @@ static long sc635hai_compat_ioctl32(struct v4l2_subdev *sd, struct rk_light_param *light_param; long ret; u32 stream = 0; + u32 *sync_mode = NULL; switch (cmd) { case RKMODULE_GET_MODULE_INFO: @@ -2035,6 +2078,21 @@ static long sc635hai_compat_ioctl32(struct v4l2_subdev *sd, ret = -EFAULT; kfree(setting); break; + case RKMODULE_GET_SYNC_MODE: + ret = sc635hai_ioctl(sd, cmd, &sync_mode); + if (!ret) { + ret = copy_to_user(up, &sync_mode, sizeof(u32)); + if (ret) + ret = -EFAULT; + } + break; + case RKMODULE_SET_SYNC_MODE: + ret = copy_from_user(&sync_mode, up, sizeof(u32)); + if (!ret) + ret = sc635hai_ioctl(sd, cmd, &sync_mode); + else + ret = -EFAULT; + break; case RKCIS_CMD_FLASH_LIGHT_CTRL: light_param = kzalloc(sizeof(*light_param), GFP_KERNEL); if (!light_param) { @@ -2060,7 +2118,7 @@ static long sc635hai_compat_ioctl32(struct v4l2_subdev *sd, static int __sc635hai_start_stream(struct sc635hai *sc635hai) { - int ret; + int ret = 0; if (!sc635hai->is_thunderboot) { ret = sc635hai_write_array(sc635hai->client, sc635hai->cur_mode->reg_list); @@ -2080,8 +2138,15 @@ static int __sc635hai_start_stream(struct sc635hai *sc635hai) } } } - ret = sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, - SC635HAI_REG_VALUE_08BIT, SC635HAI_MODE_STREAMING); + if (sc635hai->sync_mode == INTERNAL_MASTER_MODE) + ret |= sc635hai_write_array(sc635hai->client, + sc635hai_interal_sync_master_start_regs); + else if (sc635hai->sync_mode == EXTERNAL_MASTER_MODE) + ret |= sc635hai_write_array(sc635hai->client, + sc635hai_interal_sync_slave_start_regs); + else if (sc635hai->sync_mode == NO_SYNC_MODE) + ret |= sc635hai_write_reg(sc635hai->client, SC635HAI_REG_CTRL_MODE, + SC635HAI_REG_VALUE_08BIT, SC635HAI_MODE_STREAMING); return ret; } @@ -2676,6 +2741,7 @@ static int sc635hai_read_module_info(struct sc635hai *sc635hai) int ret; struct device *dev = &sc635hai->client->dev; struct device_node *node = dev->of_node; + const char *sync_mode_name = NULL; ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, &sc635hai->module_index); @@ -2693,6 +2759,25 @@ static int sc635hai_read_module_info(struct sc635hai *sc635hai) &sc635hai->standby_hw); dev_info(dev, "sc635hai->standby_hw = %d\n", sc635hai->standby_hw); + ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE, + &sync_mode_name); + if (ret) { + sc635hai->sync_mode = NO_SYNC_MODE; + dev_err(dev, "could not get sync mode!\n"); + } else { + if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0) { + sc635hai->sync_mode = EXTERNAL_MASTER_MODE; + dev_info(dev, "sync_mode= [EXTERNAL_MASTER_MODE]\n"); + } else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0) { + sc635hai->sync_mode = INTERNAL_MASTER_MODE; + dev_info(dev, "sync_mode= [INTERNAL_MASTER_MODE]\n"); + } else if (strcmp(sync_mode_name, RKMODULE_SOFT_SYNC_MODE) == 0) { + sc635hai->sync_mode = SOFT_SYNC_MODE; + dev_info(dev, "sync_mode= [SOFT_SYNC_MODE]\n"); + } else { + dev_info(dev, "sync_mode= [NO_SYNC_MODE]\n"); + } + } return ret; } From 33f3c216294cb446fc7e06061ee7c230592f723a Mon Sep 17 00:00:00 2001 From: LongChang Ma Date: Sat, 16 Aug 2025 16:41:08 +0800 Subject: [PATCH 13/14] media: i2c: add support sc235hai sensor driver Signed-off-by: LongChang Ma Change-Id: Ia8d63407bd770d625c0cc0513b78096a5d1c9a1e --- drivers/media/i2c/Kconfig | 10 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/sc235hai.c | 2261 ++++++++++++++++++++++++++++++++++ 3 files changed, 2272 insertions(+) create mode 100644 drivers/media/i2c/sc235hai.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index fd0602b82cd1..6038383257a3 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1999,6 +1999,16 @@ config VIDEO_SC2355 To compile this driver as a module, choose M here: the module will be called sc2355. +config VIDEO_SC235HAI + tristate "SmartSens SC235HAI sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the SmartSens + SC235HAI camera. + config VIDEO_SC301IOT tristate "SmartSens SC301IOT sensor support" depends on I2C && VIDEO_DEV diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index ef52d805886d..30b3d29eda2e 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -247,6 +247,7 @@ obj-$(CONFIG_VIDEO_SC230AI) += sc230ai.o obj-$(CONFIG_VIDEO_SC2310) += sc2310.o obj-$(CONFIG_VIDEO_SC2336) += sc2336.o obj-$(CONFIG_VIDEO_SC2355) += sc2355.o +obj-$(CONFIG_VIDEO_SC235HAI) += sc235hai.o obj-$(CONFIG_VIDEO_SC301IOT) += sc301iot.o obj-$(CONFIG_VIDEO_SC3336) += sc3336.o obj-$(CONFIG_VIDEO_SC3336P) += sc3336p.o diff --git a/drivers/media/i2c/sc235hai.c b/drivers/media/i2c/sc235hai.c new file mode 100644 index 000000000000..f632526cc6df --- /dev/null +++ b/drivers/media/i2c/sc235hai.c @@ -0,0 +1,2261 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sc235hai driver + * + * Copyright (C) 2024 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first implement. + * V0.0X01.0X02 add soft sync mode. + * V0.0X01.0X03 add support wake-up/sleep(aov) mode. + * + */ + +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" +#include "cam-sleep-wakeup.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x03) + +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define SC235HAI_LANES 2 +#define SC235HAI_BITS_PER_SAMPLE 10 +#define SC235HAI_LINK_FREQ_371 371250000// 742.5Mbps + +#define PIXEL_RATE_WITH_371M_10BIT (SC235HAI_LINK_FREQ_371 * 2 * \ + SC235HAI_LANES / SC235HAI_BITS_PER_SAMPLE) + +#define SC235HAI_XVCLK_FREQ 27000000 + +#define CHIP_ID 0xcb6a +#define SC235HAI_REG_CHIP_ID 0x3107 + +#define SC235HAI_REG_CTRL_MODE 0x0100 +#define SC235HAI_MODE_SW_STANDBY 0x0 +#define SC235HAI_MODE_STREAMING BIT(0) + +#define SC235HAI_REG_MIPI_CTRL 0x3019 +#define SC235HAI_MIPI_CTRL_ON 0x0c +#define SC235HAI_MIPI_CTRL_OFF 0x0f + +#define SC235HAI_REG_EXPOSURE_H 0x3e00 +#define SC235HAI_REG_EXPOSURE_M 0x3e01 +#define SC235HAI_REG_EXPOSURE_L 0x3e02 +#define SC235HAI_REG_SEXPOSURE_H 0x3e22 +#define SC235HAI_REG_SEXPOSURE_M 0x3e04 +#define SC235HAI_REG_SEXPOSURE_L 0x3e05 +#define SC235HAI_EXPOSURE_MIN 1 +#define SC235HAI_EXPOSURE_STEP 1 +#define SC235HAI_VTS_MAX 0x7fff + +#define SC235HAI_REG_DIG_GAIN 0x3e06 +#define SC235HAI_REG_DIG_FINE_GAIN 0x3e07 +#define SC235HAI_REG_ANA_GAIN 0x3e08 +#define SC235HAI_REG_ANA_FINE_GAIN 0x3e09 + +#define SC235HAI_REG_SDIG_GAIN 0x3e10 +#define SC235HAI_REG_SDIG_FINE_GAIN 0x3e11 +#define SC235HAI_REG_SANA_GAIN 0x3e12 +#define SC235HAI_REG_SANA_FINE_GAIN 0x3e13 +#define SC235HAI_REG_MAX_SEXPOSURE_H 0x3e23 +#define SC235HAI_REG_MAX_SEXPOSURE_L 0x3e24 + +#define SC235HAI_GAIN_MIN 0x20 +#define SC235HAI_GAIN_MAX (117 * 16 * 32) // 116.55*15.875*32 +#define SC235HAI_GAIN_STEP 1 +#define SC235HAI_GAIN_DEFAULT 0x40 +#define SC235HAI_LGAIN 0 +#define SC235HAI_SGAIN 1 + +#define SC235HAI_REG_GROUP_HOLD 0x3812 +#define SC235HAI_GROUP_HOLD_START 0x00 +#define SC235HAI_GROUP_HOLD_END 0x30 + +#define SC235HAI_REG_HIGH_TEMP_H 0x3974 +#define SC235HAI_REG_HIGH_TEMP_L 0x3975 + +#define SC235HAI_REG_TEST_PATTERN 0x4501 +#define SC235HAI_TEST_PATTERN_BIT_MASK BIT(3) + +#define SC235HAI_REG_VTS_H 0x320e +#define SC235HAI_REG_VTS_L 0x320f + +#define SC235HAI_FLIP_MIRROR_REG 0x3221 + +#define SC235HAI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF) +#define SC235HAI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF) +#define SC235HAI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4) + +#define SC235HAI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03) +#define SC235HAI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF) + +#define SC235HAI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9) +#define SC235HAI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f) + +#define REG_DELAY 0xFFFE +#define REG_NULL 0xFFFF + +#define SC235HAI_REG_VALUE_08BIT 1 +#define SC235HAI_REG_VALUE_16BIT 2 +#define SC235HAI_REG_VALUE_24BIT 3 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" +#define SC235HAI_NAME "sc235hai" + +static const char *const sc235hai_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define SC235HAI_NUM_SUPPLIES ARRAY_SIZE(sc235hai_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct sc235hai_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 mipi_freq_idx; + u32 bpp; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct sc235hai { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[SC235HAI_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *test_pattern; + struct mutex mutex; + struct v4l2_fract cur_fps; + bool streaming; + bool power_on; + const struct sc235hai_mode *cur_mode; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + enum rkmodule_sync_mode sync_mode; + u32 cur_vts; + bool has_init_exp; + bool is_thunderboot; + bool is_first_streamoff; + u32 standby_hw; + bool is_standby; + struct preisp_hdrae_exp_s init_hdrae_exp; + struct cam_sw_info *cam_sw_info; +}; + +#define to_sc235hai(sd) container_of(sd, struct sc235hai, subdev) + +/* + * Xclk 27Mhz + */ +static const struct regval sc235hai_global_regs[] = { + {REG_NULL, 0x00}, +}; + +static __maybe_unused const struct regval sc235hai_linear_10_640x480_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x301f, 0x2d}, + {0x3200, 0x00}, + {0x3201, 0x00}, + {0x3202, 0x00}, + {0x3203, 0x3c}, + {0x3204, 0x07}, + {0x3205, 0x87}, + {0x3206, 0x04}, + {0x3207, 0x03}, + {0x3208, 0x02}, + {0x3209, 0x80}, + {0x320a, 0x01}, + {0x320b, 0xe0}, + {0x320e, 0x02}, + {0x320f, 0x32}, + {0x3210, 0x00}, + {0x3211, 0xa2}, + {0x3212, 0x00}, + {0x3213, 0x02}, + {0x3215, 0x31}, + {0x3220, 0x01}, + {0x3301, 0x09}, + {0x3304, 0x50}, + {0x3306, 0x48}, + {0x3308, 0x18}, + {0x3309, 0x68}, + {0x330a, 0x00}, + {0x330b, 0xc0}, + {0x331e, 0x41}, + {0x331f, 0x59}, + {0x3333, 0x10}, + {0x3334, 0x40}, + {0x335d, 0x60}, + {0x335e, 0x06}, + {0x335f, 0x08}, + {0x3364, 0x5e}, + {0x337c, 0x02}, + {0x337d, 0x0a}, + {0x3390, 0x01}, + {0x3391, 0x0b}, + {0x3392, 0x0f}, + {0x3393, 0x0c}, + {0x3394, 0x0d}, + {0x3395, 0x60}, + {0x3396, 0x48}, + {0x3397, 0x49}, + {0x3398, 0x4f}, + {0x3399, 0x0a}, + {0x339a, 0x0f}, + {0x339b, 0x14}, + {0x339c, 0x60}, + {0x33a2, 0x04}, + {0x33af, 0x40}, + {0x33b1, 0x80}, + {0x33b3, 0x40}, + {0x33b9, 0x0a}, + {0x33f9, 0x70}, + {0x33fb, 0x90}, + {0x33fc, 0x4b}, + {0x33fd, 0x5f}, + {0x349f, 0x03}, + {0x34a6, 0x4b}, + {0x34a7, 0x4f}, + {0x34a8, 0x30}, + {0x34a9, 0x20}, + {0x34aa, 0x00}, + {0x34ab, 0xe0}, + {0x34ac, 0x01}, + {0x34ad, 0x00}, + {0x34f8, 0x5f}, + {0x34f9, 0x10}, + {0x3630, 0xc0}, + {0x3633, 0x44}, + {0x3637, 0x29}, + {0x363b, 0x20}, + {0x3670, 0x09}, + {0x3674, 0xb0}, + {0x3675, 0x80}, + {0x3676, 0x88}, + {0x367c, 0x40}, + {0x367d, 0x49}, + {0x3690, 0x44}, + {0x3691, 0x44}, + {0x3692, 0x54}, + {0x369c, 0x49}, + {0x369d, 0x4f}, + {0x36ae, 0x4b}, + {0x36af, 0x4f}, + {0x36b0, 0x87}, + {0x36b1, 0x9b}, + {0x36b2, 0xb7}, + {0x36d0, 0x01}, + {0x36ea, 0x0b}, + {0x36eb, 0x04}, + {0x36ec, 0x1c}, + {0x36ed, 0x24}, + {0x370f, 0x01}, + {0x3722, 0x17}, + {0x3728, 0x90}, + {0x37b0, 0x17}, + {0x37b1, 0x17}, + {0x37b2, 0x97}, + {0x37b3, 0x4b}, + {0x37b4, 0x4f}, + {0x37fa, 0x0b}, + {0x37fb, 0x24}, + {0x37fc, 0x10}, + {0x37fd, 0x22}, + {0x3901, 0x02}, + {0x3902, 0xc5}, + {0x3904, 0x04}, + {0x3907, 0x00}, + {0x3908, 0x41}, + {0x3909, 0x00}, + {0x390a, 0x00}, + {0x391f, 0x04}, + {0x3933, 0x84}, + {0x3934, 0x02}, + {0x3940, 0x62}, + {0x3941, 0x00}, + {0x3942, 0x04}, + {0x3943, 0x03}, + {0x3e00, 0x00}, + {0x3e01, 0x45}, + {0x3e02, 0xb0}, + {0x440e, 0x02}, + {0x450d, 0x11}, + {0x4819, 0x05}, + {0x481b, 0x03}, + {0x481d, 0x0a}, + {0x481f, 0x02}, + {0x4821, 0x08}, + {0x4823, 0x03}, + {0x4825, 0x02}, + {0x4827, 0x03}, + {0x4829, 0x04}, + {0x5000, 0x46}, + {0x5010, 0x01}, + {0x5787, 0x08}, + {0x5788, 0x03}, + {0x5789, 0x00}, + {0x578a, 0x10}, + {0x578b, 0x08}, + {0x578c, 0x00}, + {0x5790, 0x08}, + {0x5791, 0x04}, + {0x5792, 0x00}, + {0x5793, 0x10}, + {0x5794, 0x08}, + {0x5795, 0x00}, + {0x5799, 0x06}, + {0x57ad, 0x00}, + {0x5900, 0xf1}, + {0x5901, 0x04}, + {0x5ae0, 0xfe}, + {0x5ae1, 0x40}, + {0x5ae2, 0x3f}, + {0x5ae3, 0x38}, + {0x5ae4, 0x28}, + {0x5ae5, 0x3f}, + {0x5ae6, 0x38}, + {0x5ae7, 0x28}, + {0x5ae8, 0x3f}, + {0x5ae9, 0x3c}, + {0x5aea, 0x2c}, + {0x5aeb, 0x3f}, + {0x5aec, 0x3c}, + {0x5aed, 0x2c}, + {0x5af4, 0x3f}, + {0x5af5, 0x38}, + {0x5af6, 0x28}, + {0x5af7, 0x3f}, + {0x5af8, 0x38}, + {0x5af9, 0x28}, + {0x5afa, 0x3f}, + {0x5afb, 0x3c}, + {0x5afc, 0x2c}, + {0x5afd, 0x3f}, + {0x5afe, 0x3c}, + {0x5aff, 0x2c}, + {0x36e9, 0x20}, + {0x37f9, 0x24}, + {REG_NULL, 0x00}, +}; + +/* + * Xclk 27Mhz + * max_framerate 60fps + * mipi_datarate per lane 371.25Mbps, 2lane + */ +static const struct regval sc235hai_linear_10_1920x1080_60fps_regs[] = { + {0x0103, 0x01}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x301f, 0x02}, + {0x3058, 0x21}, + {0x3059, 0x53}, + {0x305a, 0x40}, + {0x3250, 0x00}, + {0x3301, 0x0a}, + {0x3302, 0x20}, + {0x3304, 0x90}, + {0x3305, 0x00}, + {0x3306, 0x78}, + {0x3309, 0xd0}, + {0x330b, 0xe8}, + {0x330d, 0x08}, + {0x331c, 0x04}, + {0x331e, 0x81}, + {0x331f, 0xc1}, + {0x3323, 0x06}, + {0x3333, 0x10}, + {0x3334, 0x40}, + {0x3364, 0x5e}, + {0x336c, 0x8c}, + {0x337f, 0x13}, + {0x338f, 0x80}, + {0x3390, 0x08}, + {0x3391, 0x18}, + {0x3392, 0xb8}, + {0x3393, 0x0e}, + {0x3394, 0x14}, + {0x3395, 0x10}, + {0x3396, 0x88}, + {0x3397, 0x98}, + {0x3398, 0xf8}, + {0x3399, 0x0a}, + {0x339a, 0x0e}, + {0x339b, 0x10}, + {0x339c, 0x14}, + {0x33ae, 0x80}, + {0x33af, 0xc0}, + {0x33b2, 0x50}, + {0x33b3, 0x08}, + {0x33f8, 0x00}, + {0x33f9, 0x78}, + {0x33fa, 0x00}, + {0x33fb, 0x78}, + {0x33fc, 0x48}, + {0x33fd, 0x78}, + {0x349f, 0x03}, + {0x34a6, 0x40}, + {0x34a7, 0x58}, + {0x34a8, 0x08}, + {0x34a9, 0x0c}, + {0x34f8, 0x78}, + {0x34f9, 0x18}, + {0x3619, 0x20}, + {0x361a, 0x90}, + {0x3633, 0x44}, + {0x3637, 0x5c}, + {0x363c, 0xc0}, + {0x363d, 0x02}, + {0x3660, 0x80}, + {0x3661, 0x81}, + {0x3662, 0x8f}, + {0x3663, 0x81}, + {0x3664, 0x81}, + {0x3665, 0x82}, + {0x3666, 0x8f}, + {0x3667, 0x08}, + {0x3668, 0x80}, + {0x3669, 0x88}, + {0x366a, 0x98}, + {0x366b, 0xb8}, + {0x366c, 0xf8}, + {0x3670, 0xc2}, + {0x3671, 0xc2}, + {0x3672, 0x98}, + {0x3680, 0x43}, + {0x3681, 0x54}, + {0x3682, 0x54}, + {0x36c0, 0x80}, + {0x36c1, 0x88}, + {0x36c8, 0x88}, + {0x36c9, 0xb8}, + {0x3718, 0x04}, + {0x3722, 0x8b}, + {0x3724, 0xd1}, + {0x3741, 0x08}, + {0x3770, 0x17}, + {0x3771, 0x9b}, + {0x3772, 0x9b}, + {0x37c0, 0x88}, + {0x37c1, 0xb8}, + {0x3902, 0xc0}, + {0x3903, 0x40}, + {0x3909, 0x00}, + {0x391f, 0x41}, + {0x3926, 0xe0}, + {0x3933, 0x80}, + {0x3934, 0x02}, + {0x3937, 0x6f}, + {0x3e00, 0x00}, + {0x3e01, 0x8b}, + {0x3e02, 0xf0}, + {0x3e08, 0x00}, + {0x4509, 0x20}, + {0x450d, 0x07}, + {0x5780, 0x76}, + {0x5784, 0x10}, + {0x5787, 0x0a}, + {0x5788, 0x0a}, + {0x5789, 0x08}, + {0x578a, 0x0a}, + {0x578b, 0x0a}, + {0x578c, 0x08}, + {0x578d, 0x40}, + {0x5792, 0x04}, + {0x5795, 0x04}, + {0x57ac, 0x00}, + {0x57ad, 0x00}, + {0x36e9, 0x24}, + {0x37f9, 0x24}, + //{0x0100, 0x01}, + {REG_NULL, 0x00}, +}; + + +static const struct sc235hai_mode supported_modes[] = { + { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .exp_def = 0x0460, + .hts_def = 0x44C * 2, + .vts_def = 0x0465, + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .reg_list = sc235hai_linear_10_1920x1080_60fps_regs, + .hdr_mode = NO_HDR, + .bpp = 10, + .mipi_freq_idx = 0, + .vc[PAD0] = 0, + }, +}; + +static const u32 bus_code[] = { + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + +static const s64 link_freq_menu_items[] = { + SC235HAI_LINK_FREQ_371 +}; + +static const char *const sc235hai_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +/* Write registers up to 4 at a time */ +static int sc235hai_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int sc235hai_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) + ret = sc235hai_write_reg(client, regs[i].addr, + SC235HAI_REG_VALUE_08BIT, regs[i].val); + + return ret; +} + +/* Read registers up to 4 at a time */ +static int sc235hai_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +/* mode: 0 = lgain 1 = sgain */ +static int sc235hai_set_gain_reg(struct sc235hai *sc235hai, u32 total_gain, int mode) +{ + u8 Coarse_gain = 1, DIG_gain = 1; + u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1; + u8 Coarse_gain_reg = 0, DIG_gain_reg = 0; + u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80; + int ret = 0; + + total_gain = total_gain * 32; + if (total_gain < SC235HAI_GAIN_MIN * 32) + total_gain = SC235HAI_GAIN_MIN; + else if (total_gain > SC235HAI_GAIN_MAX * 32) + total_gain = SC235HAI_GAIN_MAX * 32; + + if (total_gain < 2 * 1024) { /* Start again 1.0x ~ 2.0x */ + Dcg_gainx100 = 100; + Coarse_gain = 1; DIG_gain = 1; + Coarse_gain_reg = 0x00; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 3788) { /* 2.0x ~ 3.7x 1024 * 3.7 = 3788*/ + Dcg_gainx100 = 100; + Coarse_gain = 2; DIG_gain = 1; + Coarse_gain_reg = 0x01; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 7577) { /* 3.7x ~ 7.4x 1024 * 7.4 = 7577 */ + Dcg_gainx100 = 370; + Coarse_gain = 1; DIG_gain = 1; + Coarse_gain_reg = 0x80; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 15115) { /* 7.4x ~ 14.8x 1024 * 14.8 = 15115*/ + Dcg_gainx100 = 370; + Coarse_gain = 2; DIG_gain = 1; + Coarse_gain_reg = 0x81; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 30310) { /* 14.8x ~ 29.6x 1024 * 29.6 = 30310*/ + Dcg_gainx100 = 370; + Coarse_gain = 4; DIG_gain = 1; + Coarse_gain_reg = 0x83; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 60620) { /* 29.6x ~ 59.2x 1024 * 59.2 = 60620*/ + Dcg_gainx100 = 370; + Coarse_gain = 8; DIG_gain = 1; + Coarse_gain_reg = 0x87; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain <= 119347) { + /* End again 59.2x ~ 116.55x 1024 * 116.55 = 119347*/ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 1; + Coarse_gain_reg = 0x8f; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain <= 119347 * 2) { /* Start dgain 1.0x ~ 2.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 1; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 119347 * 4) { /* 2.0x ~ 4.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 2; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x1; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 119347 * 8) { /* 4.0x ~ 8.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 4; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x3; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 1894633) { /* End dgain 8.0x ~ 15.875x 119347*15.875=1894633*/ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 8; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x7; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } + + if (total_gain < 3776) + ANA_Fine_gain_reg = abs(100 * total_gain / (Dcg_gainx100 * Coarse_gain) / 32); // *NOPAD* + else if (total_gain == 3776) /* 3.688x */ + ANA_Fine_gain_reg = 0x3B; + else if (total_gain < 119347) /* again */ + ANA_Fine_gain_reg = abs(100 * total_gain / (Dcg_gainx100 * Coarse_gain) / 32); // *NOPAD* + else /* dgain */ + DIG_Fine_gain_reg = abs(800 * total_gain / (Dcg_gainx100 * Coarse_gain * // *NOPAD* + DIG_gain) / ANA_Fine_gainx64); + + if (mode == SC235HAI_LGAIN) { + ret = sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_DIG_GAIN, + SC235HAI_REG_VALUE_08BIT, + DIG_gain_reg & 0xF); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_DIG_FINE_GAIN, + SC235HAI_REG_VALUE_08BIT, + DIG_Fine_gain_reg); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_ANA_GAIN, + SC235HAI_REG_VALUE_08BIT, + Coarse_gain_reg); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_ANA_FINE_GAIN, + SC235HAI_REG_VALUE_08BIT, + ANA_Fine_gain_reg); + } else { + ret = sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SDIG_GAIN, + SC235HAI_REG_VALUE_08BIT, + DIG_gain_reg & 0xF); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SDIG_FINE_GAIN, + SC235HAI_REG_VALUE_08BIT, + DIG_Fine_gain_reg); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SANA_GAIN, + SC235HAI_REG_VALUE_08BIT, + Coarse_gain_reg); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SANA_FINE_GAIN, + SC235HAI_REG_VALUE_08BIT, + ANA_Fine_gain_reg); + } + + return ret; +} + +static int sc235hai_set_hdrae(struct sc235hai *sc235hai, + struct preisp_hdrae_exp_s *ae) +{ + int ret = 0; + u32 l_exp_time, m_exp_time, s_exp_time; + u32 l_a_gain, m_a_gain, s_a_gain; + + if (!sc235hai->has_init_exp && !sc235hai->streaming) { + sc235hai->init_hdrae_exp = *ae; + sc235hai->has_init_exp = true; + dev_dbg(&sc235hai->client->dev, "sc235hai don't stream, record exp for hdr!\n"); + return ret; + } + l_exp_time = ae->long_exp_reg; + m_exp_time = ae->middle_exp_reg; + s_exp_time = ae->short_exp_reg; + l_a_gain = ae->long_gain_reg; + m_a_gain = ae->middle_gain_reg; + s_a_gain = ae->short_gain_reg; + + dev_dbg(&sc235hai->client->dev, + "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n", + l_exp_time, m_exp_time, s_exp_time, + l_a_gain, m_a_gain, s_a_gain); + + if (sc235hai->cur_mode->hdr_mode == HDR_X2) { + //2 stagger + l_a_gain = m_a_gain; + l_exp_time = m_exp_time; + } + + //set exposure + l_exp_time = l_exp_time * 2; + s_exp_time = s_exp_time * 2; + if (l_exp_time > 4362) //(2250 - 64 - 5) * 2 + l_exp_time = 4362; + if (s_exp_time > 404) //(64 - 5) * 2 + s_exp_time = 404; + + ret = sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_H, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_H(l_exp_time)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_M, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_M(l_exp_time)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_L, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_L(l_exp_time)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SEXPOSURE_M, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_M(s_exp_time)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_SEXPOSURE_L, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_L(s_exp_time)); + + ret |= sc235hai_set_gain_reg(sc235hai, l_a_gain, SC235HAI_LGAIN); + ret |= sc235hai_set_gain_reg(sc235hai, s_a_gain, SC235HAI_SGAIN); + return ret; + + return ret; +} + +static int sc235hai_get_reso_dist(const struct sc235hai_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct sc235hai_mode * +sc235hai_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = sc235hai_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } else if (dist == cur_best_fit_dist && + framefmt->code == supported_modes[i].bus_fmt) { + cur_best_fit = i; + break; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int sc235hai_set_rates(struct sc235hai *sc235hai) +{ + const struct sc235hai_mode *mode = sc235hai->cur_mode; + s64 h_blank, vblank_def; + int ret = 0; + u64 pixel_rate = 0; + + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(sc235hai->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(sc235hai->vblank, vblank_def, + SC235HAI_VTS_MAX - mode->height, + 1, vblank_def); + pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] / + mode->bpp * 2 * SC235HAI_LANES; + __v4l2_ctrl_s_ctrl_int64(sc235hai->pixel_rate, + pixel_rate); + __v4l2_ctrl_s_ctrl(sc235hai->link_freq, + mode->mipi_freq_idx); + + return ret; +} + +static int sc235hai_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + const struct sc235hai_mode *mode; + + mutex_lock(&sc235hai->mutex); + + mode = sc235hai_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; +#else + mutex_unlock(&sc235hai->mutex); + return -ENOTTY; +#endif + } else { + sc235hai->cur_mode = mode; + sc235hai_set_rates(sc235hai); + sc235hai->cur_fps = mode->max_fps; + } + + mutex_unlock(&sc235hai->mutex); + + return 0; +} + +static int sc235hai_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + const struct sc235hai_mode *mode = sc235hai->cur_mode; + + mutex_lock(&sc235hai->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); +#else + mutex_unlock(&sc235hai->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&sc235hai->mutex); + + return 0; +} + +static int sc235hai_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(bus_code)) + return -EINVAL; + code->code = bus_code[code->index]; + + return 0; +} + +static int sc235hai_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int sc235hai_enable_test_pattern(struct sc235hai *sc235hai, u32 pattern) +{ + u32 val = 0; + int ret = 0; + + ret = sc235hai_read_reg(sc235hai->client, SC235HAI_REG_TEST_PATTERN, + SC235HAI_REG_VALUE_08BIT, &val); + if (pattern) + val |= SC235HAI_TEST_PATTERN_BIT_MASK; + else + val &= ~SC235HAI_TEST_PATTERN_BIT_MASK; + + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_TEST_PATTERN, + SC235HAI_REG_VALUE_08BIT, val); + return ret; +} + +static int sc235hai_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + const struct sc235hai_mode *mode = sc235hai->cur_mode; + + if (sc235hai->streaming) + fi->interval = sc235hai->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static const struct sc235hai_mode *sc235hai_find_mode(struct sc235hai *sc235hai, int fps) +{ + const struct sc235hai_mode *mode = NULL; + const struct sc235hai_mode *match = NULL; + int cur_fps = 0; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + mode = &supported_modes[i]; + if (mode->width == sc235hai->cur_mode->width && + mode->height == sc235hai->cur_mode->height && + mode->hdr_mode == sc235hai->cur_mode->hdr_mode && + mode->bus_fmt == sc235hai->cur_mode->bus_fmt) { + cur_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator); + if (cur_fps == fps) { + match = mode; + break; + } + } + } + return match; +} + +static int sc235hai_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + const struct sc235hai_mode *mode = NULL; + struct v4l2_fract *fract = &fi->interval; + int fps; + + if (sc235hai->streaming) + return -EBUSY; + + if (fi->pad != 0) + return -EINVAL; + + if (fract->numerator == 0) { + v4l2_err(sd, "error param, check interval param\n"); + return -EINVAL; + } + fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); + mode = sc235hai_find_mode(sc235hai, fps); + if (mode == NULL) { + v4l2_err(sd, "couldn't match fi\n"); + return -EINVAL; + } + + sc235hai->cur_mode = mode; + + sc235hai_set_rates(sc235hai); + + return 0; +} + +static int sc235hai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + config->type = V4L2_MBUS_CSI2_DPHY; + config->bus.mipi_csi2.num_data_lanes = SC235HAI_LANES; + + return 0; +} + +static void sc235hai_get_module_inf(struct sc235hai *sc235hai, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, SC235HAI_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, sc235hai->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, sc235hai->len_name, sizeof(inf->base.lens)); +} + +static int sc235hai_get_channel_info(struct sc235hai *sc235hai, + struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + ch_info->vc = sc235hai->cur_mode->vc[ch_info->index]; + ch_info->width = sc235hai->cur_mode->width; + ch_info->height = sc235hai->cur_mode->height; + ch_info->bus_fmt = sc235hai->cur_mode->bus_fmt; + return 0; +} + +static long sc235hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + struct rkmodule_hdr_cfg *hdr; + struct rkmodule_channel_info *ch_info; + u32 i, w, h; + long ret = 0; + u32 stream = 0; + u32 *sync_mode = NULL; + int cur_best_fit = -1; + int cur_best_fit_dist = -1; + int cur_dist, cur_fps, dst_fps; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + sc235hai_get_module_inf(sc235hai, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = sc235hai->cur_mode->hdr_mode; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + if (hdr->hdr_mode == sc235hai->cur_mode->hdr_mode) + return 0; + w = sc235hai->cur_mode->width; + h = sc235hai->cur_mode->height; + dst_fps = DIV_ROUND_CLOSEST(sc235hai->cur_mode->max_fps.denominator, + sc235hai->cur_mode->max_fps.numerator); + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + cur_fps = DIV_ROUND_CLOSEST(supported_modes[i].max_fps.denominator, + supported_modes[i].max_fps.numerator); + cur_dist = abs(cur_fps - dst_fps); + if (cur_best_fit_dist == -1 || cur_dist < cur_best_fit_dist) { + cur_best_fit_dist = cur_dist; + cur_best_fit = i; + } else if (cur_dist == cur_best_fit_dist) { + cur_best_fit = i; + break; + } + } + } + if (cur_best_fit == -1) { + dev_err(&sc235hai->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + sc235hai->cur_mode = &supported_modes[cur_best_fit]; + sc235hai_set_rates(sc235hai); + sc235hai->cur_fps = sc235hai->cur_mode->max_fps; + } + break; + case PREISP_CMD_SET_HDRAE_EXP: + sc235hai_set_hdrae(sc235hai, arg); + if (sc235hai->cam_sw_info) + memcpy(&sc235hai->cam_sw_info->hdr_ae, (struct preisp_hdrae_exp_s *)(arg), + sizeof(struct preisp_hdrae_exp_s)); + break; + case RKMODULE_SET_QUICK_STREAM: + stream = *((u32 *)arg); + if (sc235hai->standby_hw) { // hardware standby + if (stream) { + if (!IS_ERR(sc235hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc235hai->pwdn_gpio, 1); + // Make sure __v4l2_ctrl_handler_setup can be called correctly + sc235hai->is_standby = false; + +#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP) + if (__v4l2_ctrl_handler_setup(&sc235hai->ctrl_handler)) + dev_err(&sc235hai->client->dev, "__v4l2_ctrl_handler_setup fail!"); + if (sc235hai->cur_mode->hdr_mode != NO_HDR) { + if (sc235hai->cam_sw_info) { + ret = sc235hai_ioctl(&sc235hai->subdev, + PREISP_CMD_SET_HDRAE_EXP, + &sc235hai->cam_sw_info->hdr_ae); + if (ret) { + dev_err(&sc235hai->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + } + } +#endif + + // according sensor FAE: to save power to set 0x302c,0x363c,0x36e9,0x37f9 + ret = sc235hai_write_reg(sc235hai->client, 0x302c, + SC235HAI_REG_VALUE_08BIT, 0x00); + ret |= sc235hai_write_reg(sc235hai->client, 0x363c, + SC235HAI_REG_VALUE_08BIT, 0x8e); + ret |= sc235hai_write_reg(sc235hai->client, 0x36e9, + SC235HAI_REG_VALUE_08BIT, 0x24); + ret |= sc235hai_write_reg(sc235hai->client, 0x37f9, + SC235HAI_REG_VALUE_08BIT, 0x24); + ret |= sc235hai_write_reg(sc235hai->client, 0x3018, + SC235HAI_REG_VALUE_08BIT, 0x3A); + + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_MIPI_CTRL, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MIPI_CTRL_ON); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MODE_STREAMING); + + dev_info(&sc235hai->client->dev, "quickstream, streaming on: exit hw standby mode\n"); + } else { + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MODE_SW_STANDBY); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_MIPI_CTRL, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MIPI_CTRL_OFF); + ret |= sc235hai_write_reg(sc235hai->client, 0x363c, + SC235HAI_REG_VALUE_08BIT, 0xae); + ret |= sc235hai_write_reg(sc235hai->client, 0x36e9, + SC235HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc235hai_write_reg(sc235hai->client, 0x37f9, + SC235HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc235hai_write_reg(sc235hai->client, 0x3018, + SC235HAI_REG_VALUE_08BIT, 0x3F); + + if (!IS_ERR(sc235hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc235hai->pwdn_gpio, 0); + + dev_info(&sc235hai->client->dev, "quickstream, streaming off: enter hw standby mode\n"); + sc235hai->is_standby = true; + } + } else { // software standby + if (stream) { + // according sensor FAE: to save power to set 0x302c,0x363c,0x36e9,0x37f9 + ret = sc235hai_write_reg(sc235hai->client, 0x302c, + SC235HAI_REG_VALUE_08BIT, 0x00); + ret |= sc235hai_write_reg(sc235hai->client, 0x363c, + SC235HAI_REG_VALUE_08BIT, 0x8e); + ret |= sc235hai_write_reg(sc235hai->client, 0x36e9, + SC235HAI_REG_VALUE_08BIT, 0x24); + ret |= sc235hai_write_reg(sc235hai->client, 0x37f9, + SC235HAI_REG_VALUE_08BIT, 0x24); + ret |= sc235hai_write_reg(sc235hai->client, 0x3018, + SC235HAI_REG_VALUE_08BIT, 0x3A); + + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_MIPI_CTRL, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MIPI_CTRL_ON); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MODE_STREAMING); + dev_info(&sc235hai->client->dev, "quickstream, streaming on: exit soft standby mode\n"); + } else { + // according sensor FAE: to save power to set 0x302c,0x363c,0x36e9,0x37f9 + ret = sc235hai_write_reg(sc235hai->client, 0x302c, + SC235HAI_REG_VALUE_08BIT, 0x01); + + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MODE_SW_STANDBY); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_REG_MIPI_CTRL, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_MIPI_CTRL_OFF); + + ret |= sc235hai_write_reg(sc235hai->client, 0x363c, + SC235HAI_REG_VALUE_08BIT, 0xae); + ret |= sc235hai_write_reg(sc235hai->client, 0x36e9, + SC235HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc235hai_write_reg(sc235hai->client, 0x37f9, + SC235HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc235hai_write_reg(sc235hai->client, 0x3018, + SC235HAI_REG_VALUE_08BIT, 0x3F); + dev_info(&sc235hai->client->dev, "quickstream, streaming off: enter soft standby mode\n"); + } + } + break; + case RKMODULE_GET_SYNC_MODE: + sync_mode = (u32 *)arg; + *sync_mode = sc235hai->sync_mode; + break; + case RKMODULE_SET_SYNC_MODE: + sync_mode = (u32 *)arg; + sc235hai->sync_mode = *sync_mode; + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = sc235hai_get_channel_info(sc235hai, ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long sc235hai_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_hdr_cfg *hdr; + struct rkmodule_channel_info *ch_info; + struct preisp_hdrae_exp_s *hdrae; + long ret; + u32 stream = 0; + u32 *sync_mode = NULL; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = sc235hai_ioctl(sd, cmd, inf); + if (!ret) { + ret = copy_to_user(up, inf, sizeof(*inf)); + if (ret) + return -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = sc235hai_ioctl(sd, cmd, hdr); + if (!ret) { + ret = copy_to_user(up, hdr, sizeof(*hdr)); + if (ret) + return -EFAULT; + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdr, up, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + + ret = sc235hai_ioctl(sd, cmd, hdr); + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdrae, up, sizeof(*hdrae))) { + kfree(hdrae); + return -EFAULT; + } + + ret = sc235hai_ioctl(sd, cmd, hdrae); + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + if (copy_from_user(&stream, up, sizeof(u32))) + return -EFAULT; + + ret = sc235hai_ioctl(sd, cmd, &stream); + break; + case RKMODULE_GET_SYNC_MODE: + ret = sc235hai_ioctl(sd, cmd, &sync_mode); + if (!ret) { + ret = copy_to_user(up, &sync_mode, sizeof(u32)); + if (ret) + ret = -EFAULT; + } + break; + case RKMODULE_SET_SYNC_MODE: + ret = copy_from_user(&sync_mode, up, sizeof(u32)); + if (!ret) + ret = sc235hai_ioctl(sd, cmd, &sync_mode); + else + ret = -EFAULT; + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = sc235hai_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __sc235hai_start_stream(struct sc235hai *sc235hai) +{ + int ret; + + dev_info(&sc235hai->client->dev, + "%dx%d@%d, mode %d, vts 0x%x\n", + sc235hai->cur_mode->width, + sc235hai->cur_mode->height, + sc235hai->cur_fps.denominator / sc235hai->cur_fps.numerator, + sc235hai->cur_mode->hdr_mode, + sc235hai->cur_vts); + + if (!sc235hai->is_thunderboot) { + ret = sc235hai_write_array(sc235hai->client, sc235hai->cur_mode->reg_list); + if (ret) + return ret; + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&sc235hai->ctrl_handler); + if (ret) + return ret; + if (sc235hai->has_init_exp && sc235hai->cur_mode->hdr_mode != NO_HDR) { + ret = sc235hai_ioctl(&sc235hai->subdev, PREISP_CMD_SET_HDRAE_EXP, + &sc235hai->init_hdrae_exp); + if (ret) { + dev_err(&sc235hai->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + } + } + return sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, SC235HAI_MODE_STREAMING); +} + +static int __sc235hai_stop_stream(struct sc235hai *sc235hai) +{ + sc235hai->has_init_exp = false; + if (sc235hai->is_thunderboot) { + sc235hai->is_first_streamoff = true; + pm_runtime_put(&sc235hai->client->dev); + } + return sc235hai_write_reg(sc235hai->client, SC235HAI_REG_CTRL_MODE, + SC235HAI_REG_VALUE_08BIT, SC235HAI_MODE_SW_STANDBY); +} + +static int __sc235hai_power_on(struct sc235hai *sc235hai); +static int sc235hai_s_stream(struct v4l2_subdev *sd, int on) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + struct i2c_client *client = sc235hai->client; + int ret = 0; + + mutex_lock(&sc235hai->mutex); + on = !!on; + if (on == sc235hai->streaming) + goto unlock_and_return; + + if (on) { + if (sc235hai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) { + sc235hai->is_thunderboot = false; + __sc235hai_power_on(sc235hai); + } + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __sc235hai_start_stream(sc235hai); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __sc235hai_stop_stream(sc235hai); + pm_runtime_put(&client->dev); + } + + sc235hai->streaming = on; + +unlock_and_return: + mutex_unlock(&sc235hai->mutex); + + return ret; +} + +static int sc235hai_s_power(struct v4l2_subdev *sd, int on) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + struct i2c_client *client = sc235hai->client; + int ret = 0; + + mutex_lock(&sc235hai->mutex); + + /* If the power state is not modified - no work to do. */ + if (sc235hai->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + if (!sc235hai->is_thunderboot) { + ret = sc235hai_write_array(sc235hai->client, sc235hai_global_regs); + if (ret) { + v4l2_err(sd, "could not set init registers\n"); + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + } + + sc235hai->power_on = true; + } else { + pm_runtime_put(&client->dev); + sc235hai->power_on = false; + } + +unlock_and_return: + mutex_unlock(&sc235hai->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 sc235hai_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, SC235HAI_XVCLK_FREQ / 1000 / 1000); +} + +static int __sc235hai_power_on(struct sc235hai *sc235hai) +{ + int ret; + u32 delay_us; + struct device *dev = &sc235hai->client->dev; + + if (!IS_ERR_OR_NULL(sc235hai->pins_default)) { + ret = pinctrl_select_state(sc235hai->pinctrl, + sc235hai->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(sc235hai->xvclk, SC235HAI_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(sc235hai->xvclk) != SC235HAI_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(sc235hai->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + + cam_sw_regulator_bulk_init(sc235hai->cam_sw_info, + SC235HAI_NUM_SUPPLIES, sc235hai->supplies); + + if (sc235hai->is_thunderboot) + return 0; + + if (!IS_ERR(sc235hai->reset_gpio)) + gpiod_set_value_cansleep(sc235hai->reset_gpio, 0); + + ret = regulator_bulk_enable(SC235HAI_NUM_SUPPLIES, sc235hai->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(sc235hai->reset_gpio)) + gpiod_set_value_cansleep(sc235hai->reset_gpio, 1); + + usleep_range(500, 1000); + if (!IS_ERR(sc235hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc235hai->pwdn_gpio, 1); + + if (!IS_ERR(sc235hai->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = sc235hai_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + + return 0; + +disable_clk: + clk_disable_unprepare(sc235hai->xvclk); + + return ret; +} + +static void __sc235hai_power_off(struct sc235hai *sc235hai) +{ + int ret; + struct device *dev = &sc235hai->client->dev; + + clk_disable_unprepare(sc235hai->xvclk); + if (sc235hai->is_thunderboot) { + if (sc235hai->is_first_streamoff) { + sc235hai->is_thunderboot = false; + sc235hai->is_first_streamoff = false; + } else { + return; + } + } + if (!IS_ERR(sc235hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc235hai->pwdn_gpio, 0); + if (!IS_ERR(sc235hai->reset_gpio)) + gpiod_set_value_cansleep(sc235hai->reset_gpio, 0); + if (!IS_ERR_OR_NULL(sc235hai->pins_sleep)) { + ret = pinctrl_select_state(sc235hai->pinctrl, + sc235hai->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(SC235HAI_NUM_SUPPLIES, sc235hai->supplies); +} + +#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP) +static int sc235hai_resume(struct device *dev) +{ + int ret; + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc235hai *sc235hai = to_sc235hai(sd); + + if (sc235hai->standby_hw) { + dev_info(dev, "resume standby!"); + return 0; + } + cam_sw_prepare_wakeup(sc235hai->cam_sw_info, dev); + + usleep_range(4000, 5000); + cam_sw_write_array(sc235hai->cam_sw_info); + + if (__v4l2_ctrl_handler_setup(&sc235hai->ctrl_handler)) + dev_err(dev, "__v4l2_ctrl_handler_setup fail!"); + + if (sc235hai->has_init_exp && sc235hai->cur_mode != NO_HDR) { // hdr mode + ret = sc235hai_ioctl(&sc235hai->subdev, PREISP_CMD_SET_HDRAE_EXP, + &sc235hai->cam_sw_info->hdr_ae); + if (ret) { + dev_err(&sc235hai->client->dev, "set exp fail in hdr mode\n"); + return ret; + } + } + return 0; +} + +static int sc235hai_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc235hai *sc235hai = to_sc235hai(sd); + + if (sc235hai->standby_hw) { + dev_info(dev, "suspend standby!"); + return 0; + } + + cam_sw_write_array_cb_init(sc235hai->cam_sw_info, client, + (void *)sc235hai->cur_mode->reg_list, + (sensor_write_array)sc235hai_write_array); + cam_sw_prepare_sleep(sc235hai->cam_sw_info); + + return 0; +} +#else +#define sc235hai_resume NULL +#define sc235hai_suspend NULL +#endif + +static int sc235hai_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc235hai *sc235hai = to_sc235hai(sd); + + return __sc235hai_power_on(sc235hai); +} + +static int sc235hai_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc235hai *sc235hai = to_sc235hai(sd); + + __sc235hai_power_off(sc235hai); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int sc235hai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct sc235hai *sc235hai = to_sc235hai(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->state, 0); + const struct sc235hai_mode *def_mode = &supported_modes[0]; + + mutex_lock(&sc235hai->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&sc235hai->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int sc235hai_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops sc235hai_pm_ops = { + SET_RUNTIME_PM_OPS(sc235hai_runtime_suspend, sc235hai_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(sc235hai_suspend, sc235hai_resume) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops sc235hai_internal_ops = { + .open = sc235hai_open, +}; +#endif + +static const struct v4l2_subdev_core_ops sc235hai_core_ops = { + .s_power = sc235hai_s_power, + .ioctl = sc235hai_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = sc235hai_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops sc235hai_video_ops = { + .s_stream = sc235hai_s_stream, + .g_frame_interval = sc235hai_g_frame_interval, + .s_frame_interval = sc235hai_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops sc235hai_pad_ops = { + .enum_mbus_code = sc235hai_enum_mbus_code, + .enum_frame_size = sc235hai_enum_frame_sizes, + .enum_frame_interval = sc235hai_enum_frame_interval, + .get_fmt = sc235hai_get_fmt, + .set_fmt = sc235hai_set_fmt, + .get_mbus_config = sc235hai_g_mbus_config, +}; + +static const struct v4l2_subdev_ops sc235hai_subdev_ops = { + .core = &sc235hai_core_ops, + .video = &sc235hai_video_ops, + .pad = &sc235hai_pad_ops, +}; + +static void sc235hai_modify_fps_info(struct sc235hai *sc235hai) +{ + const struct sc235hai_mode *mode = sc235hai->cur_mode; + + sc235hai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / // *NOPAD* + sc235hai->cur_vts; +} + +static int sc235hai_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct sc235hai *sc235hai = container_of(ctrl->handler, + struct sc235hai, ctrl_handler); + struct i2c_client *client = sc235hai->client; + s64 max; + int ret = 0; + u32 val = 0; + s32 temp = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = sc235hai->cur_mode->height + ctrl->val - 5; + __v4l2_ctrl_modify_range(sc235hai->exposure, + sc235hai->exposure->minimum, max, + sc235hai->exposure->step, + sc235hai->exposure->default_value); + break; + } + + if (sc235hai->standby_hw && sc235hai->is_standby) { + dev_dbg(&client->dev, "%s: is_standby = true, will return\n", __func__); + return 0; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val); + if (sc235hai->cur_mode->hdr_mode == NO_HDR) { + temp = ctrl->val * 2; + /* 4 least significant bits of expsoure are fractional part */ + ret = sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_H, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_H(temp)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_M, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_M(temp)); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_EXPOSURE_L, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_EXP_L(temp)); + } + break; + case V4L2_CID_ANALOGUE_GAIN: + if (sc235hai->cur_mode->hdr_mode == NO_HDR) + ret = sc235hai_set_gain_reg(sc235hai, ctrl->val, SC235HAI_LGAIN); + break; + case V4L2_CID_VBLANK: + dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val); + ret = sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_VTS_H, + SC235HAI_REG_VALUE_08BIT, + (ctrl->val + sc235hai->cur_mode->height) + >> 8); + ret |= sc235hai_write_reg(sc235hai->client, + SC235HAI_REG_VTS_L, + SC235HAI_REG_VALUE_08BIT, + (ctrl->val + sc235hai->cur_mode->height) + & 0xff); + if (!ret) + sc235hai->cur_vts = ctrl->val + sc235hai->cur_mode->height; + sc235hai_modify_fps_info(sc235hai); + break; + case V4L2_CID_TEST_PATTERN: + ret = sc235hai_enable_test_pattern(sc235hai, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = sc235hai_read_reg(sc235hai->client, SC235HAI_FLIP_MIRROR_REG, + SC235HAI_REG_VALUE_08BIT, &val); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_FLIP_MIRROR_REG, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_MIRROR(val, ctrl->val)); + break; + case V4L2_CID_VFLIP: + ret = sc235hai_read_reg(sc235hai->client, SC235HAI_FLIP_MIRROR_REG, + SC235HAI_REG_VALUE_08BIT, &val); + ret |= sc235hai_write_reg(sc235hai->client, SC235HAI_FLIP_MIRROR_REG, + SC235HAI_REG_VALUE_08BIT, + SC235HAI_FETCH_FLIP(val, ctrl->val)); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops sc235hai_ctrl_ops = { + .s_ctrl = sc235hai_set_ctrl, +}; + +static int sc235hai_initialize_controls(struct sc235hai *sc235hai) +{ + const struct sc235hai_mode *mode; + struct v4l2_ctrl_handler *handler; + s64 exposure_max, vblank_def; + u64 dst_pixel_rate = 0; + u32 h_blank; + int ret; + + handler = &sc235hai->ctrl_handler; + mode = sc235hai->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &sc235hai->mutex; + + sc235hai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, 0, + link_freq_menu_items); + __v4l2_ctrl_s_ctrl(sc235hai->link_freq, mode->mipi_freq_idx); + + if (mode->mipi_freq_idx == 0) + dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT; + else if (mode->mipi_freq_idx == 1) + dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT; + + sc235hai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, 0, + PIXEL_RATE_WITH_371M_10BIT, + 1, dst_pixel_rate); + + h_blank = mode->hts_def - mode->width; + sc235hai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (sc235hai->hblank) + sc235hai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_def = mode->vts_def - mode->height; + sc235hai->vblank = v4l2_ctrl_new_std(handler, &sc235hai_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + SC235HAI_VTS_MAX - mode->height, + 1, vblank_def); + exposure_max = mode->vts_def - 5; + // exposure_max = 2 * mode->vts_def - 8; + sc235hai->exposure = v4l2_ctrl_new_std(handler, &sc235hai_ctrl_ops, + V4L2_CID_EXPOSURE, SC235HAI_EXPOSURE_MIN, + exposure_max, SC235HAI_EXPOSURE_STEP, + mode->exp_def); + sc235hai->anal_gain = v4l2_ctrl_new_std(handler, &sc235hai_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, SC235HAI_GAIN_MIN, + SC235HAI_GAIN_MAX, SC235HAI_GAIN_STEP, + SC235HAI_GAIN_DEFAULT); + sc235hai->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &sc235hai_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(sc235hai_test_pattern_menu) - 1, + 0, 0, sc235hai_test_pattern_menu); + v4l2_ctrl_new_std(handler, &sc235hai_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + v4l2_ctrl_new_std(handler, &sc235hai_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (handler->error) { + ret = handler->error; + dev_err(&sc235hai->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + sc235hai->subdev.ctrl_handler = handler; + sc235hai->has_init_exp = false; + sc235hai->is_standby = false; + sc235hai->cur_fps = mode->max_fps; + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int sc235hai_check_sensor_id(struct sc235hai *sc235hai, + struct i2c_client *client) +{ + struct device *dev = &sc235hai->client->dev; + u32 id = 0; + int ret; + + if (sc235hai->is_thunderboot) { + dev_info(dev, "Enable thunderboot mode, skip sensor id check\n"); + return 0; + } + ret = sc235hai_read_reg(client, SC235HAI_REG_CHIP_ID, + SC235HAI_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected SC235HAI (%04x) sensor\n", CHIP_ID); + + return 0; +} + +static int sc235hai_configure_regulators(struct sc235hai *sc235hai) +{ + unsigned int i; + + for (i = 0; i < SC235HAI_NUM_SUPPLIES; i++) + sc235hai->supplies[i].supply = sc235hai_supply_names[i]; + + return devm_regulator_bulk_get(&sc235hai->client->dev, + SC235HAI_NUM_SUPPLIES, + sc235hai->supplies); +} + +static int sc235hai_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct sc235hai *sc235hai; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + u32 i, hdr_mode = 0; + const char *sync_mode_name = NULL; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + sc235hai = devm_kzalloc(dev, sizeof(*sc235hai), GFP_KERNEL); + if (!sc235hai) + return -ENOMEM; + + of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode); + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &sc235hai->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &sc235hai->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &sc235hai->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &sc235hai->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + /* Compatible with non-standby mode if this attribute is not configured in dts*/ + of_property_read_u32(node, RKMODULE_CAMERA_STANDBY_HW, + &sc235hai->standby_hw); + dev_info(dev, "sc235hai->standby_hw = %d\n", sc235hai->standby_hw); + + ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE, + &sync_mode_name); + if (ret) { + sc235hai->sync_mode = NO_SYNC_MODE; + dev_err(dev, "could not get sync mode!\n"); + } else { + if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0) { + sc235hai->sync_mode = EXTERNAL_MASTER_MODE; + dev_info(dev, "external master mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0) { + sc235hai->sync_mode = INTERNAL_MASTER_MODE; + dev_info(dev, "internal master mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0) { + sc235hai->sync_mode = SLAVE_MODE; + dev_info(dev, "slave mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_SOFT_SYNC_MODE) == 0) { + sc235hai->sync_mode = SOFT_SYNC_MODE; + dev_info(dev, "sync_mode = [SOFT_SYNC_MODE]\n"); + } else { + dev_info(dev, "sync_mode = [NO_SYNC_MODE]\n"); + } + } + + sc235hai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); + sc235hai->client = client; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (hdr_mode == supported_modes[i].hdr_mode) { + sc235hai->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) + sc235hai->cur_mode = &supported_modes[0]; + + sc235hai->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(sc235hai->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + sc235hai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(sc235hai->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + sc235hai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(sc235hai->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + + sc235hai->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(sc235hai->pinctrl)) { + sc235hai->pins_default = + pinctrl_lookup_state(sc235hai->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(sc235hai->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + sc235hai->pins_sleep = + pinctrl_lookup_state(sc235hai->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(sc235hai->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = sc235hai_configure_regulators(sc235hai); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&sc235hai->mutex); + + sd = &sc235hai->subdev; + v4l2_i2c_subdev_init(sd, client, &sc235hai_subdev_ops); + ret = sc235hai_initialize_controls(sc235hai); + if (ret) + goto err_destroy_mutex; + + ret = __sc235hai_power_on(sc235hai); + if (ret) + goto err_free_handler; + + ret = sc235hai_check_sensor_id(sc235hai, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &sc235hai_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + sc235hai->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &sc235hai->pad); + if (ret < 0) + goto err_power_off; +#endif + + if (!sc235hai->cam_sw_info) { + sc235hai->cam_sw_info = cam_sw_init(); + cam_sw_clk_init(sc235hai->cam_sw_info, sc235hai->xvclk, SC235HAI_XVCLK_FREQ); + cam_sw_reset_pin_init(sc235hai->cam_sw_info, sc235hai->reset_gpio, 0); + cam_sw_pwdn_pin_init(sc235hai->cam_sw_info, sc235hai->pwdn_gpio, 1); + } + + memset(facing, 0, sizeof(facing)); + if (strcmp(sc235hai->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + sc235hai->module_index, facing, + SC235HAI_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + if (sc235hai->is_thunderboot) + pm_runtime_get_sync(dev); + else + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __sc235hai_power_off(sc235hai); +err_free_handler: + v4l2_ctrl_handler_free(&sc235hai->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&sc235hai->mutex); + + return ret; +} + +static void sc235hai_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc235hai *sc235hai = to_sc235hai(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&sc235hai->ctrl_handler); + mutex_destroy(&sc235hai->mutex); + + cam_sw_deinit(sc235hai->cam_sw_info); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __sc235hai_power_off(sc235hai); + pm_runtime_set_suspended(&client->dev); +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id sc235hai_of_match[] = { + { .compatible = "smartsens,sc235hai" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sc235hai_of_match); +#endif + +static const struct i2c_device_id sc235hai_match_id[] = { + { "smartsens,sc235hai", 0 }, + { }, +}; + +static struct i2c_driver sc235hai_i2c_driver = { + .driver = { + .name = SC235HAI_NAME, + .pm = &sc235hai_pm_ops, + .of_match_table = of_match_ptr(sc235hai_of_match), + }, + .probe = sc235hai_probe, + .remove = sc235hai_remove, + .id_table = sc235hai_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&sc235hai_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&sc235hai_i2c_driver); +} + +#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) +subsys_initcall(sensor_mod_init); +#else +device_initcall_sync(sensor_mod_init); +#endif +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("smartsens sc235hai sensor driver"); +MODULE_LICENSE("GPL"); From 8805d031be45943da983e3018530a1848327ac34 Mon Sep 17 00:00:00 2001 From: LongChang Ma Date: Sat, 16 Aug 2025 16:58:32 +0800 Subject: [PATCH 14/14] media: i2c: add support sc231hai sensor driver Signed-off-by: LongChang Ma Change-Id: Ia3d60c6fe2050c1eb45e0b208691af0453ea5497 --- drivers/media/i2c/Kconfig | 10 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/sc231hai.c | 2189 ++++++++++++++++++++++++++++++++++ 3 files changed, 2200 insertions(+) create mode 100644 drivers/media/i2c/sc231hai.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 6038383257a3..16652565d2bb 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1978,6 +1978,16 @@ config VIDEO_SC2310 This is a Video4Linux2 sensor driver for the SmartSens SC2310 camera. +config VIDEO_SC231HAI + tristate "SmartSens SC231HAI sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the SmartSens + SC231HAI camera. + config VIDEO_SC2336 tristate "SmartSens SC2336 sensor support" depends on I2C && VIDEO_DEV diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 30b3d29eda2e..6f6ebaaf17be 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -245,6 +245,7 @@ obj-$(CONFIG_VIDEO_SC2239) += sc2239.o obj-$(CONFIG_VIDEO_SC223A) += sc223a.o obj-$(CONFIG_VIDEO_SC230AI) += sc230ai.o obj-$(CONFIG_VIDEO_SC2310) += sc2310.o +obj-$(CONFIG_VIDEO_SC231HAI) += sc231hai.o obj-$(CONFIG_VIDEO_SC2336) += sc2336.o obj-$(CONFIG_VIDEO_SC2355) += sc2355.o obj-$(CONFIG_VIDEO_SC235HAI) += sc235hai.o diff --git a/drivers/media/i2c/sc231hai.c b/drivers/media/i2c/sc231hai.c new file mode 100644 index 000000000000..2bb4b5b23f2f --- /dev/null +++ b/drivers/media/i2c/sc231hai.c @@ -0,0 +1,2189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sc231hai driver + * + * Copyright (C) 2024 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first implement. + * V0.0X01.0X02 add soft sync mode. + * + */ +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" +#include "cam-sleep-wakeup.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02) + +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define SC231HAI_LANES 2 +#define SC231HAI_BITS_PER_SAMPLE 10 +#define SC231HAI_LINK_FREQ_371 371250000// 742.5Mbps + +#define PIXEL_RATE_WITH_371M_10BIT (SC231HAI_LINK_FREQ_371 * 2 * \ + SC231HAI_LANES / SC231HAI_BITS_PER_SAMPLE) + +#define SC231HAI_XVCLK_FREQ 27000000 + +#define CHIP_ID 0xcb6a +#define SC231HAI_REG_CHIP_ID 0x3107 + +#define SC231HAI_REG_CTRL_MODE 0x0100 +#define SC231HAI_MODE_SW_STANDBY 0x0 +#define SC231HAI_MODE_STREAMING BIT(0) + +#define SC231HAI_REG_MIPI_CTRL 0x3019 +#define SC231HAI_MIPI_CTRL_ON 0x0c +#define SC231HAI_MIPI_CTRL_OFF 0x0f + +#define SC231HAI_REG_EXPOSURE_H 0x3e00 +#define SC231HAI_REG_EXPOSURE_M 0x3e01 +#define SC231HAI_REG_EXPOSURE_L 0x3e02 +#define SC231HAI_REG_SEXPOSURE_H 0x3e22 +#define SC231HAI_REG_SEXPOSURE_M 0x3e04 +#define SC231HAI_REG_SEXPOSURE_L 0x3e05 +#define SC231HAI_EXPOSURE_MIN 1 +#define SC231HAI_EXPOSURE_STEP 1 +#define SC231HAI_VTS_MAX 0x7fff + +#define SC231HAI_REG_DIG_GAIN 0x3e06 +#define SC231HAI_REG_DIG_FINE_GAIN 0x3e07 +#define SC231HAI_REG_ANA_GAIN 0x3e08 +#define SC231HAI_REG_ANA_FINE_GAIN 0x3e09 + +#define SC231HAI_REG_SDIG_GAIN 0x3e10 +#define SC231HAI_REG_SDIG_FINE_GAIN 0x3e11 +#define SC231HAI_REG_SANA_GAIN 0x3e12 +#define SC231HAI_REG_SANA_FINE_GAIN 0x3e13 +#define SC231HAI_REG_MAX_SEXPOSURE_H 0x3e23 +#define SC231HAI_REG_MAX_SEXPOSURE_L 0x3e24 + +#define SC231HAI_GAIN_MIN 0x20 +#define SC231HAI_GAIN_MAX (117 * 16 * 32) // 116.55*15.875*32 +#define SC231HAI_GAIN_STEP 1 +#define SC231HAI_GAIN_DEFAULT 0x40 +#define SC231HAI_LGAIN 0 +#define SC231HAI_SGAIN 1 + +#define SC231HAI_REG_GROUP_HOLD 0x3812 +#define SC231HAI_GROUP_HOLD_START 0x00 +#define SC231HAI_GROUP_HOLD_END 0x30 + +#define SC231HAI_REG_HIGH_TEMP_H 0x3974 +#define SC231HAI_REG_HIGH_TEMP_L 0x3975 + +#define SC231HAI_REG_TEST_PATTERN 0x4501 +#define SC231HAI_TEST_PATTERN_BIT_MASK BIT(3) + +#define SC231HAI_REG_VTS_H 0x320e +#define SC231HAI_REG_VTS_L 0x320f + +#define SC231HAI_FLIP_MIRROR_REG 0x3221 + +#define SC231HAI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF) +#define SC231HAI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF) +#define SC231HAI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4) + +#define SC231HAI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03) +#define SC231HAI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF) + +#define SC231HAI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9) +#define SC231HAI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f) + +#define REG_DELAY 0xFFFE +#define REG_NULL 0xFFFF + +#define SC231HAI_REG_VALUE_08BIT 1 +#define SC231HAI_REG_VALUE_16BIT 2 +#define SC231HAI_REG_VALUE_24BIT 3 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" +#define SC231HAI_NAME "sc231hai" + +static const char *const sc231hai_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define SC231HAI_NUM_SUPPLIES ARRAY_SIZE(sc231hai_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct sc231hai_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 mipi_freq_idx; + u32 bpp; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct sc231hai { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[SC231HAI_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *test_pattern; + struct mutex mutex; + struct v4l2_fract cur_fps; + bool streaming; + bool power_on; + const struct sc231hai_mode *cur_mode; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + enum rkmodule_sync_mode sync_mode; + u32 cur_vts; + bool has_init_exp; + bool is_thunderboot; + bool is_first_streamoff; + u32 standby_hw; + struct preisp_hdrae_exp_s init_hdrae_exp; + struct cam_sw_info *cam_sw_info; +}; + +#define to_sc231hai(sd) container_of(sd, struct sc231hai, subdev) + +/* + * Xclk 27Mhz + */ +static const struct regval sc231hai_global_regs[] = { + {REG_NULL, 0x00}, +}; + +static __maybe_unused const struct regval sc231hai_linear_10_640x480_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x301f, 0x2d}, + {0x3200, 0x00}, + {0x3201, 0x00}, + {0x3202, 0x00}, + {0x3203, 0x3c}, + {0x3204, 0x07}, + {0x3205, 0x87}, + {0x3206, 0x04}, + {0x3207, 0x03}, + {0x3208, 0x02}, + {0x3209, 0x80}, + {0x320a, 0x01}, + {0x320b, 0xe0}, + {0x320e, 0x02}, + {0x320f, 0x32}, + {0x3210, 0x00}, + {0x3211, 0xa2}, + {0x3212, 0x00}, + {0x3213, 0x02}, + {0x3215, 0x31}, + {0x3220, 0x01}, + {0x3301, 0x09}, + {0x3304, 0x50}, + {0x3306, 0x48}, + {0x3308, 0x18}, + {0x3309, 0x68}, + {0x330a, 0x00}, + {0x330b, 0xc0}, + {0x331e, 0x41}, + {0x331f, 0x59}, + {0x3333, 0x10}, + {0x3334, 0x40}, + {0x335d, 0x60}, + {0x335e, 0x06}, + {0x335f, 0x08}, + {0x3364, 0x5e}, + {0x337c, 0x02}, + {0x337d, 0x0a}, + {0x3390, 0x01}, + {0x3391, 0x0b}, + {0x3392, 0x0f}, + {0x3393, 0x0c}, + {0x3394, 0x0d}, + {0x3395, 0x60}, + {0x3396, 0x48}, + {0x3397, 0x49}, + {0x3398, 0x4f}, + {0x3399, 0x0a}, + {0x339a, 0x0f}, + {0x339b, 0x14}, + {0x339c, 0x60}, + {0x33a2, 0x04}, + {0x33af, 0x40}, + {0x33b1, 0x80}, + {0x33b3, 0x40}, + {0x33b9, 0x0a}, + {0x33f9, 0x70}, + {0x33fb, 0x90}, + {0x33fc, 0x4b}, + {0x33fd, 0x5f}, + {0x349f, 0x03}, + {0x34a6, 0x4b}, + {0x34a7, 0x4f}, + {0x34a8, 0x30}, + {0x34a9, 0x20}, + {0x34aa, 0x00}, + {0x34ab, 0xe0}, + {0x34ac, 0x01}, + {0x34ad, 0x00}, + {0x34f8, 0x5f}, + {0x34f9, 0x10}, + {0x3630, 0xc0}, + {0x3633, 0x44}, + {0x3637, 0x29}, + {0x363b, 0x20}, + {0x3670, 0x09}, + {0x3674, 0xb0}, + {0x3675, 0x80}, + {0x3676, 0x88}, + {0x367c, 0x40}, + {0x367d, 0x49}, + {0x3690, 0x44}, + {0x3691, 0x44}, + {0x3692, 0x54}, + {0x369c, 0x49}, + {0x369d, 0x4f}, + {0x36ae, 0x4b}, + {0x36af, 0x4f}, + {0x36b0, 0x87}, + {0x36b1, 0x9b}, + {0x36b2, 0xb7}, + {0x36d0, 0x01}, + {0x36ea, 0x0b}, + {0x36eb, 0x04}, + {0x36ec, 0x1c}, + {0x36ed, 0x24}, + {0x370f, 0x01}, + {0x3722, 0x17}, + {0x3728, 0x90}, + {0x37b0, 0x17}, + {0x37b1, 0x17}, + {0x37b2, 0x97}, + {0x37b3, 0x4b}, + {0x37b4, 0x4f}, + {0x37fa, 0x0b}, + {0x37fb, 0x24}, + {0x37fc, 0x10}, + {0x37fd, 0x22}, + {0x3901, 0x02}, + {0x3902, 0xc5}, + {0x3904, 0x04}, + {0x3907, 0x00}, + {0x3908, 0x41}, + {0x3909, 0x00}, + {0x390a, 0x00}, + {0x391f, 0x04}, + {0x3933, 0x84}, + {0x3934, 0x02}, + {0x3940, 0x62}, + {0x3941, 0x00}, + {0x3942, 0x04}, + {0x3943, 0x03}, + {0x3e00, 0x00}, + {0x3e01, 0x45}, + {0x3e02, 0xb0}, + {0x440e, 0x02}, + {0x450d, 0x11}, + {0x4819, 0x05}, + {0x481b, 0x03}, + {0x481d, 0x0a}, + {0x481f, 0x02}, + {0x4821, 0x08}, + {0x4823, 0x03}, + {0x4825, 0x02}, + {0x4827, 0x03}, + {0x4829, 0x04}, + {0x5000, 0x46}, + {0x5010, 0x01}, + {0x5787, 0x08}, + {0x5788, 0x03}, + {0x5789, 0x00}, + {0x578a, 0x10}, + {0x578b, 0x08}, + {0x578c, 0x00}, + {0x5790, 0x08}, + {0x5791, 0x04}, + {0x5792, 0x00}, + {0x5793, 0x10}, + {0x5794, 0x08}, + {0x5795, 0x00}, + {0x5799, 0x06}, + {0x57ad, 0x00}, + {0x5900, 0xf1}, + {0x5901, 0x04}, + {0x5ae0, 0xfe}, + {0x5ae1, 0x40}, + {0x5ae2, 0x3f}, + {0x5ae3, 0x38}, + {0x5ae4, 0x28}, + {0x5ae5, 0x3f}, + {0x5ae6, 0x38}, + {0x5ae7, 0x28}, + {0x5ae8, 0x3f}, + {0x5ae9, 0x3c}, + {0x5aea, 0x2c}, + {0x5aeb, 0x3f}, + {0x5aec, 0x3c}, + {0x5aed, 0x2c}, + {0x5af4, 0x3f}, + {0x5af5, 0x38}, + {0x5af6, 0x28}, + {0x5af7, 0x3f}, + {0x5af8, 0x38}, + {0x5af9, 0x28}, + {0x5afa, 0x3f}, + {0x5afb, 0x3c}, + {0x5afc, 0x2c}, + {0x5afd, 0x3f}, + {0x5afe, 0x3c}, + {0x5aff, 0x2c}, + {0x36e9, 0x20}, + {0x37f9, 0x24}, + {REG_NULL, 0x00}, +}; + +/* + * Xclk 27Mhz + * max_framerate 60fps + * mipi_datarate per lane 371.25Mbps, 2lane + */ +static const struct regval sc231hai_linear_10_1920x1080_60fps_regs[] = { + {0x0103, 0x01}, + {0x36e9, 0x80}, + {0x37f9, 0x80}, + {0x301f, 0x02}, + {0x3058, 0x21}, + {0x3059, 0x53}, + {0x305a, 0x40}, + {0x3250, 0x00}, + {0x3301, 0x0a}, + {0x3302, 0x20}, + {0x3304, 0x90}, + {0x3305, 0x00}, + {0x3306, 0x78}, + {0x3309, 0xd0}, + {0x330b, 0xe8}, + {0x330d, 0x08}, + {0x331c, 0x04}, + {0x331e, 0x81}, + {0x331f, 0xc1}, + {0x3323, 0x06}, + {0x3333, 0x10}, + {0x3334, 0x40}, + {0x3364, 0x5e}, + {0x336c, 0x8c}, + {0x337f, 0x13}, + {0x338f, 0x80}, + {0x3390, 0x08}, + {0x3391, 0x18}, + {0x3392, 0xb8}, + {0x3393, 0x0e}, + {0x3394, 0x14}, + {0x3395, 0x10}, + {0x3396, 0x88}, + {0x3397, 0x98}, + {0x3398, 0xf8}, + {0x3399, 0x0a}, + {0x339a, 0x0e}, + {0x339b, 0x10}, + {0x339c, 0x14}, + {0x33ae, 0x80}, + {0x33af, 0xc0}, + {0x33b2, 0x50}, + {0x33b3, 0x08}, + {0x33f8, 0x00}, + {0x33f9, 0x78}, + {0x33fa, 0x00}, + {0x33fb, 0x78}, + {0x33fc, 0x48}, + {0x33fd, 0x78}, + {0x349f, 0x03}, + {0x34a6, 0x40}, + {0x34a7, 0x58}, + {0x34a8, 0x08}, + {0x34a9, 0x0c}, + {0x34f8, 0x78}, + {0x34f9, 0x18}, + {0x3619, 0x20}, + {0x361a, 0x90}, + {0x3633, 0x44}, + {0x3637, 0x5c}, + {0x363c, 0xc0}, + {0x363d, 0x02}, + {0x3660, 0x80}, + {0x3661, 0x81}, + {0x3662, 0x8f}, + {0x3663, 0x81}, + {0x3664, 0x81}, + {0x3665, 0x82}, + {0x3666, 0x8f}, + {0x3667, 0x08}, + {0x3668, 0x80}, + {0x3669, 0x88}, + {0x366a, 0x98}, + {0x366b, 0xb8}, + {0x366c, 0xf8}, + {0x3670, 0xc2}, + {0x3671, 0xc2}, + {0x3672, 0x98}, + {0x3680, 0x43}, + {0x3681, 0x54}, + {0x3682, 0x54}, + {0x36c0, 0x80}, + {0x36c1, 0x88}, + {0x36c8, 0x88}, + {0x36c9, 0xb8}, + {0x3718, 0x04}, + {0x3722, 0x8b}, + {0x3724, 0xd1}, + {0x3741, 0x08}, + {0x3770, 0x17}, + {0x3771, 0x9b}, + {0x3772, 0x9b}, + {0x37c0, 0x88}, + {0x37c1, 0xb8}, + {0x3902, 0xc0}, + {0x3903, 0x40}, + {0x3909, 0x00}, + {0x391f, 0x41}, + {0x3926, 0xe0}, + {0x3933, 0x80}, + {0x3934, 0x02}, + {0x3937, 0x6f}, + {0x3e00, 0x00}, + {0x3e01, 0x8b}, + {0x3e02, 0xf0}, + {0x3e08, 0x00}, + {0x4509, 0x20}, + {0x450d, 0x07}, + {0x5780, 0x76}, + {0x5784, 0x10}, + {0x5787, 0x0a}, + {0x5788, 0x0a}, + {0x5789, 0x08}, + {0x578a, 0x0a}, + {0x578b, 0x0a}, + {0x578c, 0x08}, + {0x578d, 0x40}, + {0x5792, 0x04}, + {0x5795, 0x04}, + {0x57ac, 0x00}, + {0x57ad, 0x00}, + {0x36e9, 0x24}, + {0x37f9, 0x24}, + //{0x0100, 0x01}, + {REG_NULL, 0x00}, +}; + + +static const struct sc231hai_mode supported_modes[] = { + { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .exp_def = 0x0460, + .hts_def = 0x44C * 2, + .vts_def = 0x0465, + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .reg_list = sc231hai_linear_10_1920x1080_60fps_regs, + .hdr_mode = NO_HDR, + .bpp = 10, + .mipi_freq_idx = 0, + .vc[PAD0] = 0, + }, +}; + +static const u32 bus_code[] = { + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + +static const s64 link_freq_menu_items[] = { + SC231HAI_LINK_FREQ_371 +}; + +static const char *const sc231hai_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +/* Write registers up to 4 at a time */ +static int sc231hai_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int sc231hai_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) + ret = sc231hai_write_reg(client, regs[i].addr, + SC231HAI_REG_VALUE_08BIT, regs[i].val); + + return ret; +} + +/* Read registers up to 4 at a time */ +static int sc231hai_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +/* mode: 0 = lgain 1 = sgain */ +static int sc231hai_set_gain_reg(struct sc231hai *sc231hai, u32 total_gain, int mode) +{ + u8 Coarse_gain = 1, DIG_gain = 1; + u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1; + u8 Coarse_gain_reg = 0, DIG_gain_reg = 0; + u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80; + int ret = 0; + + total_gain = total_gain * 32; + if (total_gain < SC231HAI_GAIN_MIN * 32) + total_gain = SC231HAI_GAIN_MIN; + else if (total_gain > SC231HAI_GAIN_MAX * 32) + total_gain = SC231HAI_GAIN_MAX * 32; + + if (total_gain < 2 * 1024) { /* Start again 1.0x ~ 2.0x */ + Dcg_gainx100 = 100; + Coarse_gain = 1; DIG_gain = 1; + Coarse_gain_reg = 0x00; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 3788) { /* 2.0x ~ 3.7x 1024 * 3.7 = 3788*/ + Dcg_gainx100 = 100; + Coarse_gain = 2; DIG_gain = 1; + Coarse_gain_reg = 0x01; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 7577) { /* 3.7x ~ 7.4x 1024 * 7.4 = 7577 */ + Dcg_gainx100 = 370; + Coarse_gain = 1; DIG_gain = 1; + Coarse_gain_reg = 0x80; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 15115) { /* 7.4x ~ 14.8x 1024 * 14.8 = 15115*/ + Dcg_gainx100 = 370; + Coarse_gain = 2; DIG_gain = 1; + Coarse_gain_reg = 0x81; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 30310) { /* 14.8x ~ 29.6x 1024 * 29.6 = 30310*/ + Dcg_gainx100 = 370; + Coarse_gain = 4; DIG_gain = 1; + Coarse_gain_reg = 0x83; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain < 60620) { /* 29.6x ~ 59.2x 1024 * 59.2 = 60620*/ + Dcg_gainx100 = 370; + Coarse_gain = 8; DIG_gain = 1; + Coarse_gain_reg = 0x87; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain <= 119347) { + /* End again 59.2x ~ 116.55x 1024 * 116.55 = 119347*/ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 1; + Coarse_gain_reg = 0x8f; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + } else if (total_gain <= 119347 * 2) { /* Start dgain 1.0x ~ 2.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 1; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x0; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 119347 * 4) { /* 2.0x ~ 4.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 2; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x1; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 119347 * 8) { /* 4.0x ~ 8.0x */ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 4; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x3; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } else if (total_gain <= 1894633) { /* End dgain 8.0x ~ 15.875x 119347*15.875=1894633*/ + Dcg_gainx100 = 370; + Coarse_gain = 16; DIG_gain = 8; + Coarse_gain_reg = 0x8f; ANA_Fine_gain_reg = 0x3f; + DIG_gain_reg = 0x7; DIG_Fine_gain_reg = 0x80; + ANA_Fine_gainx64 = 127; + } + + if (total_gain < 3776) + ANA_Fine_gain_reg = abs(100 * total_gain / (Dcg_gainx100 * Coarse_gain) / 32); + else if (total_gain == 3776) /* 3.688x */ + ANA_Fine_gain_reg = 0x3B; + else if (total_gain < 119347) /* again */ + ANA_Fine_gain_reg = abs(100 * total_gain / (Dcg_gainx100 * Coarse_gain) / 32); + else /* dgain */ + DIG_Fine_gain_reg = abs(800 * total_gain / (Dcg_gainx100 * Coarse_gain * + DIG_gain) / ANA_Fine_gainx64); + + if (mode == SC231HAI_LGAIN) { + ret = sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_DIG_GAIN, + SC231HAI_REG_VALUE_08BIT, + DIG_gain_reg & 0xF); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_DIG_FINE_GAIN, + SC231HAI_REG_VALUE_08BIT, + DIG_Fine_gain_reg); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_ANA_GAIN, + SC231HAI_REG_VALUE_08BIT, + Coarse_gain_reg); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_ANA_FINE_GAIN, + SC231HAI_REG_VALUE_08BIT, + ANA_Fine_gain_reg); + } else { + ret = sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SDIG_GAIN, + SC231HAI_REG_VALUE_08BIT, + DIG_gain_reg & 0xF); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SDIG_FINE_GAIN, + SC231HAI_REG_VALUE_08BIT, + DIG_Fine_gain_reg); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SANA_GAIN, + SC231HAI_REG_VALUE_08BIT, + Coarse_gain_reg); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SANA_FINE_GAIN, + SC231HAI_REG_VALUE_08BIT, + ANA_Fine_gain_reg); + } + + return ret; +} + +static int sc231hai_set_hdrae(struct sc231hai *sc231hai, + struct preisp_hdrae_exp_s *ae) +{ + int ret = 0; + u32 l_exp_time, m_exp_time, s_exp_time; + u32 l_a_gain, m_a_gain, s_a_gain; + + if (!sc231hai->has_init_exp && !sc231hai->streaming) { + sc231hai->init_hdrae_exp = *ae; + sc231hai->has_init_exp = true; + dev_dbg(&sc231hai->client->dev, "sc231hai don't stream, record exp for hdr!\n"); + return ret; + } + l_exp_time = ae->long_exp_reg; + m_exp_time = ae->middle_exp_reg; + s_exp_time = ae->short_exp_reg; + l_a_gain = ae->long_gain_reg; + m_a_gain = ae->middle_gain_reg; + s_a_gain = ae->short_gain_reg; + + dev_dbg(&sc231hai->client->dev, + "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n", + l_exp_time, m_exp_time, s_exp_time, + l_a_gain, m_a_gain, s_a_gain); + + if (sc231hai->cur_mode->hdr_mode == HDR_X2) { + //2 stagger + l_a_gain = m_a_gain; + l_exp_time = m_exp_time; + } + + //set exposure + l_exp_time = l_exp_time * 2; + s_exp_time = s_exp_time * 2; + if (l_exp_time > 4362) //(2250 - 64 - 5) * 2 + l_exp_time = 4362; + if (s_exp_time > 404) //(64 - 5) * 2 + s_exp_time = 404; + + ret = sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_H, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_H(l_exp_time)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_M, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_M(l_exp_time)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_L, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_L(l_exp_time)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SEXPOSURE_M, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_M(s_exp_time)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_SEXPOSURE_L, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_L(s_exp_time)); + + ret |= sc231hai_set_gain_reg(sc231hai, l_a_gain, SC231HAI_LGAIN); + ret |= sc231hai_set_gain_reg(sc231hai, s_a_gain, SC231HAI_SGAIN); + return ret; + + return ret; +} + +static int sc231hai_get_reso_dist(const struct sc231hai_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct sc231hai_mode * +sc231hai_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = sc231hai_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } else if (dist == cur_best_fit_dist && + framefmt->code == supported_modes[i].bus_fmt) { + cur_best_fit = i; + break; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int sc231hai_set_rates(struct sc231hai *sc231hai) +{ + const struct sc231hai_mode *mode = sc231hai->cur_mode; + s64 h_blank, vblank_def; + int ret = 0; + u64 pixel_rate = 0; + + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(sc231hai->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(sc231hai->vblank, vblank_def, + SC231HAI_VTS_MAX - mode->height, + 1, vblank_def); + pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] / + mode->bpp * 2 * SC231HAI_LANES; + __v4l2_ctrl_s_ctrl_int64(sc231hai->pixel_rate, + pixel_rate); + __v4l2_ctrl_s_ctrl(sc231hai->link_freq, + mode->mipi_freq_idx); + + return ret; +} + +static int sc231hai_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + const struct sc231hai_mode *mode; + + mutex_lock(&sc231hai->mutex); + + mode = sc231hai_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; +#else + mutex_unlock(&sc231hai->mutex); + return -ENOTTY; +#endif + } else { + sc231hai->cur_mode = mode; + sc231hai_set_rates(sc231hai); + sc231hai->cur_fps = mode->max_fps; + } + + mutex_unlock(&sc231hai->mutex); + + return 0; +} + +static int sc231hai_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + const struct sc231hai_mode *mode = sc231hai->cur_mode; + + mutex_lock(&sc231hai->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); +#else + mutex_unlock(&sc231hai->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&sc231hai->mutex); + + return 0; +} + +static int sc231hai_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(bus_code)) + return -EINVAL; + code->code = bus_code[code->index]; + + return 0; +} + +static int sc231hai_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int sc231hai_enable_test_pattern(struct sc231hai *sc231hai, u32 pattern) +{ + u32 val = 0; + int ret = 0; + + ret = sc231hai_read_reg(sc231hai->client, SC231HAI_REG_TEST_PATTERN, + SC231HAI_REG_VALUE_08BIT, &val); + if (pattern) + val |= SC231HAI_TEST_PATTERN_BIT_MASK; + else + val &= ~SC231HAI_TEST_PATTERN_BIT_MASK; + + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_REG_TEST_PATTERN, + SC231HAI_REG_VALUE_08BIT, val); + return ret; +} + +static int sc231hai_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + const struct sc231hai_mode *mode = sc231hai->cur_mode; + + if (sc231hai->streaming) + fi->interval = sc231hai->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static const struct sc231hai_mode *sc231hai_find_mode(struct sc231hai *sc231hai, int fps) +{ + const struct sc231hai_mode *mode = NULL; + const struct sc231hai_mode *match = NULL; + int cur_fps = 0; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + mode = &supported_modes[i]; + if (mode->width == sc231hai->cur_mode->width && + mode->height == sc231hai->cur_mode->height && + mode->hdr_mode == sc231hai->cur_mode->hdr_mode && + mode->bus_fmt == sc231hai->cur_mode->bus_fmt) { + cur_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator); + if (cur_fps == fps) { + match = mode; + break; + } + } + } + return match; +} + +static int sc231hai_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + const struct sc231hai_mode *mode = NULL; + struct v4l2_fract *fract = &fi->interval; + int fps; + + if (sc231hai->streaming) + return -EBUSY; + + if (fi->pad != 0) + return -EINVAL; + + if (fract->numerator == 0) { + v4l2_err(sd, "error param, check interval param\n"); + return -EINVAL; + } + fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); + mode = sc231hai_find_mode(sc231hai, fps); + if (mode == NULL) { + v4l2_err(sd, "couldn't match fi\n"); + return -EINVAL; + } + + sc231hai->cur_mode = mode; + + sc231hai_set_rates(sc231hai); + + return 0; +} + +static int sc231hai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + config->type = V4L2_MBUS_CSI2_DPHY; + config->bus.mipi_csi2.num_data_lanes = SC231HAI_LANES; + + return 0; +} + +static void sc231hai_get_module_inf(struct sc231hai *sc231hai, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, SC231HAI_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, sc231hai->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, sc231hai->len_name, sizeof(inf->base.lens)); +} + +static int sc231hai_get_channel_info(struct sc231hai *sc231hai, + struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + ch_info->vc = sc231hai->cur_mode->vc[ch_info->index]; + ch_info->width = sc231hai->cur_mode->width; + ch_info->height = sc231hai->cur_mode->height; + ch_info->bus_fmt = sc231hai->cur_mode->bus_fmt; + return 0; +} + +static long sc231hai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + struct rkmodule_hdr_cfg *hdr; + struct rkmodule_channel_info *ch_info; + u32 i, w, h; + long ret = 0; + u32 stream = 0; + u32 *sync_mode = NULL; + int cur_best_fit = -1; + int cur_best_fit_dist = -1; + int cur_dist, cur_fps, dst_fps; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + sc231hai_get_module_inf(sc231hai, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = sc231hai->cur_mode->hdr_mode; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + if (hdr->hdr_mode == sc231hai->cur_mode->hdr_mode) + return 0; + w = sc231hai->cur_mode->width; + h = sc231hai->cur_mode->height; + dst_fps = DIV_ROUND_CLOSEST(sc231hai->cur_mode->max_fps.denominator, + sc231hai->cur_mode->max_fps.numerator); + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + cur_fps = DIV_ROUND_CLOSEST(supported_modes[i].max_fps.denominator, + supported_modes[i].max_fps.numerator); + cur_dist = abs(cur_fps - dst_fps); + if (cur_best_fit_dist == -1 || cur_dist < cur_best_fit_dist) { + cur_best_fit_dist = cur_dist; + cur_best_fit = i; + } else if (cur_dist == cur_best_fit_dist) { + cur_best_fit = i; + break; + } + } + } + if (cur_best_fit == -1) { + dev_err(&sc231hai->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + sc231hai->cur_mode = &supported_modes[cur_best_fit]; + sc231hai_set_rates(sc231hai); + sc231hai->cur_fps = sc231hai->cur_mode->max_fps; + } + break; + case PREISP_CMD_SET_HDRAE_EXP: + sc231hai_set_hdrae(sc231hai, arg); + if (sc231hai->cam_sw_info) + memcpy(&sc231hai->cam_sw_info->hdr_ae, (struct preisp_hdrae_exp_s *)(arg), + sizeof(struct preisp_hdrae_exp_s)); + break; + case RKMODULE_SET_QUICK_STREAM: + stream = *((u32 *)arg); + if (stream) { + // according sensor FAE: to save power to set 0x302c,0x363c,0x36e9,0x37f9 + ret = sc231hai_write_reg(sc231hai->client, 0x302c, + SC231HAI_REG_VALUE_08BIT, 0x00); + ret |= sc231hai_write_reg(sc231hai->client, 0x363c, + SC231HAI_REG_VALUE_08BIT, 0x8e); + ret |= sc231hai_write_reg(sc231hai->client, 0x36e9, + SC231HAI_REG_VALUE_08BIT, 0x24); + ret |= sc231hai_write_reg(sc231hai->client, 0x37f9, + SC231HAI_REG_VALUE_08BIT, 0x24); + ret |= sc231hai_write_reg(sc231hai->client, 0x3018, + SC231HAI_REG_VALUE_08BIT, 0x3A); + + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_REG_MIPI_CTRL, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_MIPI_CTRL_ON); + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_REG_CTRL_MODE, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_MODE_STREAMING); + } else { + // according sensor FAE: to save power to set 0x302c,0x363c,0x36e9,0x37f9 + ret = sc231hai_write_reg(sc231hai->client, 0x302c, + SC231HAI_REG_VALUE_08BIT, 0x01); + + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_REG_CTRL_MODE, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_MODE_SW_STANDBY); + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_REG_MIPI_CTRL, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_MIPI_CTRL_OFF); + + ret |= sc231hai_write_reg(sc231hai->client, 0x363c, + SC231HAI_REG_VALUE_08BIT, 0xae); + ret |= sc231hai_write_reg(sc231hai->client, 0x36e9, + SC231HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc231hai_write_reg(sc231hai->client, 0x37f9, + SC231HAI_REG_VALUE_08BIT, 0xa4); + ret |= sc231hai_write_reg(sc231hai->client, 0x3018, + SC231HAI_REG_VALUE_08BIT, 0x3F); + } + break; + case RKMODULE_GET_SYNC_MODE: + sync_mode = (u32 *)arg; + *sync_mode = sc231hai->sync_mode; + break; + case RKMODULE_SET_SYNC_MODE: + sync_mode = (u32 *)arg; + if (sync_mode) { + sc231hai->sync_mode = *sync_mode; + dev_info(&sc231hai->client->dev, "set sync mode is: %s\n", + ((*sync_mode == EXTERNAL_MASTER_MODE) || + (*sync_mode == SLAVE_MODE)) ? "secondary" : "primary"); + } else { + dev_info(&sc231hai->client->dev, "set sync mode is: NO_SYNC_MODE\n"); + } + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = sc231hai_get_channel_info(sc231hai, ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long sc231hai_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_hdr_cfg *hdr; + struct rkmodule_channel_info *ch_info; + struct preisp_hdrae_exp_s *hdrae; + long ret; + u32 stream = 0; + u32 *sync_mode = NULL; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = sc231hai_ioctl(sd, cmd, inf); + if (!ret) { + ret = copy_to_user(up, inf, sizeof(*inf)); + if (ret) + return -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = sc231hai_ioctl(sd, cmd, hdr); + if (!ret) { + ret = copy_to_user(up, hdr, sizeof(*hdr)); + if (ret) + return -EFAULT; + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdr, up, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + + ret = sc231hai_ioctl(sd, cmd, hdr); + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdrae, up, sizeof(*hdrae))) { + kfree(hdrae); + return -EFAULT; + } + + ret = sc231hai_ioctl(sd, cmd, hdrae); + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + if (copy_from_user(&stream, up, sizeof(u32))) + return -EFAULT; + + ret = sc231hai_ioctl(sd, cmd, &stream); + break; + case RKMODULE_GET_SYNC_MODE: + ret = sc231hai_ioctl(sd, cmd, &sync_mode); + if (!ret) { + ret = copy_to_user(up, &sync_mode, sizeof(u32)); + if (ret) + ret = -EFAULT; + } + break; + case RKMODULE_SET_SYNC_MODE: + ret = copy_from_user(&sync_mode, up, sizeof(u32)); + if (!ret) + ret = sc231hai_ioctl(sd, cmd, &sync_mode); + else + ret = -EFAULT; + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = sc231hai_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __sc231hai_start_stream(struct sc231hai *sc231hai) +{ + int ret; + + dev_info(&sc231hai->client->dev, + "%dx%d@%d, mode %d, vts 0x%x\n", + sc231hai->cur_mode->width, + sc231hai->cur_mode->height, + sc231hai->cur_fps.denominator / sc231hai->cur_fps.numerator, + sc231hai->cur_mode->hdr_mode, + sc231hai->cur_vts); + + if (!sc231hai->is_thunderboot) { + ret = sc231hai_write_array(sc231hai->client, sc231hai->cur_mode->reg_list); + if (ret) + return ret; + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&sc231hai->ctrl_handler); + if (ret) + return ret; + if (sc231hai->has_init_exp && sc231hai->cur_mode->hdr_mode != NO_HDR) { + ret = sc231hai_ioctl(&sc231hai->subdev, PREISP_CMD_SET_HDRAE_EXP, + &sc231hai->init_hdrae_exp); + if (ret) { + dev_err(&sc231hai->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + } + } + return sc231hai_write_reg(sc231hai->client, SC231HAI_REG_CTRL_MODE, + SC231HAI_REG_VALUE_08BIT, SC231HAI_MODE_STREAMING); +} + +static int __sc231hai_stop_stream(struct sc231hai *sc231hai) +{ + sc231hai->has_init_exp = false; + if (sc231hai->is_thunderboot) { + sc231hai->is_first_streamoff = true; + pm_runtime_put(&sc231hai->client->dev); + } + return sc231hai_write_reg(sc231hai->client, SC231HAI_REG_CTRL_MODE, + SC231HAI_REG_VALUE_08BIT, SC231HAI_MODE_SW_STANDBY); +} + +static int __sc231hai_power_on(struct sc231hai *sc231hai); +static int sc231hai_s_stream(struct v4l2_subdev *sd, int on) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + struct i2c_client *client = sc231hai->client; + int ret = 0; + + mutex_lock(&sc231hai->mutex); + on = !!on; + if (on == sc231hai->streaming) + goto unlock_and_return; + + if (on) { + if (sc231hai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) { + sc231hai->is_thunderboot = false; + __sc231hai_power_on(sc231hai); + } + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __sc231hai_start_stream(sc231hai); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __sc231hai_stop_stream(sc231hai); + pm_runtime_put(&client->dev); + } + + sc231hai->streaming = on; + +unlock_and_return: + mutex_unlock(&sc231hai->mutex); + + return ret; +} + +static int sc231hai_s_power(struct v4l2_subdev *sd, int on) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + struct i2c_client *client = sc231hai->client; + int ret = 0; + + mutex_lock(&sc231hai->mutex); + + /* If the power state is not modified - no work to do. */ + if (sc231hai->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + if (!sc231hai->is_thunderboot) { + ret = sc231hai_write_array(sc231hai->client, sc231hai_global_regs); + if (ret) { + v4l2_err(sd, "could not set init registers\n"); + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + } + + sc231hai->power_on = true; + } else { + pm_runtime_put(&client->dev); + sc231hai->power_on = false; + } + +unlock_and_return: + mutex_unlock(&sc231hai->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 sc231hai_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, SC231HAI_XVCLK_FREQ / 1000 / 1000); +} + +static int __sc231hai_power_on(struct sc231hai *sc231hai) +{ + int ret; + u32 delay_us; + struct device *dev = &sc231hai->client->dev; + + if (!IS_ERR_OR_NULL(sc231hai->pins_default)) { + ret = pinctrl_select_state(sc231hai->pinctrl, + sc231hai->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(sc231hai->xvclk, SC231HAI_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(sc231hai->xvclk) != SC231HAI_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(sc231hai->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + + cam_sw_regulator_bulk_init(sc231hai->cam_sw_info, + SC231HAI_NUM_SUPPLIES, sc231hai->supplies); + + if (sc231hai->is_thunderboot) + return 0; + + if (!IS_ERR(sc231hai->reset_gpio)) + gpiod_set_value_cansleep(sc231hai->reset_gpio, 0); + + ret = regulator_bulk_enable(SC231HAI_NUM_SUPPLIES, sc231hai->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(sc231hai->reset_gpio)) + gpiod_set_value_cansleep(sc231hai->reset_gpio, 1); + + usleep_range(500, 1000); + if (!IS_ERR(sc231hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc231hai->pwdn_gpio, 1); + + if (!IS_ERR(sc231hai->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = sc231hai_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + + return 0; + +disable_clk: + clk_disable_unprepare(sc231hai->xvclk); + + return ret; +} + +static void __sc231hai_power_off(struct sc231hai *sc231hai) +{ + int ret; + struct device *dev = &sc231hai->client->dev; + + clk_disable_unprepare(sc231hai->xvclk); + if (sc231hai->is_thunderboot) { + if (sc231hai->is_first_streamoff) { + sc231hai->is_thunderboot = false; + sc231hai->is_first_streamoff = false; + } else { + return; + } + } + if (!IS_ERR(sc231hai->pwdn_gpio)) + gpiod_set_value_cansleep(sc231hai->pwdn_gpio, 0); + if (!IS_ERR(sc231hai->reset_gpio)) + gpiod_set_value_cansleep(sc231hai->reset_gpio, 0); + if (!IS_ERR_OR_NULL(sc231hai->pins_sleep)) { + ret = pinctrl_select_state(sc231hai->pinctrl, + sc231hai->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(SC231HAI_NUM_SUPPLIES, sc231hai->supplies); +} + +#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP) +static int sc231hai_resume(struct device *dev) +{ + int ret; + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc231hai *sc231hai = to_sc231hai(sd); + + if (sc231hai->standby_hw) { + dev_info(dev, "resume standby!"); + return 0; + } + cam_sw_prepare_wakeup(sc231hai->cam_sw_info, dev); + + usleep_range(4000, 5000); + cam_sw_write_array(sc231hai->cam_sw_info); + + if (__v4l2_ctrl_handler_setup(&sc231hai->ctrl_handler)) + dev_err(dev, "__v4l2_ctrl_handler_setup fail!"); + + if (sc231hai->has_init_exp && sc231hai->cur_mode != NO_HDR) { // hdr mode + ret = sc231hai_ioctl(&sc231hai->subdev, PREISP_CMD_SET_HDRAE_EXP, + &sc231hai->cam_sw_info->hdr_ae); + if (ret) { + dev_err(&sc231hai->client->dev, "set exp fail in hdr mode\n"); + return ret; + } + } + return 0; +} + +static int sc231hai_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc231hai *sc231hai = to_sc231hai(sd); + + if (sc231hai->standby_hw) { + dev_info(dev, "suspend standby!"); + return 0; + } + + cam_sw_write_array_cb_init(sc231hai->cam_sw_info, client, + (void *)sc231hai->cur_mode->reg_list, + (sensor_write_array)sc231hai_write_array); + cam_sw_prepare_sleep(sc231hai->cam_sw_info); + + return 0; +} +#else +#define sc231hai_resume NULL +#define sc231hai_suspend NULL +#endif + +static int sc231hai_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc231hai *sc231hai = to_sc231hai(sd); + + return __sc231hai_power_on(sc231hai); +} + +static int sc231hai_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc231hai *sc231hai = to_sc231hai(sd); + + __sc231hai_power_off(sc231hai); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int sc231hai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct sc231hai *sc231hai = to_sc231hai(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->state, 0); + const struct sc231hai_mode *def_mode = &supported_modes[0]; + + mutex_lock(&sc231hai->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&sc231hai->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int sc231hai_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops sc231hai_pm_ops = { + SET_RUNTIME_PM_OPS(sc231hai_runtime_suspend, + sc231hai_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(sc231hai_suspend, sc231hai_resume) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops sc231hai_internal_ops = { + .open = sc231hai_open, +}; +#endif + +static const struct v4l2_subdev_core_ops sc231hai_core_ops = { + .s_power = sc231hai_s_power, + .ioctl = sc231hai_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = sc231hai_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops sc231hai_video_ops = { + .s_stream = sc231hai_s_stream, + .g_frame_interval = sc231hai_g_frame_interval, + .s_frame_interval = sc231hai_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops sc231hai_pad_ops = { + .enum_mbus_code = sc231hai_enum_mbus_code, + .enum_frame_size = sc231hai_enum_frame_sizes, + .enum_frame_interval = sc231hai_enum_frame_interval, + .get_fmt = sc231hai_get_fmt, + .set_fmt = sc231hai_set_fmt, + .get_mbus_config = sc231hai_g_mbus_config, +}; + +static const struct v4l2_subdev_ops sc231hai_subdev_ops = { + .core = &sc231hai_core_ops, + .video = &sc231hai_video_ops, + .pad = &sc231hai_pad_ops, +}; + +static void sc231hai_modify_fps_info(struct sc231hai *sc231hai) +{ + const struct sc231hai_mode *mode = sc231hai->cur_mode; + + sc231hai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / + sc231hai->cur_vts; +} + +static int sc231hai_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct sc231hai *sc231hai = container_of(ctrl->handler, + struct sc231hai, ctrl_handler); + struct i2c_client *client = sc231hai->client; + s64 max; + int ret = 0; + u32 val = 0; + s32 temp = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = sc231hai->cur_mode->height + ctrl->val - 5; + __v4l2_ctrl_modify_range(sc231hai->exposure, + sc231hai->exposure->minimum, max, + sc231hai->exposure->step, + sc231hai->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val); + if (sc231hai->cur_mode->hdr_mode == NO_HDR) { + temp = ctrl->val * 2; + /* 4 least significant bits of expsoure are fractional part */ + ret = sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_H, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_H(temp)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_M, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_M(temp)); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_EXPOSURE_L, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_EXP_L(temp)); + } + break; + case V4L2_CID_ANALOGUE_GAIN: + if (sc231hai->cur_mode->hdr_mode == NO_HDR) + ret = sc231hai_set_gain_reg(sc231hai, ctrl->val, SC231HAI_LGAIN); + break; + case V4L2_CID_VBLANK: + dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val); + ret = sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_VTS_H, + SC231HAI_REG_VALUE_08BIT, + (ctrl->val + sc231hai->cur_mode->height) + >> 8); + ret |= sc231hai_write_reg(sc231hai->client, + SC231HAI_REG_VTS_L, + SC231HAI_REG_VALUE_08BIT, + (ctrl->val + sc231hai->cur_mode->height) + & 0xff); + if (!ret) + sc231hai->cur_vts = ctrl->val + sc231hai->cur_mode->height; + sc231hai_modify_fps_info(sc231hai); + break; + case V4L2_CID_TEST_PATTERN: + ret = sc231hai_enable_test_pattern(sc231hai, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = sc231hai_read_reg(sc231hai->client, SC231HAI_FLIP_MIRROR_REG, + SC231HAI_REG_VALUE_08BIT, &val); + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_FLIP_MIRROR_REG, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_MIRROR(val, ctrl->val)); + break; + case V4L2_CID_VFLIP: + ret = sc231hai_read_reg(sc231hai->client, SC231HAI_FLIP_MIRROR_REG, + SC231HAI_REG_VALUE_08BIT, &val); + ret |= sc231hai_write_reg(sc231hai->client, SC231HAI_FLIP_MIRROR_REG, + SC231HAI_REG_VALUE_08BIT, + SC231HAI_FETCH_FLIP(val, ctrl->val)); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops sc231hai_ctrl_ops = { + .s_ctrl = sc231hai_set_ctrl, +}; + +static int sc231hai_initialize_controls(struct sc231hai *sc231hai) +{ + const struct sc231hai_mode *mode; + struct v4l2_ctrl_handler *handler; + s64 exposure_max, vblank_def; + u64 dst_pixel_rate = 0; + u32 h_blank; + int ret; + + handler = &sc231hai->ctrl_handler; + mode = sc231hai->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &sc231hai->mutex; + + sc231hai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, 0, + link_freq_menu_items); + __v4l2_ctrl_s_ctrl(sc231hai->link_freq, mode->mipi_freq_idx); + + if (mode->mipi_freq_idx == 0) + dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT; + else if (mode->mipi_freq_idx == 1) + dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT; + + sc231hai->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, 0, + PIXEL_RATE_WITH_371M_10BIT, + 1, dst_pixel_rate); + + h_blank = mode->hts_def - mode->width; + sc231hai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (sc231hai->hblank) + sc231hai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_def = mode->vts_def - mode->height; + sc231hai->vblank = v4l2_ctrl_new_std(handler, &sc231hai_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + SC231HAI_VTS_MAX - mode->height, + 1, vblank_def); + // exposure_max = mode->vts_def - 5; + exposure_max = 2 * mode->vts_def - 8; + sc231hai->exposure = v4l2_ctrl_new_std(handler, &sc231hai_ctrl_ops, + V4L2_CID_EXPOSURE, SC231HAI_EXPOSURE_MIN, + exposure_max, SC231HAI_EXPOSURE_STEP, + mode->exp_def); + sc231hai->anal_gain = v4l2_ctrl_new_std(handler, &sc231hai_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, SC231HAI_GAIN_MIN, + SC231HAI_GAIN_MAX, SC231HAI_GAIN_STEP, + SC231HAI_GAIN_DEFAULT); + sc231hai->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &sc231hai_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(sc231hai_test_pattern_menu) - 1, + 0, 0, sc231hai_test_pattern_menu); + v4l2_ctrl_new_std(handler, &sc231hai_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + v4l2_ctrl_new_std(handler, &sc231hai_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (handler->error) { + ret = handler->error; + dev_err(&sc231hai->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + sc231hai->subdev.ctrl_handler = handler; + sc231hai->has_init_exp = false; + sc231hai->cur_fps = mode->max_fps; + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int sc231hai_check_sensor_id(struct sc231hai *sc231hai, + struct i2c_client *client) +{ + struct device *dev = &sc231hai->client->dev; + u32 id = 0; + int ret; + + if (sc231hai->is_thunderboot) { + dev_info(dev, "Enable thunderboot mode, skip sensor id check\n"); + return 0; + } + ret = sc231hai_read_reg(client, SC231HAI_REG_CHIP_ID, + SC231HAI_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected SC321HAI (%06x) sensor\n", CHIP_ID); + + return 0; +} + +static int sc231hai_configure_regulators(struct sc231hai *sc231hai) +{ + unsigned int i; + + for (i = 0; i < SC231HAI_NUM_SUPPLIES; i++) + sc231hai->supplies[i].supply = sc231hai_supply_names[i]; + + return devm_regulator_bulk_get(&sc231hai->client->dev, + SC231HAI_NUM_SUPPLIES, + sc231hai->supplies); +} + +static int sc231hai_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct sc231hai *sc231hai; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + u32 i, hdr_mode = 0; + const char *sync_mode_name = NULL; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + sc231hai = devm_kzalloc(dev, sizeof(*sc231hai), GFP_KERNEL); + if (!sc231hai) + return -ENOMEM; + + of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode); + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &sc231hai->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &sc231hai->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &sc231hai->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &sc231hai->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + /* Compatible with non-standby mode if this attribute is not configured in dts*/ + of_property_read_u32(node, RKMODULE_CAMERA_STANDBY_HW, + &sc231hai->standby_hw); + + ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE, + &sync_mode_name); + if (ret) { + sc231hai->sync_mode = NO_SYNC_MODE; + dev_err(dev, "could not get sync mode!\n"); + } else { + if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0) { + sc231hai->sync_mode = EXTERNAL_MASTER_MODE; + dev_info(dev, "external master mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0) { + sc231hai->sync_mode = INTERNAL_MASTER_MODE; + dev_info(dev, "internal master mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0) { + sc231hai->sync_mode = SLAVE_MODE; + dev_info(dev, "slave mode\n"); + } else if (strcmp(sync_mode_name, RKMODULE_SOFT_SYNC_MODE) == 0) { + sc231hai->sync_mode = SOFT_SYNC_MODE; + dev_info(dev, "sync_mode = [SOFT_SYNC_MODE]\n"); + } else { + dev_info(dev, "sync_mode = [NO_SYNC_MODE]\n"); + } + } + + sc231hai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); + sc231hai->client = client; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (hdr_mode == supported_modes[i].hdr_mode) { + sc231hai->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) + sc231hai->cur_mode = &supported_modes[0]; + + sc231hai->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(sc231hai->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + sc231hai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(sc231hai->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + sc231hai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(sc231hai->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + + sc231hai->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(sc231hai->pinctrl)) { + sc231hai->pins_default = + pinctrl_lookup_state(sc231hai->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(sc231hai->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + sc231hai->pins_sleep = + pinctrl_lookup_state(sc231hai->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(sc231hai->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = sc231hai_configure_regulators(sc231hai); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&sc231hai->mutex); + + sd = &sc231hai->subdev; + v4l2_i2c_subdev_init(sd, client, &sc231hai_subdev_ops); + ret = sc231hai_initialize_controls(sc231hai); + if (ret) + goto err_destroy_mutex; + + ret = __sc231hai_power_on(sc231hai); + if (ret) + goto err_free_handler; + + ret = sc231hai_check_sensor_id(sc231hai, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &sc231hai_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + sc231hai->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &sc231hai->pad); + if (ret < 0) + goto err_power_off; +#endif + + if (!sc231hai->cam_sw_info) { + sc231hai->cam_sw_info = cam_sw_init(); + cam_sw_clk_init(sc231hai->cam_sw_info, sc231hai->xvclk, SC231HAI_XVCLK_FREQ); + cam_sw_reset_pin_init(sc231hai->cam_sw_info, sc231hai->reset_gpio, 0); + cam_sw_pwdn_pin_init(sc231hai->cam_sw_info, sc231hai->pwdn_gpio, 1); + } + + memset(facing, 0, sizeof(facing)); + if (strcmp(sc231hai->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + sc231hai->module_index, facing, + SC231HAI_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + if (sc231hai->is_thunderboot) + pm_runtime_get_sync(dev); + else + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __sc231hai_power_off(sc231hai); +err_free_handler: + v4l2_ctrl_handler_free(&sc231hai->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&sc231hai->mutex); + + return ret; +} + +static void sc231hai_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct sc231hai *sc231hai = to_sc231hai(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&sc231hai->ctrl_handler); + mutex_destroy(&sc231hai->mutex); + + cam_sw_deinit(sc231hai->cam_sw_info); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __sc231hai_power_off(sc231hai); + pm_runtime_set_suspended(&client->dev); +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id sc231hai_of_match[] = { + { .compatible = "smartsens,sc231hai" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sc231hai_of_match); +#endif + +static const struct i2c_device_id sc231hai_match_id[] = { + { "smartsens,sc231hai", 0 }, + { }, +}; + +static struct i2c_driver sc231hai_i2c_driver = { + .driver = { + .name = SC231HAI_NAME, + .pm = &sc231hai_pm_ops, + .of_match_table = of_match_ptr(sc231hai_of_match), + }, + .probe = sc231hai_probe, + .remove = sc231hai_remove, + .id_table = sc231hai_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&sc231hai_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&sc231hai_i2c_driver); +} + +#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) +subsys_initcall(sensor_mod_init); +#else +device_initcall_sync(sensor_mod_init); +#endif +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("smartsens sc231hai sensor driver"); +MODULE_LICENSE("GPL");