From f95633e02b832bb443fb62d3a057e88a1e13c176 Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Fri, 30 Oct 2020 20:03:12 +0800
Subject: [PATCH] arm64: dts: rockchip: Fix usb2phy clk for rk3568

Fixes: 3fefaf4ac83d ("arm64: dts: rockchip: Add usb2 phy nodes for RK3568 Soc")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ib5603aa1c610e3aa9225c2733c48da8941baaf63
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 961d3943c3fc..247ed2e7f9c7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -1830,7 +1830,7 @@
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8a0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru CLK_USBPHY0_REF>;
+		clocks = <&pmucru CLK_USBPHY0_REF>;
 		clock-names = "phyclk";
 		#clock-cells = <0>;
 		clock-output-names = "usb480m_phy";
@@ -1852,7 +1852,7 @@
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8b0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru CLK_USBPHY1_REF>;
+		clocks = <&pmucru CLK_USBPHY1_REF>;
 		clock-names = "phyclk";
 		rockchip,usbgrf = <&usb2phy1_grf>;
 		status = "disabled";