diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2d98916747c1..a843c4e88060 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1216,7 +1216,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-speedy.dtb \ rk3288-veyron-tiger.dtb \ rk3288-vyasa.dtb \ + rk3308-evb-audio-v10-amp-display-rgb-aarch32.dtb \ rk3308-evb-audio-v10-display-rgb-aarch32.dtb \ + rk3308-evb-audio-v11-display-rgb-aarch32.dtb \ rk3308bs-evb-amic-v11-aarch32.dtb \ rk3308bs-evb-dmic-pdm-v11-aarch32.dtb \ rk3308bs-evb-mipi-display-v11-aarch32.dtb \ diff --git a/arch/arm/boot/dts/rk3308-evb-audio-v10-amp-display-rgb-aarch32.dts b/arch/arm/boot/dts/rk3308-evb-audio-v10-amp-display-rgb-aarch32.dts new file mode 100644 index 000000000000..0c01340ff64a --- /dev/null +++ b/arch/arm/boot/dts/rk3308-evb-audio-v10-amp-display-rgb-aarch32.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rk3308-evb-audio-v10-amp-display-rgb.dts" + +/ { + model = "Rockchip RK3308 evb audio display rgb board (AArch32)"; + compatible = "rockchip,rk3308-evb-audio-v10-display-rgb-aarch32", "rockchip,rk3308"; +}; + +&ramoops { + reg = <0x0 0x30000 0x0 0x20000>; + record-size = <0x00000>; + console-size = <0x20000>; +}; diff --git a/arch/arm/boot/dts/rk3308-evb-audio-v11-display-rgb-aarch32.dts b/arch/arm/boot/dts/rk3308-evb-audio-v11-display-rgb-aarch32.dts new file mode 100644 index 000000000000..2138e0f2f8ce --- /dev/null +++ b/arch/arm/boot/dts/rk3308-evb-audio-v11-display-rgb-aarch32.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rk3308-evb-audio-v11-display-rgb.dts" + +/ { + model = "Rockchip RK3308 evb audio v11 display rgb board (AArch32)"; + compatible = "rockchip,rk3308-evb-audio-v11-display-rgb-aarch32", "rockchip,rk3308"; +}; + +&ramoops { + reg = <0x0 0x30000 0x0 0x20000>; + record-size = <0x00000>; + console-size = <0x20000>; +}; diff --git a/arch/arm/boot/dts/rk3308bs-evb-amic-v11-aarch32.dts b/arch/arm/boot/dts/rk3308bs-evb-amic-v11-aarch32.dts index 262cdf2dd161..04e9cd51893b 100644 --- a/arch/arm/boot/dts/rk3308bs-evb-amic-v11-aarch32.dts +++ b/arch/arm/boot/dts/rk3308bs-evb-amic-v11-aarch32.dts @@ -10,11 +10,8 @@ compatible = "rockchip,rk3308bs-evb-amic-v11-aarch32", "rockchip,rk3308"; }; -&ramoops_mem { - reg = <0x0 0x30000 0x0 0x20000>; -}; - &ramoops { - record-size = <0x0 0x00000>; - console-size = <0x0 0x20000>; + reg = <0x0 0x30000 0x0 0x20000>; + record-size = <0x00000>; + console-size = <0x20000>; }; diff --git a/arch/arm/boot/dts/rk3308bs-evb-dmic-pdm-v11-aarch32.dts b/arch/arm/boot/dts/rk3308bs-evb-dmic-pdm-v11-aarch32.dts index 4759afe0b458..8e6884c5270f 100644 --- a/arch/arm/boot/dts/rk3308bs-evb-dmic-pdm-v11-aarch32.dts +++ b/arch/arm/boot/dts/rk3308bs-evb-dmic-pdm-v11-aarch32.dts @@ -10,11 +10,8 @@ compatible = "rockchip,rk3308bs-evb-dmic-pdm-v11-aarch32", "rockchip,rk3308"; }; -&ramoops_mem { - reg = <0x0 0x30000 0x0 0x20000>; -}; - &ramoops { - record-size = <0x0 0x00000>; - console-size = <0x0 0x20000>; + reg = <0x0 0x30000 0x0 0x20000>; + record-size = <0x00000>; + console-size = <0x20000>; }; diff --git a/arch/arm/boot/dts/rk3308bs-evb-mipi-display-v11-aarch32.dts b/arch/arm/boot/dts/rk3308bs-evb-mipi-display-v11-aarch32.dts index 61c3e0fcdb43..af1eac3508c6 100644 --- a/arch/arm/boot/dts/rk3308bs-evb-mipi-display-v11-aarch32.dts +++ b/arch/arm/boot/dts/rk3308bs-evb-mipi-display-v11-aarch32.dts @@ -10,11 +10,8 @@ compatible = "rockchip,rk3308bs-evb-mipi-display-v11-aarch32", "rockchip,rk3308"; }; -&ramoops_mem { - reg = <0x0 0x30000 0x0 0x20000>; -}; - &ramoops { - record-size = <0x0 0x00000>; - console-size = <0x0 0x20000>; + reg = <0x0 0x30000 0x0 0x20000>; + record-size = <0x00000>; + console-size = <0x20000>; }; diff --git a/arch/arm/configs/rk3308_linux_aarch32_defconfig b/arch/arm/configs/rk3308_linux_aarch32_defconfig index 076f01a61e97..bcf6cddf0937 100644 --- a/arch/arm/configs/rk3308_linux_aarch32_defconfig +++ b/arch/arm/configs/rk3308_linux_aarch32_defconfig @@ -209,9 +209,11 @@ CONFIG_CPU_RK3308=y CONFIG_ROCKCHIP_CPUINFO=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_OPP=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_SUSPEND_MODE=y +CONFIG_ROCKCHIP_SYSTEM_MONITOR=y CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b7c6b253e861..358b28f4f38b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -15,9 +15,17 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v13.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-amic-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-amic-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v10-amp-display-rgb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v11-amp-display-rgb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v10-display-rgb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v11-display-rgb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v10-partybox.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v11-partybox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-dmic-pdm-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-dmic-pdm-v13.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-partybox-coreboard-demo-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-partybox-ext-rolling-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308b-evb-amic-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3308-audio-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-audio-amp.dtsi new file mode 100644 index 000000000000..88ba25b979cd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-audio-amp.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include + +#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 0 | ((cluster) << 8)) + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,amp"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>, + <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>, <&cru SCLK_TIMER5>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; + amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; + amp-irqs = /bits/ 64 ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* remote amp core address */ + amp_reserved: amp@2e00000 { + reg = <0x0 0x2e00000 0x0 0x1200000>; + no-map; + }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x08000000 0x0 0x100000>; + no-map; + }; + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg-softirq"; + interrupts = , + ; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&cpu3 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-amic-v11.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-amic-v11.dts new file mode 100644 index 000000000000..e483ee454dda --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-amic-v11.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-amic-v10.dts" +#include "rk3308-evb-audio-v11.dtsi" + +/ { + model = "Rockchip RK3308 evb audio analog mic v11 board"; + compatible = "rockchip,rk3308-evb-audio-amic-v11", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-amp-display-rgb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-amp-display-rgb.dts new file mode 100644 index 000000000000..99f247093d6d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-amp-display-rgb.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-amic-v10.dts" +#include "rk3308-audio-amp.dtsi" + +/ { + model = "Rockchip RK3308B EVB AUDIO DDR3 V10 Board + Rockchip RK3308 RGB ExtBoard V10"; + compatible = "rockchip,rk3308-evb-audio-rgb-display-v10", "rockchip,rk3308"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&fx070_dhm11boe_timing>; + + fx070_dhm11boe_timing: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <2>; //value range <2~22> + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x1000000>; + linux,cma-default; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + touch-gpio = <&gpio0 RK_PA6 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <9110>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&pinctrl { + tp { + tp_int: tp-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-display-rgb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-display-rgb.dts index 1dbcd8b73086..3e58d704a7b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-display-rgb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-display-rgb.dts @@ -55,11 +55,11 @@ compatible = "simple-panel"; bus-format = ; backlight = <&backlight>; - enable-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; - enable-delay-ms = <20>; - reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; - reset-value = <0>; - reset-delay-ms = <10>; + //enable-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + //enable-delay-ms = <20>; + //reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + //reset-value = <0>; + //reset-delay-ms = <10>; status = "okay"; display-timings { @@ -97,7 +97,7 @@ cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0x1000000>; + size = <0x0 0x1800000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-partybox.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-partybox.dts new file mode 100644 index 000000000000..68c03a6442fb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10-partybox.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10-display-rgb.dts" + +/ { + model = "Rockchip RK3308 EVB AUDIO V10 PARTYBOX"; + compatible = "rockchip,rk3308-evb-audio-v10-partybox", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0c0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1 isolcpus=2,3 nohz_full=2,3 snd_soc_core.prealloc_buffer_size_kbytes=16"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x1000000>; + linux,cma-default; + }; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,no-hp-det; + rockchip,boot-dac-out = "line-hp"; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <0 1 2 3>; +}; + +&bluetooth_sound { + status = "disabled"; +}; + +&cpu0_opp_table { + opp-408000000 { + status = "disabled"; + }; + opp-600000000 { + status = "disabled"; + }; + opp-1200000000 { + status = "okay"; + }; + opp-1296000000 { + status = "okay"; + }; +}; + +&dmac0 { + iram = <&vad_sram>; +}; + +&dmac1 { + iram = <&vad_sram>; +}; + +&rk3308bs_cpu0_opp_table { + opp-408000000 { + status = "disabled"; + }; + opp-600000000 { + status = "disabled"; + }; + opp-1008000000 { + status = "okay"; + }; + opp-1104000000 { + status = "okay"; + }; +}; + +&spdif_rx { + status = "okay"; +}; + +&spdif_rx_sound { + status = "okay"; + rockchip,wait-card-locked = <0>; +}; + +&vad { + status = "disabled"; +}; + +&vad_acodec_sound { + status = "okay"; +}; + +&vad_sram { + pool; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10.dtsi index c2a9ea41a012..b8e2e81c6784 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v10.dtsi @@ -10,6 +10,7 @@ /delete-node/ wireless-wlan; /delete-node/ wireless-bluetooth; /delete-node/ gpio-keys; + /delete-node/ tas5731_sound; wireless-wlan { compatible = "wlan-platdata"; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-amp-display-rgb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-amp-display-rgb.dts new file mode 100644 index 000000000000..11e0af1800df --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-amp-display-rgb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10-amp-display-rgb.dts" +#include "rk3308-evb-audio-v11.dtsi" + +/ { + model = "Rockchip RK3308B EVB AUDIO DDR3 V11 Board + Rockchip RK3308 RGB ExtBoard V10"; + compatible = "rockchip,rk3308-evb-audio-rgb-display-v11", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-display-rgb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-display-rgb.dts new file mode 100644 index 000000000000..cfb194e1d56f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-display-rgb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10-display-rgb.dts" +#include "rk3308-evb-audio-v11.dtsi" + +/ { + model = "Rockchip RK3308B EVB AUDIO DDR3 V11 Board + Rockchip RK3308 RGB ExtBoard V10"; + compatible = "rockchip,rk3308-evb-audio-rgb-display-v11", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-partybox.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-partybox.dts new file mode 100644 index 000000000000..d283c33f4417 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11-partybox.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10-partybox.dts" +#include "rk3308-evb-audio-v11.dtsi" + +/ { + model = "Rockchip RK3308 EVB AUDIO V11 PARTYBOX"; + compatible = "rockchip,rk3308-evb-audio-v11-partybox", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11.dtsi new file mode 100644 index 000000000000..27e6e5955de4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-audio-v11.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +&io_domains { + status = "okay"; + vccio2-supply = <&vcc_io>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi index 9a905ea2b1fe..f6a6febe2e64 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi @@ -88,6 +88,7 @@ }; acodec_sound: acodec-sound { + status = "disabled"; compatible = "rockchip,multicodecs-card"; rockchip,card-name = "rockchip,rk3308-acodec"; rockchip,codec-hp-det; @@ -108,29 +109,27 @@ rockchip,wait-card-locked = <0>; }; + spdif_dummy_codec: spdif-dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + spdif_rx_sound: spdif-rx-sound { status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif-rx-sound"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,cpu { - sound-dai = <&spdif_rx>; - }; - simple-audio-card,codec { - sound-dai = <&dummy_codec>; - }; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,spdif-rx"; + rockchip,mclk-fs = <128>; + rockchip,cpu = <&spdif_rx>; + rockchip,codec = <&dummy_codec>; }; spdif_tx_sound: spdif-tx-sound { status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif-tx-sound"; - simple-audio-card,cpu { - sound-dai = <&spdif_tx>; - }; - simple-audio-card,codec { - sound-dai = <&dummy_codec>; - }; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,spdif-tx"; + rockchip,mclk-fs = <128>; + rockchip,cpu = <&spdif_tx>; + rockchip,codec = <&spdif_dummy_codec>; }; tas5731_sound: tas5731-sound { @@ -312,11 +311,6 @@ }; }; -&dmc { - center-supply = <&vdd_log>; - status = "okay"; -}; - &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -772,6 +766,16 @@ status = "disabled"; }; +&spdif_rx { + status = "disabled"; + #sound-dai-cells = <0>; +}; + +&spdif_tx { + status = "disabled"; + #sound-dai-cells = <0>; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ diff --git a/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo-v10.dts b/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo-v10.dts new file mode 100644 index 000000000000..937abf416828 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo-v10.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-partybox-coreboard-demo.dtsi" + +/ { + model = "Rockchip RK3308B PARTYBOX CORE BOARD DEMO V10"; + compatible = "rockchip,rk3308-partybox-coreboard-demo-v10", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo.dtsi new file mode 100644 index 000000000000..e04c3e01cd27 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-partybox-coreboard-demo.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3308-partybox.dtsi" + +/ { + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0c0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait isolcpus=2,3 nohz_full=2,3 snd_soc_core.prealloc_buffer_size_kbytes=16"; + }; + + pwm-leds { + compatible = "pwm-leds"; + + mic1-green-led { + label = "mic1_green"; + pwms = <&pwm1 0 50000 0>; + default-state = "off"; + }; + mic1-red-led { + label = "mic1_red"; + pwms = <&pwm2 0 50000 0>; + default-state = "off"; + }; + mic2-green-led { + label = "mic2_green"; + pwms = <&pwm3 0 50000 0>; + default-state = "off"; + }; + mic2-red-led { + label = "mic2_red"; + pwms = <&pwm4 0 50000 0>; + default-state = "off"; + }; + aux-green-led { + label = "aux_green"; + pwms = <&pwm5 0 50000 0>; + default-state = "off"; + }; + aux-red-led { + label = "aux_red"; + pwms = <&pwm6 0 50000 0>; + default-state = "off"; + }; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_pin>; + BT,power_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&acodec { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; + rockchip,frame-master = <&bt_codec>; + rockchip,bitclock-master = <&bt_codec>; + rockchip,format = "i2s"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&dac_sound { + status = "okay"; +}; + +&dmac0 { + iram = <&vad_sram>; +}; + +&dmac1 { + iram = <&vad_sram>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "disabled"; +}; + + /* + * VCCIO[0:5] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + */ +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; +}; + +&i2s_8ch_0 { + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci{ + status = "disabled"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "disabled"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&vad_sram { + pool; +}; + +&pinctrl { + wireless-bluetooth { + uart4_gpios: uart4-gpios { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-board.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-board.dtsi new file mode 100644 index 000000000000..3b4d3703fa47 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-board.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/ { + dac_codec: dac-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_I2S0_8CH_TX_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&akm4385_reset>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&mic_mute &light_mode &howling_gpio>; + + play { + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Play Pause"; + debounce-interval = <100>; + }; + light { + gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Light Mode"; + debounce-interval = <100>; + }; + howling { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Howling"; + debounce-interval = <100>; + }; + }; + + rotary { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_gpio>; + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>, + <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + linux,axis = <0>; /* REL_X */ + rotary-encoder,relative-axis; + status = "okay"; + }; + + i2s_dac_sound: i2s-dac-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,i2s-dac-sound"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_0>; + rockchip,codec = <&dac_codec>; + rockchip,format = "left_j"; + rockchip,wait-card-locked = <1>; + }; +}; + +&pinctrl { + buttons { + mic_mute: mic-mute { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + light_mode: light-mode { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + howling_gpio: howling-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + dac { + akm4385_reset: akm4385-reset { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + rotary { + rotary_gpio: rotary-gpio { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vccio_flash>; + vccio4-supply = <&vccio_sdio>; + vccio5-supply = <&vccio_sd>; +}; + +&i2s_8ch_0 { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_sdo0 + &i2s_8ch_0_mclk>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-v10.dts b/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-v10.dts new file mode 100644 index 000000000000..e89c919cc1a4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-partybox-ext-rolling-v10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10-partybox.dts" +#include "rk3308-partybox-ext-rolling-board.dtsi" + +/ { + model = "Rockchip RK3308 EVB AUDIO V10 PARTYBOX EXT ROLLING Board"; + compatible = "rockchip,rk3308-partybox-ext-rolling-v10", "rockchip,rk3308"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-partybox.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-partybox.dtsi new file mode 100644 index 000000000000..070abadcc58c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-partybox.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 PARTYBOX"; + compatible = "rockchip,rk3308-partybox", "rockchip,rk3308"; + + bluetooth_sound: bluetooth-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-pcm"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_2ch_0>; + rockchip,codec = <&bt_codec>; + rockchip,format = "i2s"; + rockchip,wait-card-locked = <0>; + + rockchip,frame-master = <&bt_codec>; + rockchip,bitclock-master = <&bt_codec>; + }; + + dac_sound: dac-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk3308-dac"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&sound2_master>; + simple-audio-card,frame-master = <&sound2_master>; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch_0>; + }; + sound2_master:simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + spdif_tx_sound: spdif-tx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + spdif_rx_sound: spdif-rx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-rx-sound"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_rx>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_dummy_codec>; + }; + }; + + bt_codec: bt-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + dummy_codec: dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + spdif_dummy_codec: spdif-dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + vcc_3v3: vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + status = "okay"; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&cpu0_opp_table { + opp-408000000 { + status = "disabled"; + }; + opp-600000000 { + status = "disabled"; + }; + opp-1200000000 { + status = "okay"; + }; + opp-1296000000 { + status = "okay"; + }; +}; + +&dmc { + center-supply = <&vdd_log>; + status = "okay"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&nandc { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&rk3308bs_cpu0_opp_table { + opp-1008000000 { + status = "okay"; + }; + opp-1104000000 { + status = "okay"; + }; +}; + +&rockchip_suspend { + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM_REGULATOR + ) + >; + + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sfc { + status = "okay"; +}; + +&spdif_tx { + #sound-dai-cells = <0>; +}; +&spdif_rx { + #sound-dai-cells = <0>; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 107189003380..5547c17a3f04 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -355,20 +355,6 @@ method = "smc"; }; - ramoops_mem: ramoops_mem { - reg = <0x0 0x110000 0x0 0xf0000>; - reg-names = "ramoops_mem"; - }; - - ramoops: ramoops { - compatible = "ramoops"; - record-size = <0x0 0x30000>; - console-size = <0x0 0xc0000>; - ftrace-size = <0x0 0x00000>; - pmsg-size = <0x0 0x00000>; - memory-region = <&ramoops_mem>; - }; - rgb: rgb { compatible = "rockchip,rk3308-rgb"; status = "disabled"; @@ -403,6 +389,15 @@ compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x30000>; + console-size = <0xc0000>; + ftrace-size = <0x00000>; + pmsg-size = <0x00000>; + }; }; rockchip_suspend: rockchip-suspend { @@ -446,8 +441,14 @@ pmu_pvtm: pmu-pvtm { compatible = "rockchip,rk3308-pmu-pvtm"; - clocks = <&cru SCLK_PVTM_PMU>; - clock-names = "pmu"; + #address-cells = <1>; + #size-cells = <0>; + + pvtm@1 { + reg = <1>; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "clk"; + }; }; reboot-mode { @@ -514,8 +515,14 @@ pvtm: pvtm { compatible = "rockchip,rk3308-pvtm"; - clocks = <&cru SCLK_PVTM_CORE>; - clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + + pvtm@0 { + reg = <0>; + clocks = <&cru SCLK_PVTM_CORE>; + clock-names = "clk"; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index dc84aa15de78..c85b64a20fbc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1546,6 +1546,7 @@ ddc-i2c-scl-low-time-ns = <10000>; reg-io-width = <4>; rockchip,grf = <&grf>; + rockchip,cts-manual; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pins>; phys = <&hdmiphy>; @@ -1962,10 +1963,13 @@ interrupts = ; clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>; clock-names = "mclk", "hclk"; + assigned-clocks = <&cru MCLK_SAI_I2S3>; + assigned-clock-rates = <6144000>; dmas = <&dmac 5>; dma-names = "tx"; resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>; reset-names = "m", "h"; + rockchip,always-on; #sound-dai-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/configs/rk3308_linux_defconfig b/arch/arm64/configs/rk3308_linux_defconfig index f5d9ac2393aa..0e160fad5dba 100644 --- a/arch/arm64/configs/rk3308_linux_defconfig +++ b/arch/arm64/configs/rk3308_linux_defconfig @@ -263,9 +263,11 @@ CONFIG_ROCKCHIP_AMP=y CONFIG_ROCKCHIP_CPUINFO=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_OPP=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_SUSPEND_MODE=y +CONFIG_ROCKCHIP_SYSTEM_MONITOR=y CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y diff --git a/drivers/firmware/rockchip_sip.c b/drivers/firmware/rockchip_sip.c index 785e25420346..b426ec3d4977 100644 --- a/drivers/firmware/rockchip_sip.c +++ b/drivers/firmware/rockchip_sip.c @@ -358,6 +358,19 @@ struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2) } EXPORT_SYMBOL_GPL(sip_hdcp_config); +struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1, u32 arg2, + u32 arg3) +{ + struct arm_smccc_res res; + + /* + * res.a0: error code(0: success, !0: error). + */ + arm_smccc_smc(SIP_GPIO_CFG, sub_func_id, arg1, arg2, arg3, 0, 0, 0, &res); + return res; +} +EXPORT_SYMBOL_GPL(sip_smc_gpio_config); + /************************** fiq debugger **************************************/ /* * AArch32 is not allowed to call SMC64(ATF framework does not support), so we diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index d253ebcf3ce4..78abdb19684d 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1685,6 +1686,8 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, struct analogix_dp_device *dp = bridge->driver_private; struct drm_encoder *encoder = dp->encoder; struct drm_connector *connector = NULL; + struct drm_bridge *last_bridge; + struct drm_panel *panel = NULL; int ret = 0; if (!bridge->encoder) { @@ -1692,6 +1695,9 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, return -ENODEV; } + if (!dp->plat_data->panel) + dp->dp_mode = true; + if (dp->plat_data->bridge) { ret = drm_bridge_attach(bridge->encoder, dp->plat_data->bridge, bridge, dp->plat_data->skip_connector ? @@ -1700,8 +1706,19 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, DRM_ERROR("Failed to attach external bridge: %d\n", ret); return ret; } + + last_bridge = list_last_entry(&bridge->encoder->bridge_chain, + struct drm_bridge, chain_node); + ret = drm_of_find_panel_or_bridge(last_bridge->of_node, 1, -1, &panel, NULL); + if (!ret && panel) + dp->dp_mode = false; } + if (of_property_read_bool(dp->dev->of_node, "dp-mode")) + dp->dp_mode = true; + else if (of_property_read_bool(dp->dev->of_node, "edp-mode")) + dp->dp_mode = false; + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) return 0; diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 915bf6969ca1..8b1da11064bd 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -209,6 +209,8 @@ struct analogix_dp_device { u32 split_area; const struct analogix_dp_output_format *output_fmt; + + bool dp_mode; }; /* analogix_dp_reg.c */ diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 5b58f8219ccc..810b5a2f6041 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -1103,9 +1103,13 @@ int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, int analogix_dp_phy_power_on(struct analogix_dp_device *dp) { + int submode = PHY_SUBMODE_EDP; int ret; - ret = phy_set_mode(dp->phy, PHY_MODE_DP); + if (dp->plat_data->support_dp_mode && dp->dp_mode) + submode = PHY_SUBMODE_DP; + + ret = phy_set_mode_ext(dp->phy, PHY_MODE_DP, submode); if (ret) { dev_err(dp->dev, "phy_set_mode failed: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index f10c85bce57a..a26c01042ae5 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -59,6 +59,8 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, return -EINVAL; } + dw_hdmi_audio_disable(hdmi); + /* Reset the FIFOs before applying new params */ hdmi_update_bits(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); @@ -138,6 +140,11 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, hdmi_write(audio, conf1, HDMI_AUD_CONF1); hdmi_write(audio, conf2, HDMI_AUD_CONF2); + dw_hdmi_audio_enable(hdmi); + hdmi_update_bits(audio, HDMI_AUD_CONF0_SW_RESET, + HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); + hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); + return 0; } diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 169c60893248..0fcb06c19297 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -335,6 +335,7 @@ struct dw_hdmi { bool logo_plug_out; /* hdmi is plug out when kernel logo */ bool update; bool hdr2sdr; /* from hdr to sdr */ + bool cts_manual; }; #define HDMI_IH_PHY_STAT0_RX_SENSE \ @@ -1068,7 +1069,7 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); /* Compute CTS when using internal AHB audio or General Parallel audio*/ - if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { + if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD) || hdmi->cts_manual) { /* * Compute the CTS value from the N value. Note that CTS and N * can be up to 20 bits in total, so we need 64-bit math. Also @@ -5207,6 +5208,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); + hdmi->cts_manual = of_property_read_bool(np, "rockchip,cts-manual"); + if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { struct dw_hdmi_audio_data audio; diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 41b24b0249b2..4b7537e64185 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -60,6 +60,7 @@ struct rockchip_grf_reg_field { * @audio: check if audio is supported by source * @split_mode: check if split mode is supported * @format_yuv: check if YUV output format is supported + * @support_dp_mode: check if dp mode is supported * @max_bpc: the maximum supported bpc */ struct rockchip_dp_chip_data { @@ -73,6 +74,7 @@ struct rockchip_dp_chip_data { bool audio; bool split_mode; bool format_yuv; + bool support_dp_mode; u8 max_bpc; }; @@ -746,6 +748,7 @@ static int rockchip_dp_probe(struct platform_device *pdev) dp->adp = ERR_PTR(-ENODEV); dp->data = &dp_data[id]; dp->plat_data.ssc = dp->data->ssc; + dp->plat_data.support_dp_mode = dp->data->support_dp_mode; dp->plat_data.max_bpc = dp->data->max_bpc ? dp->data->max_bpc : 8; dp->plat_data.panel = panel; dp->plat_data.dev_type = dp->data->chip_type; @@ -906,6 +909,7 @@ static const struct rockchip_dp_chip_data rk3576_edp[] = { .audio = true, .split_mode = true, .format_yuv = true, + .support_dp_mode = true, .max_bpc = 10, }, { /* sentinel */ } @@ -921,6 +925,7 @@ static const struct rockchip_dp_chip_data rk3588_edp[] = { .audio = true, .split_mode = true, .format_yuv = true, + .support_dp_mode = true, .max_bpc = 10, }, { @@ -932,6 +937,7 @@ static const struct rockchip_dp_chip_data rk3588_edp[] = { .audio = true, .split_mode = true, .format_yuv = true, + .support_dp_mode = true, .max_bpc = 10, }, { /* sentinel */ } diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index ec74256903a6..843ac09a17a3 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -446,7 +446,6 @@ struct dw_dp { struct clk *hclk; struct clk *hdcp_clk; struct reset_control *rstc; - struct regmap *grf; struct completion complete; struct completion hdcp_complete; int irq; diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 7b14cb59b1b1..5f5de41e25bc 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -1847,6 +1847,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, struct rockchip_drm_private *priv = dev->dev_private; struct drm_crtc *crtc; struct rockchip_hdmi *hdmi; + struct rockchip_crtc_state *s; if (!encoder) { const struct drm_connector_helper_funcs *funcs; @@ -1892,6 +1893,19 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, return MODE_BAD; }; + if (encoder->crtc) { + s = to_rockchip_crtc_state(encoder->crtc->state); + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + } else { + drm_for_each_crtc(crtc, connector->dev) { + if (!drm_encoder_crtc_ok(encoder, crtc)) + continue; + + s = to_rockchip_crtc_state(crtc->state); + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + } + } + if (hdmi->is_hdmi_qp) { if (!hdmi->enable_gpio && mode->clock > 600000) return MODE_BAD; diff --git a/drivers/input/sensors/lsensor/Kconfig b/drivers/input/sensors/lsensor/Kconfig index 7506d56a016f..c6cc58858a80 100644 --- a/drivers/input/sensors/lsensor/Kconfig +++ b/drivers/input/sensors/lsensor/Kconfig @@ -51,6 +51,10 @@ config LS_STK3410 tristate "light sensor stk3410" default n +config LS_STK33562 + tristate "light sensor stk33562" + default n + config LS_EM3071X tristate "light sensor em3071x" endif diff --git a/drivers/input/sensors/lsensor/Makefile b/drivers/input/sensors/lsensor/Makefile index f1b83a9b0074..d5c84da5ecea 100644 --- a/drivers/input/sensors/lsensor/Makefile +++ b/drivers/input/sensors/lsensor/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_LS_UCS14620) += ls_ucs14620.o obj-$(CONFIG_LS_US5152) += ls_us5152.o obj-$(CONFIG_LS_STK3332) += ls_stk3332.o obj-$(CONFIG_LS_STK3410) += ls_stk3410.o +obj-$(CONFIG_LS_STK33562) += ls_stk33562.o obj-$(CONFIG_LS_EM3071X) += ls_em3071x.o diff --git a/drivers/input/sensors/lsensor/ls_stk33562.c b/drivers/input/sensors/lsensor/ls_stk33562.c new file mode 100644 index 000000000000..92db1f71c279 --- /dev/null +++ b/drivers/input/sensors/lsensor/ls_stk33562.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: Alex Zhao + */ +#include +#include +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CONTROL REGISTER MAP */ +#define STK_STATE 0x00 +#define PS_CTRL 0x01 +#define ALS_CTRL1 0x02 +#define LED_CTRL 0x03 +#define INT_CTRL1 0x04 +#define STK_WAIT 0x05 +#define THDH1_PS 0x06 +#define THDH2_PS 0x07 +#define THDL1_PS 0x08 +#define THDL2_PS 0x09 +#define THDH1_ALS 0x0A +#define THDH2_ALS 0x0B +#define THDL1_ALS 0x0C +#define THDL2_ALS 0x0D +#define STK_FLAG 0x10 +#define DATA1_PS 0x11 +#define DATA2_PS 0x12 +#define DATA1_ALS 0x13 +#define DATA2_ALS 0x14 +#define DATA1_ALS1 0x17 +#define DATA2_ALS1 0x18 +#define DATA1_C 0x1B +#define DATA2_C 0x1C +#define DATA1_PS_OFFSET 0x1D +#define DATA2_PS_OFFSET 0x1E +#define STKPDT_ID 0x3E +#define STK_RESERVED 0x3F +#define GAIN_CTRL 0x4E +#define SOFT_RESET 0x80 +#define PSPD_CTRL 0xA1 +#define INT_CTRL2 0xA5 + +/* STK_STATE 0x00 */ +#define PS_DISABLE (0 << 0) +#define PS_ENABLE (1 << 0) +#define ALS_DISABLE (0 << 1) +#define ALS_ENABLE (1 << 1) +#define WAIT_DISABLE (0 << 2) +#define WAIT_ENABLE (1 << 2) + +/* PSCTRL 0x01 */ +#define PS_IT_96US (0 << 0) +#define PS_IT_192US (1 << 0) +#define PS_IT_384US (2 << 0) +#define PS_IT_768US (3 << 0) +#define PS_IT_1MS54 (4 << 0) +#define PS_IT_3MS07 (5 << 0) +#define PS_IT_6MS14 (6 << 0) + +#define PS_GAIN_1G (0 << 4) +#define PS_GAIN_2G (1 << 4) +#define PS_GAIN_4G (2 << 4) +#define PS_GAIN_8G (3 << 4) + +#define PS_PRST_1T (0 << 6) +#define PS_PRST_2T (1 << 6) +#define PS_PRST_4T (2 << 6) +#define PS_PRST_8T (3 << 6) + +/* ALS_CTRL1 0x02 */ +#define ALS_REFT_MS (1 << 0)/* [3:0] 25 ms, default value is 100ms */ + +#define ALS_GAIN_1G (0 << 4) +#define ALS_GAIN_4G (1 << 4) +#define ALS_GAIN_16G (2 << 4) +#define ALS_GAIN_64G (3 << 4) + +#define ALS_PRST_1T (0 << 6) +#define ALS_PRST_2T (1 << 6) +#define ALS_PRST_4T (2 << 6) +#define ALS_PRST_8T (3 << 6) + +/* LEDCTRL 0x03 */ +#define LED_REFT_US 0x03 /* [5:0] 2.89us , default value is 0.185ms */ +#define CTIR_DISABLE (0 << 0) +#define CTIR_ENABLE (1 << 0) +#define CTIRFC_DISABLE (0 << 1) +#define CTIRFC_ENABLE (1 << 1) + +#define LED_CUR_3_125MA (0 << 4) +#define LED_CUR_6_25MA (1 << 4) +#define LED_CUR_12_5MA (2 << 4) +#define LED_CUR_25MA (3 << 4) +#define LED_CUR_50MA (4 << 4) +#define LED_CUR_75MA (5 << 4) +#define LED_CUR_100MA (6 << 4) +#define LED_CUR_125MA (7 << 4) +#define LED_CUR_150MA (8 << 4) +#define LED_CUR_175MA (9 << 4) +#define LED_CUR_200MA (a << 4) + +/* INTCTRL1 0x04 */ +#define PS_INT_DISABLE (0 << 0) +#define PS_INT_ENABLE (1 << 0) +#define PS_INT_ENABLE_FLGNFH (2 << 0) +#define PS_INT_ENABLE_FLGNFL (3 << 0) +#define PS_INT_MODE_ENABLE (4 << 0) +#define PS_INT_ENABLE_THL (5 << 0) +#define PS_INT_ENABLE_THH (6 << 0) +#define PS_INT_ENABLE_THHL (7 << 0) +#define ALS_INT_DISABLE (0 << 3) +#define ALS_INT_ENABLE (1 << 3) +#define INT_CTRL_PS_OR_LS (0 << 7) +#define INT_CTRL_PS_AND_LS (1 << 7) + +/* FLAG 0x10 */ +#define STK_FLAG_NF (1 << 0) +#define STK_FLAG_INPS_INT (1 << 1) +#define STK_FLAG_ALS_STATE (1 << 2) +#define STK_FLAG_PS_INT (1 << 4) +#define STK_FLAG_ALS_INT (1 << 5) +#define STK_FLAG_PSDR (1 << 6) +#define STK_FLAG_ALSDR (1 << 7) + +static int sensor_active(struct i2c_client *client, int enable, int rate) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + int result = 0; + int status = 0; + + sensor->ops->ctrl_data = sensor_read_reg(client, sensor->ops->ctrl_reg); + if (!enable) { + status = ~ALS_ENABLE; + sensor->ops->ctrl_data &= status; + } else { + status |= ALS_ENABLE; + sensor->ops->ctrl_data |= status; + } + + dev_dbg(&client->dev, "reg=0x%x, reg_ctrl=0x%x, enable=%d\n", + sensor->ops->ctrl_reg, sensor->ops->ctrl_data, enable); + + result = sensor_write_reg(client, sensor->ops->ctrl_reg, + sensor->ops->ctrl_data); + if (result) + dev_err(&client->dev, "%s:fail to active sensor\n", __func__); + + return result; +} + +static int sensor_init(struct i2c_client *client) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + struct device_node *np = client->dev.of_node; + int als_val = 0; + int val = 0; + int ret = 0; + + ret = sensor->ops->active(client, 0, 0); + if (ret) { + dev_err(&client->dev, "%s:sensor active fail\n", __func__); + return ret; + } + sensor->status_cur = SENSOR_OFF; + + ret = of_property_read_u32(np, "als_threshold_low", &als_val); + if (ret) + dev_err(&client->dev, "%s:Unable to read als_threshold_low\n", + __func__); + ret = sensor_write_reg(client, THDL1_ALS, + (unsigned char)(als_val >> 8)); + if (ret) { + dev_err(&client->dev, "%s:write THDL1_ALS fail\n", __func__); + return ret; + } + + ret = sensor_write_reg(client, THDL2_ALS, (unsigned char)als_val); + if (ret) { + dev_err(&client->dev, "%s:write THDL2_ALS fail\n", __func__); + return ret; + } + + ret = of_property_read_u32(np, "als_threshold_high", &als_val); + if (ret) + dev_err(&client->dev, "%s:Unable to read als_threshold_high\n", + __func__); + + ret = sensor_write_reg(client, THDH1_ALS, + (unsigned char)(als_val >> 8)); + if (ret) { + dev_err(&client->dev, "%s:write THDH1_ALS fail\n", __func__); + return ret; + } + + ret = sensor_write_reg(client, THDH2_ALS, (unsigned char)als_val); + if (ret) { + dev_err(&client->dev, "%s:write THDH2_ALS fail\n", __func__); + return ret; + } + + ret = of_property_read_u32(np, "als_ctrl_gain", &als_val); + if (ret) + dev_err(&client->dev, "%s:Unable to read als_ctrl_gain\n", + __func__); + + ret = sensor_write_reg(client, ALS_CTRL1, + (unsigned char)((als_val << 4) | ALS_REFT_MS)); + if (ret) { + dev_err(&client->dev, "%s:write ALS_CTRL fail\n", __func__); + return ret; + } + + val = sensor_read_reg(client, INT_CTRL1); + val &= ~INT_CTRL_PS_AND_LS; + if (sensor->pdata->irq_enable) + val |= ALS_INT_ENABLE; + else + val &= ~ALS_INT_ENABLE; + ret = sensor_write_reg(client, INT_CTRL1, val); + if (ret) { + dev_err(&client->dev, "%s:write INT_CTRL1 fail\n", __func__); + return ret; + } + + return ret; +} + +static int light_report_value(struct input_dev *input, int data) +{ + unsigned char index = 0; + + if (data <= 100) { + index = 0; + goto report; + } else if (data <= 1600) { + index = 1; + goto report; + } else if (data <= 2250) { + index = 2; + goto report; + } else if (data <= 3200) { + index = 3; + goto report; + } else if (data <= 6400) { + index = 4; + goto report; + } else if (data <= 12800) { + index = 5; + goto report; + } else if (data <= 26000) { + index = 6; + goto report; + } else { + index = 7; + goto report; + } + +report: + input_report_abs(input, ABS_MISC, index); + input_sync(input); + return index; +} + +static int sensor_report_value(struct i2c_client *client) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + int result = 0; + int value = 0; + int index = 0; + char buffer[2] = { 0 }; + + if (sensor->ops->read_len < 2) { + dev_err(&client->dev, "%s:length is error, len=%d\n", __func__, + sensor->ops->read_len); + return -EINVAL; + } + + buffer[0] = sensor->ops->read_reg; + result = sensor_rx_data(client, buffer, sensor->ops->read_len); + if (result) { + dev_err(&client->dev, "%s:sensor read data fail\n", __func__); + return result; + } + value = (buffer[0] << 8) | buffer[1]; + index = light_report_value(sensor->input_dev, value); + dev_dbg(&client->dev, "%s result=0x%x, index=%d\n", + sensor->ops->name, value, index); + + if (sensor->pdata->irq_enable && sensor->ops->int_status_reg) { + value = sensor_read_reg(client, sensor->ops->int_status_reg); + if (value & STK_FLAG_ALS_INT) { + value &= ~STK_FLAG_ALS_INT; + result = sensor_write_reg(client, + sensor->ops->int_status_reg, + value); + if (result) { + dev_err(&client->dev, "write status reg error\n"); + return result; + } + } + } + + return result; +} + +static struct sensor_operate light_stk33562_ops = { + .name = "ls_stk33562", + .type = SENSOR_TYPE_LIGHT, + .id_i2c = LIGHT_ID_STK33562, + .read_reg = DATA1_ALS, + .read_len = 2, + .id_reg = SENSOR_UNKNOW_DATA, + .id_data = SENSOR_UNKNOW_DATA, + .precision = 16, + .ctrl_reg = STK_STATE, + .int_status_reg = STK_FLAG, + .range = { 100, 65535 }, + .brightness = { 10, 255 }, + .trig = IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED, + .active = sensor_active, + .init = sensor_init, + .report = sensor_report_value, +}; + +static int light_stk33562_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + return sensor_register_device(client, NULL, devid, &light_stk33562_ops); +} + +static void light_stk33562_remove(struct i2c_client *client) +{ + sensor_unregister_device(client, NULL, &light_stk33562_ops); +} + +static const struct i2c_device_id light_stk33562_id[] = { + { "ls_stk33562", LIGHT_ID_STK33562 }, + {} +}; + +static struct i2c_driver light_stk33562_driver = { + .probe = light_stk33562_probe, + .remove = (void *)light_stk33562_remove, + .shutdown = sensor_shutdown, + .id_table = light_stk33562_id, + .driver = { + .name = "light_stk33562", +#ifdef CONFIG_PM + .pm = &sensor_pm_ops, +#endif + }, +}; + +module_i2c_driver(light_stk33562_driver); + +MODULE_AUTHOR("Alex Zhao "); +MODULE_DESCRIPTION("stk33562 light driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/sensors/psensor/Kconfig b/drivers/input/sensors/psensor/Kconfig index 62ed3ac8eefa..3e7ee7f86b62 100644 --- a/drivers/input/sensors/psensor/Kconfig +++ b/drivers/input/sensors/psensor/Kconfig @@ -28,6 +28,10 @@ config PS_STK3410 tristate "proximity sensor stk3410" default n +config PS_STK33562 + tristate "proximity sensor stk33562" + default n + config PS_EM3071X tristate "proximity sensor em3071x" diff --git a/drivers/input/sensors/psensor/Makefile b/drivers/input/sensors/psensor/Makefile index 365f9cdd3cdd..20997dd31dad 100644 --- a/drivers/input/sensors/psensor/Makefile +++ b/drivers/input/sensors/psensor/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_PS_STK3171) += ps_stk3171.o obj-$(CONFIG_PS_AP321XX) += ps_ap321xx.o obj-$(CONFIG_PS_STK3332) += ps_stk3332.o obj-$(CONFIG_PS_STK3410) += ps_stk3410.o +obj-$(CONFIG_PS_STK33562) += ps_stk33562.o obj-$(CONFIG_PS_EM3071X) += ps_em3071x.o obj-$(CONFIG_PS_UCS14620) += ps_ucs14620.o diff --git a/drivers/input/sensors/psensor/ps_stk33562.c b/drivers/input/sensors/psensor/ps_stk33562.c new file mode 100644 index 000000000000..30ccc13d4e8b --- /dev/null +++ b/drivers/input/sensors/psensor/ps_stk33562.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: Alex Zhao + */ +#include +#include +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CONTROL REGISTER MAP */ +#define STK_STATE 0x00 +#define PS_CTRL 0x01 +#define ALS_CTRL1 0x02 +#define LED_CTRL 0x03 +#define INT_CTRL1 0x04 +#define STK_WAIT 0x05 +#define THDH1_PS 0x06 +#define THDH2_PS 0x07 +#define THDL1_PS 0x08 +#define THDL2_PS 0x09 +#define THDH1_ALS 0x0A +#define THDH2_ALS 0x0B +#define THDL1_ALS 0x0C +#define THDL2_ALS 0x0D +#define STK_FLAG 0x10 +#define DATA1_PS 0x11 +#define DATA2_PS 0x12 +#define DATA1_ALS 0x13 +#define DATA2_ALS 0x14 +#define DATA1_ALS1 0x17 +#define DATA2_ALS1 0x18 +#define DATA1_C 0x1B +#define DATA2_C 0x1C +#define DATA1_PS_OFFSET 0x1D +#define DATA2_PS_OFFSET 0x1E +#define STKPDT_ID 0x3E +#define STK_RESERVED 0x3F +#define GAIN_CTRL 0x4E +#define SOFT_RESET 0x80 +#define PSPD_CTRL 0xA1 +#define INT_CTRL2 0xA5 + +/* STK_STATE 0x00 */ +#define PS_DISABLE (0 << 0) +#define PS_ENABLE (1 << 0) +#define ALS_DISABLE (0 << 1) +#define ALS_ENABLE (1 << 1) +#define WAIT_DISABLE (0 << 2) +#define WAIT_ENABLE (1 << 2) + +/* PSCTRL 0x01 */ +#define PS_IT_96US (0 << 0) +#define PS_IT_192US (1 << 0) +#define PS_IT_384US (2 << 0) +#define PS_IT_768US (3 << 0) +#define PS_IT_1MS54 (4 << 0) +#define PS_IT_3MS07 (5 << 0) +#define PS_IT_6MS14 (6 << 0) + +#define PS_GAIN_1G (0 << 4) +#define PS_GAIN_2G (1 << 4) +#define PS_GAIN_4G (2 << 4) +#define PS_GAIN_8G (3 << 4) + +#define PS_PRST_1T (0 << 6) +#define PS_PRST_2T (1 << 6) +#define PS_PRST_4T (2 << 6) +#define PS_PRST_8T (3 << 6) + +/* ALS_CTRL1 0x02 */ +#define ALS_REFT_MS (1 << 0)/* [3:0] 25 ms, default value is 100ms */ + +#define ALS_GAIN_1G (0 << 4) +#define ALS_GAIN_4G (1 << 4) +#define ALS_GAIN_16G (2 << 4) +#define ALS_GAIN_64G (3 << 4) + +#define ALS_PRST_1T (0 << 6) +#define ALS_PRST_2T (1 << 6) +#define ALS_PRST_4T (2 << 6) +#define ALS_PRST_8T (3 << 6) + +/* LED_CTRL 0x03 */ +#define LED_CTIR_EN 0x03 /* [5:0] 2.89us , default value is 0.185ms */ +#define CTIR_DISABLE (0 << 0) +#define CTIR_ENABLE (1 << 0) +#define CTIRFC_DISABLE (0 << 1) +#define CTIRFC_ENABLE (1 << 1) + +#define LED_CUR_3_125MA (0 << 4) +#define LED_CUR_6_25MA (1 << 4) +#define LED_CUR_12_5MA (2 << 4) +#define LED_CUR_25MA (3 << 4) +#define LED_CUR_50MA (4 << 4) +#define LED_CUR_75MA (5 << 4) +#define LED_CUR_100MA (6 << 4) +#define LED_CUR_125MA (7 << 4) +#define LED_CUR_150MA (8 << 4) +#define LED_CUR_175MA (9 << 4) +#define LED_CUR_200MA (a << 4) + +/* INTCTRL1 0x04 */ +#define PS_INT_DISABLE (0 << 0) +#define PS_INT_ENABLE (1 << 0) +#define PS_INT_ENABLE_FLGNFH (2 << 0) +#define PS_INT_ENABLE_FLGNFL (3 << 0) +#define PS_INT_MODE_ENABLE (4 << 0) +#define PS_INT_ENABLE_THL (5 << 0) +#define PS_INT_ENABLE_THH (6 << 0) +#define PS_INT_ENABLE_THHL (7 << 0) +#define ALS_INT_DISABLE (0 << 3) +#define ALS_INT_ENABLE (1 << 3) +#define INT_CTRL_PS_OR_LS (0 << 7) +#define INT_CTRL_PS_AND_LS (1 << 7) + +/* FLAG 0x10 */ +#define STK_FLAG_NF (1 << 0) +#define STK_FLAG_INPS_INT (1 << 1) +#define STK_FLAG_ALS_STATE (1 << 2) +#define STK_FLAG_PS_INT (1 << 4) +#define STK_FLAG_ALS_INT (1 << 5) +#define STK_FLAG_PSDR (1 << 6) +#define STK_FLAG_ALSDR (1 << 7) + +static int ps_threshold_low; +static int ps_threshold_high; +static int val_flag; + +static int sensor_active(struct i2c_client *client, int enable, int rate) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + int result = 0; + int status = 0; + + sensor->ops->ctrl_data = sensor_read_reg(client, sensor->ops->ctrl_reg); + if (!enable) { + status = ~PS_ENABLE; + sensor->ops->ctrl_data &= status; + } else { + status = PS_ENABLE; + sensor->ops->ctrl_data |= status; + } + + dev_dbg(&client->dev, "reg=0x%x, reg_ctrl=0x%x, enable=%d\n", + sensor->ops->ctrl_reg, sensor->ops->ctrl_data, enable); + + result = sensor_write_reg(client, sensor->ops->ctrl_reg, + sensor->ops->ctrl_data); + if (result) + dev_err(&client->dev, "%s:fail to active sensor\n", __func__); + + return result; +} + +static int sensor_init(struct i2c_client *client) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + struct device_node *np = client->dev.of_node; + int ps_val = 0; + int result = 0; + int val = 0; + + result = sensor->ops->active(client, 0, 0); + if (result) { + dev_err(&client->dev, "%s:sensor active fail\n", __func__); + return result; + } + sensor->status_cur = SENSOR_OFF; + + result = of_property_read_u32(np, "ps_threshold_low", &ps_val); + if (result) + dev_err(&client->dev, "%s:Unable to read ps_threshold_low\n", + __func__); + + ps_threshold_low = ps_val; + result = sensor_write_reg(client, THDL1_PS, + (unsigned char)(ps_val >> 8)); + if (result) { + dev_err(&client->dev, "%s:write THDL1_PS fail\n", __func__); + return result; + } + result = sensor_write_reg(client, THDL2_PS, (unsigned char)ps_val); + if (result) { + dev_err(&client->dev, "%s:write THDL1_PS fail\n", __func__); + return result; + } + + result = of_property_read_u32(np, "ps_threshold_high", &ps_val); + if (result) + dev_err(&client->dev, "%s:Unable to read ps_threshold_high\n", + __func__); + + ps_threshold_high = ps_val; + result = sensor_write_reg(client, THDH1_PS, + (unsigned char)(ps_val >> 8)); + if (result) { + dev_err(&client->dev, "%s:write THDH1_PS fail\n", __func__); + return result; + } + + result = sensor_write_reg(client, THDH2_PS, (unsigned char)ps_val); + if (result) { + dev_err(&client->dev, "%s:write THDH1_PS fail\n", __func__); + return result; + } + + result = of_property_read_u32(np, "ps_ctrl_gain", &ps_val); + if (result) + dev_err(&client->dev, "%s:Unable to read ps_ctrl_gain\n", + __func__); + + result = sensor_write_reg(client, PS_CTRL, + (unsigned char)((ps_val << 4) | PS_IT_384US)); + if (result) { + dev_err(&client->dev, "%s:write PS_CTRL fail\n", __func__); + return result; + } + + result = of_property_read_u32(np, "ps_led_current", &ps_val); + if (result) + dev_err(&client->dev, "%s:Unable to read ps_led_current\n", + __func__); + + result = sensor_write_reg(client, LED_CTRL, + (unsigned char)((ps_val << 5) | LED_CTIR_EN)); + if (result) { + dev_err(&client->dev, "%s:write LED_CTRL fail\n", __func__); + return result; + } + + val = sensor_read_reg(client, INT_CTRL1); + val &= ~INT_CTRL_PS_AND_LS; + if (sensor->pdata->irq_enable) + val |= PS_INT_ENABLE_FLGNFL; + else + val &= PS_INT_DISABLE; + result = sensor_write_reg(client, INT_CTRL1, val); + if (result) { + dev_err(&client->dev, "%s:write INT_CTRL fail\n", __func__); + return result; + } + + return result; +} + +static int stk33562_get_ps_value(int ps) +{ + int index = 0; + + if ((ps > ps_threshold_high) && (val_flag == 0)) { + index = 1; + val_flag = 1; + } else if ((ps < ps_threshold_low) && (val_flag == 1)) { + index = 0; + val_flag = 0; + } else { + index = -1; + } + + return index; +} + +static int sensor_report_value(struct i2c_client *client) +{ + struct sensor_private_data *sensor = + (struct sensor_private_data *)i2c_get_clientdata(client); + int result = 0; + int value = 0; + char buffer[2] = { 0 }; + int index = 1; + + if (sensor->ops->read_len < 2) { + dev_err(&client->dev, "%s:length is error, len=%d\n", __func__, + sensor->ops->read_len); + return -EINVAL; + } + + buffer[0] = sensor->ops->read_reg; + result = sensor_rx_data(client, buffer, sensor->ops->read_len); + if (result) { + dev_err(&client->dev, "%s:sensor read data fail\n", __func__); + return result; + } + value = (buffer[0] << 8) | buffer[1]; + + if (sensor->pdata->irq_enable && sensor->ops->int_status_reg) { + value = sensor_read_reg(client, sensor->ops->int_status_reg); + if (value & STK_FLAG_NF) + index = 0; + else + index = 1; + input_report_abs(sensor->input_dev, ABS_DISTANCE, index); + input_sync(sensor->input_dev); + value &= ~STK_FLAG_PS_INT; + result = sensor_write_reg(client, + sensor->ops->int_status_reg, + value); + + dev_dbg(&client->dev, "%s object near = %d", sensor->ops->name, index); + + if (result) { + dev_err(&client->dev, "write status reg error\n"); + return result; + } + } else if (!sensor->pdata->irq_enable) { + index = stk33562_get_ps_value(value); + if (index >= 0) { + input_report_abs(sensor->input_dev, ABS_DISTANCE, index); + input_sync(sensor->input_dev); + dev_dbg(&client->dev, "%s sensor closed=%d\n", + sensor->ops->name, index); + } + } + + return result; +} + +static struct sensor_operate psensor_stk33562_ops = { + .name = "ps_stk33562", + .type = SENSOR_TYPE_PROXIMITY, + .id_i2c = PROXIMITY_ID_STK33562, + .read_reg = DATA1_PS, + .read_len = 2, + .id_reg = SENSOR_UNKNOW_DATA, + .id_data = SENSOR_UNKNOW_DATA, + .precision = 16, + .ctrl_reg = STK_STATE, + .int_status_reg = STK_FLAG, + .range = { 100, 65535 }, + .brightness = { 10, 255 }, + .trig = IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED, + .active = sensor_active, + .init = sensor_init, + .report = sensor_report_value, +}; + +static int proximity_stk33562_probe(struct i2c_client *client, + const struct i2c_device_id *devid) +{ + return sensor_register_device(client, NULL, devid, &psensor_stk33562_ops); +} + +static void proximity_stk33562_remove(struct i2c_client *client) +{ + sensor_unregister_device(client, NULL, &psensor_stk33562_ops); +} + +static const struct i2c_device_id proximity_stk33562_id[] = { + { "ps_stk33562", PROXIMITY_ID_STK33562 }, + {} +}; + +static struct i2c_driver proximity_stk33562_driver = { + .probe = proximity_stk33562_probe, + .remove = (void *)proximity_stk33562_remove, + .shutdown = sensor_shutdown, + .id_table = proximity_stk33562_id, + .driver = { + .name = "proximity_stk33562", +#ifdef CONFIG_PM + .pm = &sensor_pm_ops, +#endif + }, +}; + +module_i2c_driver(proximity_stk33562_driver); + +MODULE_AUTHOR("Alex Zhao "); +MODULE_DESCRIPTION("stk33562 proximity driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/rockchip/vpss/vpss.c b/drivers/media/platform/rockchip/vpss/vpss.c index f2637ec6a446..1e6af137348a 100644 --- a/drivers/media/platform/rockchip/vpss/vpss.c +++ b/drivers/media/platform/rockchip/vpss/vpss.c @@ -480,6 +480,7 @@ int rkvpss_register_subdev(struct rkvpss_device *dev, int ret; spin_lock_init(&dev->cmsc_lock); + spin_lock_init(&dev->idle_lock); memset(vpss_sdev, 0, sizeof(*vpss_sdev)); vpss_sdev->dev = dev; sd = &vpss_sdev->sd; diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c index e1d5d3330c64..5dfce987edc6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c @@ -700,6 +700,45 @@ static int rockchip_pcie_deinit_host(struct rockchip_pcie *rockchip) return 0; } +/* + * ATS does not work on platform like rk3588 when running in EP mode. + * After a host has enabled ATS on the EP side, it will send an IOTLB + * invalidation request to the EP side. The rk3588 will never send a completion + * back and eventually the host will print an IOTLB_INV_TIMEOUT error, and the + * EP will not be operational. If we hide the ATS cap, things work as expected. + */ +static void rockchip_pcie_hide_broken_ats_cap(struct dw_pcie *pci) +{ + struct device *dev = pci->dev; + unsigned int spcie_cap_offset, next_cap_offset; + u32 spcie_cap_header, next_cap_header; + + /* only hide the ATS cap for rk3588 running in EP mode */ + if (!of_device_is_compatible(dev->of_node, "rockchip,rk3588-pcie-std-ep")) + return; + + spcie_cap_offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI); + if (!spcie_cap_offset) + return; + + spcie_cap_header = dw_pcie_readl_dbi(pci, spcie_cap_offset); + next_cap_offset = PCI_EXT_CAP_NEXT(spcie_cap_header); + + next_cap_header = dw_pcie_readl_dbi(pci, next_cap_offset); + if (PCI_EXT_CAP_ID(next_cap_header) != PCI_EXT_CAP_ID_ATS) + return; + + /* clear next ptr */ + spcie_cap_header &= ~GENMASK(31, 20); + + /* set next ptr to next ptr of ATS_CAP */ + spcie_cap_header |= next_cap_header & GENMASK(31, 20); + + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, spcie_cap_offset, spcie_cap_header); + dw_pcie_dbi_ro_wr_dis(pci); +} + static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->pci.dev; @@ -717,6 +756,8 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip) dw_pcie_setup(&rockchip->pci); + rockchip_pcie_hide_broken_ats_cap(pci); + dw_pcie_dbi_ro_wr_en(&rockchip->pci); /* Enable bus master and memory space */ dw_pcie_writel_dbi(pci, PCIE_TYPE0_STATUS_COMMAND_REG, 0x6); diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index b61ceabcee34..b92ac36772bd 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -2036,6 +2036,7 @@ int rockchip_dw_pcie_pm_ctrl_for_user(struct pci_dev *dev, enum rockchip_pcie_pm struct dw_pcie_rp *pp; struct dw_pcie *pci; struct rk_pcie *rk_pcie; + u32 intr_mask; if (!dev || !dev->bus || !dev->bus->sysdata) { pr_err("%s input invalid\n", __func__); @@ -2048,8 +2049,16 @@ int rockchip_dw_pcie_pm_ctrl_for_user(struct pci_dev *dev, enum rockchip_pcie_pm switch (flag) { case ROCKCHIP_PCIE_PM_CTRL_RESET: + /* + * suspend and resume should be called in noirq context, masking and + * unmasking local irq to prevent hunging for accessing died controller + * if serving irq, for instance, hot reset case. + */ + intr_mask = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_MASK); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xffffffff); rockchip_dw_pcie_suspend(rk_pcie->pci->dev); rockchip_dw_pcie_resume(rk_pcie->pci->dev); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, intr_mask | 0xffff0000); break; case ROCKCHIP_PCIE_PM_RETRAIN_LINK: rk_pcie_retrain(pci); diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 68d8d6ac2ed3..c6ba6f6732b3 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -333,6 +333,7 @@ struct rockchip_hdptx_phy { struct regmap *regmap; struct regmap *grf; u32 lane_polarity_invert[4]; + bool dp_mode; }; enum { @@ -543,6 +544,62 @@ static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = { } }; +static struct tx_drv_ctrl tx_drv_ctrl_rbr_dp_mode[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x0, 0x2, 0x2, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xd, 0xb, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x4, 0x0, 0x4, 0x4, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xc, 0x5, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + } +}; + +static struct tx_drv_ctrl tx_drv_ctrl_hbr_dp_mode[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x0, 0x1, 0x1, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xd, 0xc, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x6, 0x1, 0x2, 0x2, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xd, 0x6, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + } +}; + /* pll configurations for link rate R216/R243/R324/R432 */ static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = { { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */ @@ -597,6 +654,10 @@ static int rockchip_grf_write(struct regmap *grf, unsigned int reg, static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { + struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy); + + hdptx->dp_mode = (submode == PHY_SUBMODE_DP); + return 0; } @@ -651,7 +712,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, switch (dp->link_rate) { case 1620: - ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; + if (hdptx->dp_mode) + ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]]; + else + ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_RBR, FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); @@ -676,7 +740,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl)); break; case 2700: - ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; + if (hdptx->dp_mode) + ctrl = &tx_drv_ctrl_hbr_dp_mode[dp->voltage[lane]][dp->pre[lane]]; + else + ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_HBR, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); @@ -1434,8 +1501,10 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev) "failed to create regmap\n"); ret = devm_clk_bulk_get_all(dev, &hdptx->clks); - if (ret < 1) - return dev_err_probe(dev, ret, "failed to get clocks\n"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + if (ret == 0) + return dev_err_probe(dev, -EINVAL, "Missing clocks\n"); hdptx->nr_clks = ret; diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig index 936f52e0e682..aa94a31a8d5e 100644 --- a/drivers/soc/rockchip/Kconfig +++ b/drivers/soc/rockchip/Kconfig @@ -72,6 +72,12 @@ config ROCKCHIP_HW_DECOMPRESS This driver support Decompress IP built-in Rockchip SoC, support LZ4, GZIP, ZLIB. +config ROCKCHIP_HW_DECOMPRESS_TEST + bool "Rockchip Hw-Decompress test" + depends on ROCKCHIP_HW_DECOMPRESS + help + Say yes here to enable decompress test + config ROCKCHIP_HW_DECOMPRESS_USER tristate "Rockchip HardWare Decompress User Interface Support" default n diff --git a/drivers/soc/rockchip/rockchip_decompress.c b/drivers/soc/rockchip/rockchip_decompress.c index afabee1f66d9..7494ea2ceef7 100644 --- a/drivers/soc/rockchip/rockchip_decompress.c +++ b/drivers/soc/rockchip/rockchip_decompress.c @@ -244,7 +244,9 @@ static irqreturn_t rk_decom_irq_handler(int irq, void *priv) g_decom_noblocking = false; wake_up(&g_decom_wait); } else { +#ifndef CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST writel(DECOM_ENABLE, rk_dec->regs + DECOM_ENR); +#endif } } } @@ -254,6 +256,7 @@ static irqreturn_t rk_decom_irq_handler(int irq, void *priv) static irqreturn_t rk_decom_irq_thread(int irq, void *priv) { +#ifndef CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST struct rk_decom *rk_dec = priv; if (g_decom_complete) { @@ -273,9 +276,54 @@ static irqreturn_t rk_decom_irq_thread(int irq, void *priv) clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks); } +#endif return IRQ_HANDLED; } +#ifdef CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST +static ssize_t start_decom_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u32 mode = 0; + phys_addr_t src, dst; + int ret; + struct rk_decom *rk_dec = dev_get_drvdata(dev); + + src = rk_dec->mem_start; + dst = rk_dec->mem_start + rk_dec->mem_size / 2; + + if (src == 0x0 || dst == 0x0) + return -EINVAL; + + ret = kstrtou32(buf, 10, &mode); + if (ret) + return ret; + + if (mode != LZ4_MOD && mode != GZIP_MOD && mode != ZLIB_MOD) + return -EINVAL; + + dev_info(dev, "%s,%d, src = %pa, dst = %pa, mode = %d\n", + __func__, __LINE__, &src, &dst, mode); + + ret = rk_decom_start(mode, src, dst, 0x80000000); + if (ret) + pr_info("%s, user decompress error\n", __func__); + + return size; +} + +static DEVICE_ATTR_WO(start_decom); +static struct attribute *decom_attrs[] = { + &dev_attr_start_decom.attr, + NULL +}; + +static const struct attribute_group decom_attr_group = { + .attrs = decom_attrs, +}; +#endif + static int __init rockchip_decom_probe(struct platform_device *pdev) { struct rk_decom *rk_dec; @@ -346,6 +394,13 @@ static int __init rockchip_decom_probe(struct platform_device *pdev) goto disable_clk; } +#ifdef CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST + ret = sysfs_create_group(&pdev->dev.kobj, &decom_attr_group); + if (ret) { + dev_err(dev, "SysFS group creation failed\n"); + return ret; + } +#endif g_decom = rk_dec; wake_up(&decom_init_done); diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h index 100558e56d17..35484105d7f0 100644 --- a/include/drm/bridge/analogix_dp.h +++ b/include/drm/bridge/analogix_dp.h @@ -43,6 +43,7 @@ struct analogix_dp_plat_data { struct drm_connector *connector; bool skip_connector; bool ssc; + bool support_dp_mode; bool split_mode; bool dual_channel_mode; diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h index 20dbece78cf9..b6196c138698 100644 --- a/include/linux/rockchip/rockchip_sip.h +++ b/include/linux/rockchip/rockchip_sip.h @@ -59,6 +59,7 @@ #define SIP_HDMIRX_CFG 0x82000027 #define SIP_MCU_CFG 0x82000028 #define SIP_PVTPLL_CFG 0x82000029 +#define SIP_GPIO_CFG 0x8200002c #define TRUSTED_OS_HDCPKEY_INIT 0xB7000003 @@ -249,6 +250,13 @@ enum { PVTPLL_VOLT_SEL = 3, }; +/* SIP_GPIO_CFG child configs */ +enum { + GPIO_GET_GROUP_INFO = 0, + GPIO_SET_GROUP_INFO = 1, + GPIO_GET_VIRT_EN = 2, +}; + struct pt_regs; typedef void (*sip_fiq_debugger_uart_irq_tf_cb_t)(struct pt_regs *_pt_regs, unsigned long cpu); @@ -286,6 +294,8 @@ struct arm_smccc_res sip_smc_pvtpll_config(u32 sub_func_id, u32 arg1, u32 arg2, void __iomem *sip_hdcp_request_share_memory(int id); struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2); +struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1, u32 arg2, + u32 arg3); ulong sip_cpu_logical_map_mpidr(u32 cpu); /***************************fiq debugger **************************************/ void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu); @@ -429,6 +439,14 @@ static inline struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2) return tmp; } +static inline struct arm_smccc_res sip_smc_gpio_config(u32 sub_func_id, u32 arg1, + u32 arg2, u32 arg3) +{ + struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, }; + + return tmp; +} + static inline ulong sip_cpu_logical_map_mpidr(u32 cpu) { return 0; } /***************************fiq debugger **************************************/ diff --git a/include/linux/sensor-dev.h b/include/linux/sensor-dev.h index e64676f2d967..bfe204ca3062 100644 --- a/include/linux/sensor-dev.h +++ b/include/linux/sensor-dev.h @@ -113,6 +113,7 @@ enum sensor_id { LIGHT_ID_STK3410, LIGHT_ID_EM3071X, LIGHT_ID_UCS14620, + LIGHT_ID_STK33562, PROXIMITY_ID_ALL, PROXIMITY_ID_AL3006, @@ -122,6 +123,7 @@ enum sensor_id { PROXIMITY_ID_STK3410, PROXIMITY_ID_EM3071X, PROXIMITY_ID_UCS14620, + PROXIMITY_ID_STK33562, TEMPERATURE_ID_ALL, TEMPERATURE_ID_MS5607,