From f9bd0486a11da4f290debbf4ec1ba5d24c61c302 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Thu, 18 Nov 2021 08:33:47 +0800 Subject: [PATCH] clk: rockchip: rk3588: Add audio fracpll freq This patch adds more audio fracpll freq around 800M. 786432000 for SR: 8k, 16k, 24k, 48k, 96k, 192k 722534400 for SR: 11.025k 22.05k, 44.1k, 88.2k, 176.4k According to CRU Chapter: +------------+---------------------------------------------------------+ | PLL Type | Equation | +------------+---------------------------------------------------------+ | FRACPLL | FFVCO = ((m + k / 65536) * FFIN) / p | | | FFOUT = FFVCO / 2^s | +------------+---------------------------------------------------------+ e.g. to achieve PLL rate: 786432000 step1: equation: FFVCO = FFOUT * 2^s to get VCO as much higher as possible in ranges for better jitter performance. FFVCO = 786432000 * 2^2 = 3145728000 step2: equation: ref = FFIN / P, (m + k / 65536) = FFVCO / ref ref should be as much higher as possible for better jitter performance. we can try to iterate from high freq to low to find the best parameter. step3: the final FFOUT should be measured by devices, sush as frequency counter. RK3588_PLL_RATE(786432000, 2, 262, 2, 9437) RK3588_PLL_RATE(722534400, 8, 963, 2, 24850) +------------------------------------------------------------------------+ | MHz | 1~63 | 64~1024 | 0~6 | 0~65535 | | 2250~4500 | 36~4500 | +------------------------------------------------------------------------+ | FFIN | p | m | s | k | ref | FFVCO | FFOUT | +------------------------------------------------------------------------+ | 24 | 2 | 262 | 2 | 9437 | 12 | 3145.727993 | 786.431998 | +------------------------------------------------------------------------+ | 24 | 8 | 963 | 2 | 24850 | 3 | 2890.137560 | 722.534390 | +------------------------------------------------------------------------+ Target freq measured by KEYSIGHT-53220A (Universal Frequency Counter) +------------+---------------------+---------------------+-------------+ | PLL (MHz) | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) | +------------+---------------------+---------------------+-------------+ | 786.432000 | 49.152000 | 49.151360 | 13 | +------------+---------------------+---------------------+-------------+ | 786.432000 | 12.288000 | 12.287841 | 13 | +------------+---------------------+---------------------+-------------+ | 722.534400 | 45.158400 | 45.157816 | 13 | +------------+---------------------+---------------------+-------------+ | 722.534400 | 11.289600 | 11.289453 | 13 | +------------+---------------------+---------------------+-------------+ And this patch also fix freq for 983.04M and 903.168M. Before: RK3588_PLL_RATE(983040000, 3, 491, 2, 34078) RK3588_PLL_RATE(903168000, 3, 451, 2, 38272) +------------+---------------------+---------------------+-------------+ | PLL (MHz) | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) | +------------+---------------------+---------------------+-------------+ | 983.040000 | 49.152000 | 49.051368 | 2047 | +------------+---------------------+---------------------+-------------+ | 983.040000 | 12.288000 | 12.262841 | 2047 | +------------+---------------------+---------------------+-------------+ | 903.168000 | 45.158400 | 45.057819 | 2227 | +------------+---------------------+---------------------+-------------+ | 903.168000 | 11.289600 | 11.264454 | 2227 | +------------+---------------------+---------------------+-------------+ After: RK3588_PLL_RATE(983040000, 4, 655, 2, 23592) RK3588_PLL_RATE(903168000, 6, 903, 2, 11009) +------------+---------------------+---------------------+-------------+ | PLL (MHz) | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) | +------------+---------------------+---------------------+-------------+ | 983.040000 | 49.152000 | 49.151367 | 13 | +------------+---------------------+---------------------+-------------+ | 983.040000 | 12.288000 | 12.287841 | 13 | +------------+---------------------+---------------------+-------------+ | 903.168000 | 45.158400 | 45.157818 | 13 | +------------+---------------------+---------------------+-------------+ | 903.168000 | 11.289600 | 11.289454 | 13 | +------------+---------------------+---------------------+-------------+ Fixes: 72c304699f38 ("clk: rockchip: rk3588: Add audio fracpll freq") Signed-off-by: Sugar Zhang Change-Id: Iacc74d135efacef5b6b65d30bdf235ceec0fe970 --- drivers/clk/rockchip/clk-rk3588.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6c748f13c503..2958e18a077e 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -76,11 +76,13 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), - RK3588_PLL_RATE(983040000, 3, 491, 2, 34078), - RK3588_PLL_RATE(903168000, 3, 451, 2, 38272), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), RK3588_PLL_RATE(900000000, 2, 300, 2, 0), RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), RK3588_PLL_RATE(600000000, 2, 200, 2, 0), RK3588_PLL_RATE(594000000, 2, 198, 2, 0), RK3588_PLL_RATE(408000000, 2, 272, 3, 0),