From ee672f753b6cdfd1839d5e74989ecc73427af475 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 27 Aug 2024 10:53:27 +0800 Subject: [PATCH 01/16] media: rockchip: flexbus_cif: Add MODULE_IMPORT_NS(DMA_BUF) ERROR: modpost: module flexbus_cif uses symbol dma_buf_put from namespace DMA_BUF, but does not import it. ERROR: modpost: module flexbus_cif uses symbol dma_buf_fd from namespace DMA_BUF, but does not import it. Signed-off-by: Tao Huang Change-Id: I3a512a9b4efc899dc16b61b6cbc867d5cabe70d1 --- drivers/media/platform/rockchip/flexbus_cif/common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/rockchip/flexbus_cif/common.c b/drivers/media/platform/rockchip/flexbus_cif/common.c index 282c5b49393e..ab153d1ff6fb 100644 --- a/drivers/media/platform/rockchip/flexbus_cif/common.c +++ b/drivers/media/platform/rockchip/flexbus_cif/common.c @@ -11,6 +11,8 @@ #include "dev.h" #include "common.h" +MODULE_IMPORT_NS(DMA_BUF); + static void flexbus_cif_init_dummy_vb2(struct flexbus_cif_device *dev, struct flexbus_cif_dummy_buffer *buf) { From 70046cbf8490e824680141889e5394a105ee2fa0 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 27 Aug 2024 11:24:44 +0800 Subject: [PATCH 02/16] ARM: rk3506_defconfig: Disable CONFIG_ROCKCHIP_CLK_INV/PVTM/CONFIG_ROCKCHIP_PVTM Signed-off-by: Tao Huang Change-Id: If22b930f24fa99b41d6e8ef7bdab3e63c9d35734 --- arch/arm/configs/rk3506_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 041bdd3e38c8..8af6cc241401 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -282,13 +282,14 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set CONFIG_STAGING=y +# CONFIG_ROCKCHIP_CLK_INV is not set CONFIG_ROCKCHIP_CLK_OUT=y +# CONFIG_ROCKCHIP_CLK_PVTM is not set # CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_CPU_RK3506=y CONFIG_ROCKCHIP_CPUINFO=y CONFIG_ROCKCHIP_OPP=y -CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_SUSPEND_MODE=y CONFIG_ROCKCHIP_SYSTEM_MONITOR=y CONFIG_FIQ_DEBUGGER=y From 6732e1af29e7a264656289f514616454d18c2a19 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Mon, 26 Aug 2024 14:18:22 +0800 Subject: [PATCH 03/16] exfat: fix memory leak in exfat_load_bitmap() Signed-off-by: Yifeng Zhao Change-Id: I50523d98e269dea3837bc520a7588bf245a01cd3 --- fs/exfat/balloc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fs/exfat/balloc.c b/fs/exfat/balloc.c index e918decb3735..54e93db1621a 100644 --- a/fs/exfat/balloc.c +++ b/fs/exfat/balloc.c @@ -110,10 +110,14 @@ int exfat_load_bitmap(struct super_block *sb) return -EIO; type = exfat_get_entry_type(ep); - if (type == TYPE_UNUSED) + if (type == TYPE_UNUSED) { + brelse(bh); break; - if (type != TYPE_BITMAP) + } + if (type != TYPE_BITMAP) { + brelse(bh); continue; + } if (ep->dentry.bitmap.flags == 0x0) { int err; From 818669da278a2401fbb12a8be90fb973ba453911 Mon Sep 17 00:00:00 2001 From: XiaoTan Luo Date: Fri, 23 Aug 2024 15:19:56 +0800 Subject: [PATCH 04/16] ASoC: rockchip: multicodecs: add tdm support Signed-off-by: XiaoTan Luo Change-Id: I7fccc0ad5214399b0354899f2a5f81b2f16161b7 --- sound/soc/rockchip/rockchip_multicodecs.c | 41 ++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/sound/soc/rockchip/rockchip_multicodecs.c b/sound/soc/rockchip/rockchip_multicodecs.c index 0b182191f72d..8c3bb17f2056 100644 --- a/sound/soc/rockchip/rockchip_multicodecs.c +++ b/sound/soc/rockchip/rockchip_multicodecs.c @@ -76,6 +76,10 @@ struct multicodecs_data { const struct adc_keys_button *map; struct input_dev *input; struct input_dev_poller *poller; + int slots; + int slot_width; + unsigned int tx_slot_mask; + unsigned int rx_slot_mask; }; static const unsigned int headset_extcon_cable[] = { @@ -399,7 +403,9 @@ static int rk_dailink_init(struct snd_soc_pcm_runtime *rtd) struct multicodecs_data *mc_data = snd_soc_card_get_drvdata(rtd->card); struct snd_soc_card *card = rtd->card; struct snd_soc_jack *jack_headset; - int ret, irq; + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai; + int ret, irq, i; struct snd_soc_jack_pin *pins; struct snd_soc_jack_zone *zones; struct snd_soc_jack_pin jack_pins[] = { @@ -427,6 +433,30 @@ static int rk_dailink_init(struct snd_soc_pcm_runtime *rtd) } }; + if (mc_data->slots) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, + mc_data->tx_slot_mask, + mc_data->rx_slot_mask, + mc_data->slots, + mc_data->slot_width); + if (ret && ret != -EOPNOTSUPP) { + dev_err(card->dev, "cpu_dai: set_tdm_slot error\n"); + return ret; + } + + for_each_rtd_codec_dais(rtd, i, codec_dai) { + ret = snd_soc_dai_set_tdm_slot(codec_dai, + mc_data->tx_slot_mask, + mc_data->rx_slot_mask, + mc_data->slots, + mc_data->slot_width); + if (ret && ret != -EOPNOTSUPP) { + dev_err(card->dev, "codec_dai: set_tdm_slot error\n"); + return ret; + } + } + } + if ((!mc_data->codec_hp_det) && (gpiod_to_irq(mc_data->hp_det_gpio) < 0)) { dev_info(card->dev, "Don't need to map headset detect gpio to irq\n"); return 0; @@ -804,6 +834,15 @@ static int rk_multicodecs_probe(struct platform_device *pdev) mc_data->dai_link[0].platforms->of_node = mc_data->dai_link[0].cpus->of_node; + ret = snd_soc_of_parse_tdm_slot(np, + &mc_data->tx_slot_mask, + &mc_data->rx_slot_mask, + &mc_data->slots, + &mc_data->slot_width); + if (ret < 0) { + dev_err(&pdev->dev, "snd_soc_of_parse_tdm_slot failed: %d\n", ret); + return ret; + } asrc_np = of_parse_phandle(np, "rockchip,asrc", 0); if (asrc_np) { mc_data->dai_link[1].cpus->of_node = asrc_np; From b58cb3ff2b0d6ec98db3e028caad2d7c8b4c49c1 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 15:35:09 +0800 Subject: [PATCH 05/16] PCI: rockchip: dw: Remove rk_pcie_clk_init() Move devm_clk_bulk_get_all into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: I4115faaa1fd84f7c7b521a025c3b9682e920c362 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 24 ++++--------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index c01dfedd7dd4..eedbf9d1eeb7 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -462,24 +462,6 @@ static int rk_add_pcie_port(struct rk_pcie *rk_pcie, struct platform_device *pde return 0; } -static int rk_pcie_clk_init(struct rk_pcie *rk_pcie) -{ - struct device *dev = rk_pcie->pci->dev; - int ret; - - rk_pcie->clk_cnt = devm_clk_bulk_get_all(dev, &rk_pcie->clks); - if (rk_pcie->clk_cnt < 1) - return -ENODEV; - - ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks); - if (ret) { - dev_err(dev, "failed to prepare enable pcie bulk clks: %d\n", ret); - return ret; - } - - return 0; -} - static int rk_pcie_resource_get(struct platform_device *pdev, struct rk_pcie *rk_pcie) { @@ -533,6 +515,10 @@ static int rk_pcie_resource_get(struct platform_device *pdev, if (IS_ERR_OR_NULL(rk_pcie->prsnt_gpio)) dev_info(&pdev->dev, "invalid prsnt-gpios property in node\n"); + rk_pcie->clk_cnt = devm_clk_bulk_get_all(&pdev->dev, &rk_pcie->clks); + if (rk_pcie->clk_cnt < 1) + return -ENODEV; + return 0; } @@ -1217,7 +1203,7 @@ retry_regulator: reset_control_deassert(rk_pcie->rsts); - ret = rk_pcie_clk_init(rk_pcie); + ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks); if (ret) { dev_err(dev, "clock init failed\n"); goto disable_phy; From b1d095908b62434c7eedb0b15888f1d4b2311037 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 15:41:26 +0800 Subject: [PATCH 06/16] PCI: rockchip: dw: Move getting rsts into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: I7c46fc1425037cc43e768a23a678ef5a348ee280 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index eedbf9d1eeb7..ff2c90802132 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -519,6 +519,12 @@ static int rk_pcie_resource_get(struct platform_device *pdev, if (rk_pcie->clk_cnt < 1) return -ENODEV; + rk_pcie->rsts = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(rk_pcie->rsts)) { + dev_err(&pdev->dev, "failed to get reset lines\n"); + return PTR_ERR(rk_pcie->rsts); + } + return 0; } @@ -1194,13 +1200,6 @@ retry_regulator: goto disable_vpcie3v3; } - rk_pcie->rsts = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(rk_pcie->rsts)) { - ret = PTR_ERR(rk_pcie->rsts); - dev_err(dev, "failed to get reset lines\n"); - goto disable_phy; - } - reset_control_deassert(rk_pcie->rsts); ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks); From 95a000fc6ce7479d309d61b4bebed6dc06dea1b1 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 15:48:03 +0800 Subject: [PATCH 07/16] PCI: rockchip: dw: Move getting clkreq, HP and bifurcation into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: Ifb3a16eadbbb50a64a6b53967fa906f363998674 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index ff2c90802132..cadba7126c3e 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -525,6 +525,17 @@ static int rk_pcie_resource_get(struct platform_device *pdev, return PTR_ERR(rk_pcie->rsts); } + if (device_property_read_bool(&pdev->dev, "rockchip,bifurcation")) + rk_pcie->bifurcation = true; + + rk_pcie->supports_clkreq = device_property_read_bool(&pdev->dev, "supports-clkreq"); + + if (device_property_read_bool(&pdev->dev, "hotplug-gpios") || + device_property_read_bool(&pdev->dev, "hotplug-gpio")) { + rk_pcie->slot_pluggable = true; + dev_info(&pdev->dev, "support hotplug-gpios!\n"); + } + return 0; } @@ -1146,9 +1157,6 @@ static int rk_pcie_really_probe(void *p) rk_pcie->msi_vector_num = data->msi_vector_num; rk_pcie->pci = pci; - if (device_property_read_bool(dev, "rockchip,bifurcation")) - rk_pcie->bifurcation = true; - ret = rk_pcie_resource_get(pdev, rk_pcie); if (ret) { dev_err(dev, "resource init failed\n"); @@ -1163,14 +1171,6 @@ static int rk_pcie_really_probe(void *p) } } - rk_pcie->supports_clkreq = device_property_read_bool(dev, "supports-clkreq"); - - if (device_property_read_bool(dev, "hotplug-gpios") || - device_property_read_bool(dev, "hotplug-gpio")) { - rk_pcie->slot_pluggable = true; - dev_info(dev, "support hotplug-gpios!\n"); - } - retry_regulator: /* DON'T MOVE ME: must be enable before phy init */ rk_pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); From a7ee33c78d68bcfff8e1cadada5ee2c3c3807d1c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 16:02:22 +0800 Subject: [PATCH 08/16] PCI: rockchip: dw: Move getting vpcie3v3 into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: I7fb17e48c7ee795454a0a15d0331ffeee4046c98 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 37 +++++++++---------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index cadba7126c3e..50091161a0dc 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -467,6 +467,7 @@ static int rk_pcie_resource_get(struct platform_device *pdev, { struct resource *dbi_base; struct resource *apb_base; + u32 val = 0; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-dbi"); @@ -536,6 +537,23 @@ static int rk_pcie_resource_get(struct platform_device *pdev, dev_info(&pdev->dev, "support hotplug-gpios!\n"); } +retry_regulator: + rk_pcie->vpcie3v3 = devm_regulator_get_optional(&pdev->dev, "vpcie3v3"); + if (IS_ERR(rk_pcie->vpcie3v3)) { + if (PTR_ERR(rk_pcie->vpcie3v3) != -ENODEV) { + if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT)) { + /* Deferred but in threaded context for most 10s */ + msleep(20); + if (++val < 500) + goto retry_regulator; + } + + return PTR_ERR(rk_pcie->vpcie3v3); + } + + dev_info(&pdev->dev, "no vpcie3v3 regulator found\n"); + } + return 0; } @@ -1171,25 +1189,6 @@ static int rk_pcie_really_probe(void *p) } } -retry_regulator: - /* DON'T MOVE ME: must be enable before phy init */ - rk_pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); - if (IS_ERR(rk_pcie->vpcie3v3)) { - if (PTR_ERR(rk_pcie->vpcie3v3) != -ENODEV) { - if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT)) { - /* Deferred but in threaded context for most 10s */ - msleep(20); - if (++val < 500) - goto retry_regulator; - } - - ret = PTR_ERR(rk_pcie->vpcie3v3); - goto release_driver; - } - - dev_info(dev, "no vpcie3v3 regulator found\n"); - } - ret = rk_pcie_enable_power(rk_pcie); if (ret) goto release_driver; From deccf139df422052bfcbaba190ea80ddc63e8015 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 16:12:48 +0800 Subject: [PATCH 09/16] PCI: rockchip: dw: Move getting skip_scan_in_resume into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: I422ad5e53d1a377e7e0b2a11e5144ce54b938be9 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 50091161a0dc..ccac9a5f3d0d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -537,6 +537,10 @@ static int rk_pcie_resource_get(struct platform_device *pdev, dev_info(&pdev->dev, "support hotplug-gpios!\n"); } + /* Skip waiting for training to pass in system PM routine */ + if (device_property_read_bool(&pdev->dev, "rockchip,skip-scan-in-resume")) + rk_pcie->skip_scan_in_resume = true; + retry_regulator: rk_pcie->vpcie3v3 = devm_regulator_get_optional(&pdev->dev, "vpcie3v3"); if (IS_ERR(rk_pcie->vpcie3v3)) { @@ -1275,10 +1279,6 @@ static int rk_pcie_really_probe(void *p) rk_pcie->is_signal_test = true; } - /* Skip waiting for training to pass in system PM routine */ - if (device_property_read_bool(dev, "rockchip,skip-scan-in-resume")) - rk_pcie->skip_scan_in_resume = true; - rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq"); if (!rk_pcie->hot_rst_wq) { dev_err(dev, "failed to create hot_rst workqueue\n"); From 6d90c6b51356faaf8b25d7cb0ebb5d8f03c0d2e7 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 2 Aug 2024 16:30:06 +0800 Subject: [PATCH 10/16] PCI: rockchip: dw: Move getting lpbk and comp into rk_pcie_resource_get() Signed-off-by: Shawn Lin Change-Id: Iaa9e7b22c402ad528e7ba839bcf4bd7d697dcedd --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 56 +++++++++++-------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index ccac9a5f3d0d..899f9ff5cc7c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -135,6 +135,8 @@ struct rk_pcie { bool slot_pluggable; struct gpio_hotplug_slot hp_slot; bool hp_no_link; + bool is_lpbk; + bool is_comp; struct regulator *vpcie3v3; struct irq_domain *irq_domain; raw_spinlock_t intx_lock; @@ -541,6 +543,32 @@ static int rk_pcie_resource_get(struct platform_device *pdev, if (device_property_read_bool(&pdev->dev, "rockchip,skip-scan-in-resume")) rk_pcie->skip_scan_in_resume = true; + /* Force into loopback master mode */ + if (device_property_read_bool(&pdev->dev, "rockchip,lpbk-master")) { + rk_pcie->is_lpbk = true; + rk_pcie->is_signal_test = true; + } + + /* + * Force into compliance mode + * comp_prst is a two dimensional array of which the first element + * stands for speed mode, and the second one is preset value encoding: + * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting + * [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero. + */ + if (!device_property_read_u32_array(&pdev->dev, "rockchip,compliance-mode", + rk_pcie->comp_prst, 2)) { + WARN_ON_ONCE(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10); + if (!rk_pcie->comp_prst[0]) + dev_info(&pdev->dev, "Auto compliance mode for SMA tool.\n"); + else + dev_info(&pdev->dev, "compliance mode for soldered board Gen%d, P%d.\n", + rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]); + + rk_pcie->is_comp = true; + rk_pcie->is_signal_test = true; + } + retry_regulator: rk_pcie->vpcie3v3 = devm_regulator_get_optional(&pdev->dev, "vpcie3v3"); if (IS_ERR(rk_pcie->vpcie3v3)) { @@ -1249,34 +1277,16 @@ static int rk_pcie_really_probe(void *p) /* Set PCIe RC mode */ rk_pcie_set_mode(rk_pcie); - /* Force into loopback master mode */ - if (device_property_read_bool(dev, "rockchip,lpbk-master")) { + if (rk_pcie->is_lpbk) { val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val |= PORT_LINK_LPBK_ENABLE; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - rk_pcie->is_signal_test = true; } - /* - * Force into compliance mode - * comp_prst is a two dimensional array of which the first element - * stands for speed mode, and the second one is preset value encoding: - * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting - * [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero. - */ - if (!device_property_read_u32_array(dev, "rockchip,compliance-mode", - rk_pcie->comp_prst, 2)) { - BUG_ON(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10); - if (!rk_pcie->comp_prst[0]) { - dev_info(dev, "Auto compliance mode for SMA tool.\n"); - } else { - dev_info(dev, "compliance mode for soldered board Gen%d, P%d.\n", - rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]); - val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); - val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12); - dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); - } - rk_pcie->is_signal_test = true; + if (rk_pcie->is_comp && rk_pcie->comp_prst[0]) { + val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); + val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12); + dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); } rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq"); From a8e681d5428a1eadd8911c1ac4a0bbf266e7122a Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 21 Aug 2024 20:21:13 +0800 Subject: [PATCH 11/16] PCI: rockchip: dw: Release PCIe reset/clock before phy initial In order to let combo phy check the mplla_state/mpllb_state. Signed-off-by: Shawn Lin Change-Id: I22da2ad35a12c1f135dcbb940e235f9cb179c439 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 899f9ff5cc7c..8ebc55c12ddf 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1225,18 +1225,18 @@ static int rk_pcie_really_probe(void *p) if (ret) goto release_driver; - ret = rk_pcie_phy_init(rk_pcie); - if (ret) { - dev_err(dev, "phy init failed\n"); - goto disable_vpcie3v3; - } - reset_control_deassert(rk_pcie->rsts); ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks); if (ret) { dev_err(dev, "clock init failed\n"); - goto disable_phy; + goto disable_vpcie3v3; + } + + ret = rk_pcie_phy_init(rk_pcie); + if (ret) { + dev_err(dev, "phy init failed\n"); + goto disable_clk; } /* @@ -1250,7 +1250,7 @@ static int rk_pcie_really_probe(void *p) ret = rk_pcie_request_sys_irq(rk_pcie, pdev); if (ret) { dev_err(dev, "pcie irq init failed\n"); - goto disable_clk; + goto disable_phy; } platform_set_drvdata(pdev, rk_pcie); @@ -1360,11 +1360,11 @@ remove_rst_wq: remove_irq_domain: if (rk_pcie->irq_domain) irq_domain_remove(rk_pcie->irq_domain); -disable_clk: - clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks); disable_phy: phy_power_off(rk_pcie->phy); phy_exit(rk_pcie->phy); +disable_clk: + clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks); disable_vpcie3v3: rk_pcie_disable_power(rk_pcie); release_driver: From b4ce92d9e0ce9fbe04e5036f3ff00409a40ecee4 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Aug 2024 12:58:16 +0800 Subject: [PATCH 12/16] PCI: rockchip: dw: Move irq and wq into rk_pcie_init_irq_and_wq() Signed-off-by: Shawn Lin Change-Id: Iad6e116a43d72c198ec5b032cfc46229651f70d8 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 89 ++++++++++--------- 1 file changed, 49 insertions(+), 40 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 8ebc55c12ddf..81d4a0a29025 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1168,6 +1168,50 @@ static const struct gpio_hotplug_slot_plat_ops rk_pcie_gpio_hp_plat_ops = { .disable = rk_pcie_slot_disable, }; +static int rk_pcie_init_irq_and_wq(struct rk_pcie *rk_pcie, struct platform_device *pdev) +{ + struct device *dev = rk_pcie->pci->dev; + int ret, irq; + + /* + * Misc interrupts was masked by default. However, they will be + * unmasked by FW before jumpping into kernel. Mask all misc interrupts, + * as we don't need to ack them before registering irq. And they will be + * unmasked later. + */ + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xffffffff); + + ret = rk_pcie_request_sys_irq(rk_pcie, pdev); + if (ret) { + dev_err(dev, "pcie irq init failed\n"); + return ret; + } + + /* Legacy interrupt is optional */ + ret = rk_pcie_init_irq_domain(rk_pcie); + if (!ret) { + irq = platform_get_irq_byname(pdev, "legacy"); + if (irq >= 0) { + irq_set_chained_handler_and_data(irq, rk_pcie_legacy_int_handler, + rk_pcie); + /* Unmask all legacy interrupt from INTA~INTD */ + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY, + UNMASK_ALL_LEGACY_INT); + } else { + dev_info(dev, "missing legacy IRQ resource\n"); + } + } + + rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq"); + if (!rk_pcie->hot_rst_wq) { + dev_err(dev, "failed to create hot_rst workqueue\n"); + return -ENOMEM; + } + INIT_WORK(&rk_pcie->hot_rst_work, rk_pcie_hot_rst_work); + + return 0; +} + static int rk_pcie_really_probe(void *p) { struct platform_device *pdev = p; @@ -1178,7 +1222,6 @@ static int rk_pcie_really_probe(void *p) const struct of_device_id *match; const struct rk_pcie_of_data *data; u32 val = 0; - int irq; match = of_match_device(rk_pcie_of_match, dev); if (!match) { @@ -1239,19 +1282,9 @@ static int rk_pcie_really_probe(void *p) goto disable_clk; } - /* - * Misc interrupts was masked by default. However, they will be - * unmasked by FW before jumpping into kernel. Mask all misc interrupts, - * as we don't need to ack them before registering irq. And they will be - * unmasked later. - */ - rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xffffffff); - - ret = rk_pcie_request_sys_irq(rk_pcie, pdev); - if (ret) { - dev_err(dev, "pcie irq init failed\n"); + ret = rk_pcie_init_irq_and_wq(rk_pcie, pdev); + if (ret) goto disable_phy; - } platform_set_drvdata(pdev, rk_pcie); @@ -1259,21 +1292,6 @@ static int rk_pcie_really_probe(void *p) rk_pcie_fast_link_setup(rk_pcie); - /* Legacy interrupt is optional */ - ret = rk_pcie_init_irq_domain(rk_pcie); - if (!ret) { - irq = platform_get_irq_byname(pdev, "legacy"); - if (irq >= 0) { - irq_set_chained_handler_and_data(irq, rk_pcie_legacy_int_handler, - rk_pcie); - /* Unmask all legacy interrupt from INTA~INTD */ - rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY, - UNMASK_ALL_LEGACY_INT); - } else { - dev_info(dev, "missing legacy IRQ resource\n"); - } - } - /* Set PCIe RC mode */ rk_pcie_set_mode(rk_pcie); @@ -1289,21 +1307,13 @@ static int rk_pcie_really_probe(void *p) dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); } - rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq"); - if (!rk_pcie->hot_rst_wq) { - dev_err(dev, "failed to create hot_rst workqueue\n"); - ret = -ENOMEM; - goto remove_irq_domain; - } - INIT_WORK(&rk_pcie->hot_rst_work, rk_pcie_hot_rst_work); - ret = rk_add_pcie_port(rk_pcie, pdev); if (rk_pcie->is_signal_test == true) return 0; if (ret && !rk_pcie->slot_pluggable) - goto remove_rst_wq; + goto deinit_irq_and_wq; if (rk_pcie->slot_pluggable) { rk_pcie->hp_slot.plat_ops = &rk_pcie_gpio_hp_plat_ops; @@ -1322,7 +1332,7 @@ static int rk_pcie_really_probe(void *p) ret = rk_pcie_init_dma_trx(rk_pcie); if (ret) { dev_err(dev, "failed to add dma extension\n"); - goto remove_rst_wq; + goto deinit_irq_and_wq; } if (rk_pcie->dma_obj) { @@ -1355,9 +1365,8 @@ static int rk_pcie_really_probe(void *p) return 0; -remove_rst_wq: +deinit_irq_and_wq: destroy_workqueue(rk_pcie->hot_rst_wq); -remove_irq_domain: if (rk_pcie->irq_domain) irq_domain_remove(rk_pcie->irq_domain); disable_phy: From 52729bfafff92e4f0ead1b53a63373cbb5d9a452 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Aug 2024 13:03:29 +0800 Subject: [PATCH 13/16] PCI: rockchip: dw: Move dma_obj initialization into rk_pcie_init_dma_trx() Signed-off-by: Shawn Lin Change-Id: Id8c744d891c00fb9b121baf33637dfe47b73a69f --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 183 +++++++++--------- 1 file changed, 91 insertions(+), 92 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 81d4a0a29025..9a963b553dd2 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -394,6 +394,93 @@ static bool rk_pcie_udma_enabled(struct rk_pcie *rk_pcie) PCIE_DMA_CTRL_OFF); } +static void rk_pcie_start_dma_rd(struct dma_trx_obj *obj, struct dma_table *cur, int ctr_off) +{ + struct rk_pcie *rk_pcie = dev_get_drvdata(obj->dev); + + dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_ENB, + cur->enb.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_LO, + cur->ctx_reg.ctrllo.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_HI, + cur->ctx_reg.ctrlhi.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_XFERSIZE, + cur->ctx_reg.xfersize); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_LO, + cur->ctx_reg.sarptrlo); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_HI, + cur->ctx_reg.sarptrhi); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_LO, + cur->ctx_reg.darptrlo); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_HI, + cur->ctx_reg.darptrhi); + dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_DOORBELL, + cur->start.asdword); +} + +static void rk_pcie_start_dma_wr(struct dma_trx_obj *obj, struct dma_table *cur, int ctr_off) +{ + struct rk_pcie *rk_pcie = dev_get_drvdata(obj->dev); + + dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_ENB, + cur->enb.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_LO, + cur->ctx_reg.ctrllo.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_HI, + cur->ctx_reg.ctrlhi.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_XFERSIZE, + cur->ctx_reg.xfersize); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_LO, + cur->ctx_reg.sarptrlo); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_HI, + cur->ctx_reg.sarptrhi); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_LO, + cur->ctx_reg.darptrlo); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_HI, + cur->ctx_reg.darptrhi); + dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_WEILO, + cur->weilo.asdword); + dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_DOORBELL, + cur->start.asdword); +} + +static void rk_pcie_start_dma_dwc(struct dma_trx_obj *obj, struct dma_table *table) +{ + int dir = table->dir; + int chn = table->chn; + + int ctr_off = PCIE_DMA_OFFSET + chn * 0x200; + + if (dir == DMA_FROM_BUS) + rk_pcie_start_dma_rd(obj, table, ctr_off); + else if (dir == DMA_TO_BUS) + rk_pcie_start_dma_wr(obj, table, ctr_off); +} + +static void rk_pcie_config_dma_dwc(struct dma_table *table) +{ + table->enb.enb = 0x1; + table->ctx_reg.ctrllo.lie = 0x1; + table->ctx_reg.ctrllo.rie = 0x0; + table->ctx_reg.ctrllo.td = 0x1; + table->ctx_reg.ctrlhi.asdword = 0x0; + table->ctx_reg.xfersize = table->buf_size; + if (table->dir == DMA_FROM_BUS) { + table->ctx_reg.sarptrlo = (u32)(table->bus & 0xffffffff); + table->ctx_reg.sarptrhi = (u32)(table->bus >> 32); + table->ctx_reg.darptrlo = (u32)(table->local & 0xffffffff); + table->ctx_reg.darptrhi = (u32)(table->local >> 32); + } else if (table->dir == DMA_TO_BUS) { + table->ctx_reg.sarptrlo = (u32)(table->local & 0xffffffff); + table->ctx_reg.sarptrhi = (u32)(table->local >> 32); + table->ctx_reg.darptrlo = (u32)(table->bus & 0xffffffff); + table->ctx_reg.darptrhi = (u32)(table->bus >> 32); + } + table->weilo.weight0 = 0x0; + table->start.stop = 0x0; + table->start.chnl = table->chn; +} + static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie) { if (!rk_pcie_udma_enabled(rk_pcie)) @@ -414,6 +501,10 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie) /* Enable core read interrupt */ dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK, 0x0); + + rk_pcie->dma_obj->start_dma_func = rk_pcie_start_dma_dwc; + rk_pcie->dma_obj->config_dma_func = rk_pcie_config_dma_dwc; + return 0; } @@ -621,93 +712,6 @@ static int rk_pcie_phy_init(struct rk_pcie *rk_pcie) return 0; } -static void rk_pcie_start_dma_rd(struct dma_trx_obj *obj, struct dma_table *cur, int ctr_off) -{ - struct rk_pcie *rk_pcie = dev_get_drvdata(obj->dev); - - dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_ENB, - cur->enb.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_LO, - cur->ctx_reg.ctrllo.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_HI, - cur->ctx_reg.ctrlhi.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_XFERSIZE, - cur->ctx_reg.xfersize); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_LO, - cur->ctx_reg.sarptrlo); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_HI, - cur->ctx_reg.sarptrhi); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_LO, - cur->ctx_reg.darptrlo); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_HI, - cur->ctx_reg.darptrhi); - dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_DOORBELL, - cur->start.asdword); -} - -static void rk_pcie_start_dma_wr(struct dma_trx_obj *obj, struct dma_table *cur, int ctr_off) -{ - struct rk_pcie *rk_pcie = dev_get_drvdata(obj->dev); - - dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_ENB, - cur->enb.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_LO, - cur->ctx_reg.ctrllo.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_HI, - cur->ctx_reg.ctrlhi.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_XFERSIZE, - cur->ctx_reg.xfersize); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_LO, - cur->ctx_reg.sarptrlo); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_HI, - cur->ctx_reg.sarptrhi); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_LO, - cur->ctx_reg.darptrlo); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_HI, - cur->ctx_reg.darptrhi); - dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_WEILO, - cur->weilo.asdword); - dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_DOORBELL, - cur->start.asdword); -} - -static void rk_pcie_start_dma_dwc(struct dma_trx_obj *obj, struct dma_table *table) -{ - int dir = table->dir; - int chn = table->chn; - - int ctr_off = PCIE_DMA_OFFSET + chn * 0x200; - - if (dir == DMA_FROM_BUS) - rk_pcie_start_dma_rd(obj, table, ctr_off); - else if (dir == DMA_TO_BUS) - rk_pcie_start_dma_wr(obj, table, ctr_off); -} - -static void rk_pcie_config_dma_dwc(struct dma_table *table) -{ - table->enb.enb = 0x1; - table->ctx_reg.ctrllo.lie = 0x1; - table->ctx_reg.ctrllo.rie = 0x0; - table->ctx_reg.ctrllo.td = 0x1; - table->ctx_reg.ctrlhi.asdword = 0x0; - table->ctx_reg.xfersize = table->buf_size; - if (table->dir == DMA_FROM_BUS) { - table->ctx_reg.sarptrlo = (u32)(table->bus & 0xffffffff); - table->ctx_reg.sarptrhi = (u32)(table->bus >> 32); - table->ctx_reg.darptrlo = (u32)(table->local & 0xffffffff); - table->ctx_reg.darptrhi = (u32)(table->local >> 32); - } else if (table->dir == DMA_TO_BUS) { - table->ctx_reg.sarptrlo = (u32)(table->local & 0xffffffff); - table->ctx_reg.sarptrhi = (u32)(table->local >> 32); - table->ctx_reg.darptrlo = (u32)(table->bus & 0xffffffff); - table->ctx_reg.darptrhi = (u32)(table->bus >> 32); - } - table->weilo.weight0 = 0x0; - table->start.stop = 0x0; - table->start.chnl = table->chn; -} - static void rk_pcie_hot_rst_work(struct work_struct *work) { struct rk_pcie *rk_pcie = container_of(work, struct rk_pcie, hot_rst_work); @@ -1335,11 +1339,6 @@ static int rk_pcie_really_probe(void *p) goto deinit_irq_and_wq; } - if (rk_pcie->dma_obj) { - rk_pcie->dma_obj->start_dma_func = rk_pcie_start_dma_dwc; - rk_pcie->dma_obj->config_dma_func = rk_pcie_config_dma_dwc; - } - dw_pcie_dbi_ro_wr_dis(pci); device_init_wakeup(dev, true); From 5fd5f84e05567071fff8ab6fe9e4b0fba96c0d1e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Aug 2024 13:11:15 +0800 Subject: [PATCH 14/16] PCI: rockchip: dw: Move debugfs all into rockchip_pcie_debugfs_init() Signed-off-by: Shawn Lin Change-Id: I34d9bdc41afa4051f903adf00a37eebaabc25524 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 32 ++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 9a963b553dd2..b3d86ed04c6c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -137,6 +137,7 @@ struct rk_pcie { bool hp_no_link; bool is_lpbk; bool is_comp; + bool have_rasdes; struct regulator *vpcie3v3; struct irq_domain *irq_domain; raw_spinlock_t intx_lock; @@ -1118,6 +1119,9 @@ static int rockchip_pcie_debugfs_init(struct rk_pcie *pcie) { struct dentry *file; + if (!IS_ENABLED(CONFIG_DEBUG_FS) || !pcie->have_rasdes) + return 0; + pcie->debugfs = debugfs_create_dir(dev_name(pcie->pci->dev), NULL); if (!pcie->debugfs) return -ENOMEM; @@ -1311,6 +1315,16 @@ static int rk_pcie_really_probe(void *p) dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); } + /* Enable RASDES Error event by default */ + val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_VNDR); + if (!val) { + dev_err(pci->dev, "Unable to find RASDES CAP!\n"); + } else { + dw_pcie_writel_dbi(pci, val + 8, 0x1c); + dw_pcie_writel_dbi(pci, val + 8, 0x3); + rk_pcie->have_rasdes = true; + } + ret = rk_add_pcie_port(rk_pcie, pdev); if (rk_pcie->is_signal_test == true) @@ -1346,21 +1360,9 @@ static int rk_pcie_really_probe(void *p) /* Enable async system PM for multiports SoC */ device_enable_async_suspend(dev); - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - ret = rockchip_pcie_debugfs_init(rk_pcie); - if (ret < 0) - dev_err(dev, "failed to setup debugfs: %d\n", ret); - - /* Enable RASDES Error event by default */ - val = dw_pcie_find_ext_capability(rk_pcie->pci, PCI_EXT_CAP_ID_VNDR); - if (!val) { - dev_err(dev, "Not able to find RASDES CAP!\n"); - return 0; - } - - dw_pcie_writel_dbi(rk_pcie->pci, val + 8, 0x1c); - dw_pcie_writel_dbi(rk_pcie->pci, val + 8, 0x3); - } + ret = rockchip_pcie_debugfs_init(rk_pcie); + if (ret < 0) + dev_err(dev, "failed to setup debugfs: %d\n", ret); return 0; From c54772e75b0d55b8bd5a7857f6131722479f2a63 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Aug 2024 14:11:28 +0800 Subject: [PATCH 15/16] PCI: rockchip: dw: Reorder and document steps of rk_pcie_really_probe() Signed-off-by: Shawn Lin Change-Id: Iffc9e7e04cc4329b7d0b71f9cc1dd1ee3080e7b6 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 70 +++++++++---------- 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index b3d86ed04c6c..3f2beca93626 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -204,7 +204,7 @@ static void disable_aspm_l1ss(struct rk_pcie *rk_pcie) static inline void disable_aspm_l1ss(struct rk_pcie *rk_pcie) { return; } #endif -static inline void rk_pcie_set_mode(struct rk_pcie *rk_pcie) +static inline void rk_pcie_set_rc_mode(struct rk_pcie *rk_pcie) { if (rk_pcie->supports_clkreq) { /* Application is ready to have reference clock removed */ @@ -1231,6 +1231,7 @@ static int rk_pcie_really_probe(void *p) const struct rk_pcie_of_data *data; u32 val = 0; + /* 1. resource initialization */ match = of_match_device(rk_pcie_of_match, dev); if (!match) { ret = -EINVAL; @@ -1251,19 +1252,21 @@ static int rk_pcie_really_probe(void *p) goto release_driver; } + /* 2. variables assignment */ + rk_pcie->pci = pci; + rk_pcie->msi_vector_num = data ? data->msi_vector_num : 0; pci->dev = dev; pci->ops = &dw_pcie_ops; + platform_set_drvdata(pdev, rk_pcie); - if (data) - rk_pcie->msi_vector_num = data->msi_vector_num; - rk_pcie->pci = pci; - + /* 3. firmware resource */ ret = rk_pcie_resource_get(pdev, rk_pcie); if (ret) { - dev_err(dev, "resource init failed\n"); + dev_err_probe(dev, ret, "resource init failed\n"); goto release_driver; } + /* 4. hardware io settings */ if (!IS_ERR_OR_NULL(rk_pcie->prsnt_gpio)) { if (!gpiod_get_value(rk_pcie->prsnt_gpio)) { dev_info(dev, "device isn't present\n"); @@ -1280,29 +1283,17 @@ static int rk_pcie_really_probe(void *p) ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks); if (ret) { - dev_err(dev, "clock init failed\n"); + dev_err_probe(dev, ret, "clock init failed\n"); goto disable_vpcie3v3; } ret = rk_pcie_phy_init(rk_pcie); if (ret) { - dev_err(dev, "phy init failed\n"); + dev_err_probe(dev, ret, "phy init failed\n"); goto disable_clk; } - ret = rk_pcie_init_irq_and_wq(rk_pcie, pdev); - if (ret) - goto disable_phy; - - platform_set_drvdata(pdev, rk_pcie); - - dw_pcie_dbi_ro_wr_en(pci); - - rk_pcie_fast_link_setup(rk_pcie); - - /* Set PCIe RC mode */ - rk_pcie_set_mode(rk_pcie); - + /* 5. signal test and capability settings */ if (rk_pcie->is_lpbk) { val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val |= PORT_LINK_LPBK_ENABLE; @@ -1325,6 +1316,17 @@ static int rk_pcie_really_probe(void *p) rk_pcie->have_rasdes = true; } + /* 6. software process */ + ret = rk_pcie_init_irq_and_wq(rk_pcie, pdev); + if (ret) + goto disable_phy; + + dw_pcie_dbi_ro_wr_en(pci); + + rk_pcie_fast_link_setup(rk_pcie); + + rk_pcie_set_rc_mode(rk_pcie); + ret = rk_add_pcie_port(rk_pcie, pdev); if (rk_pcie->is_signal_test == true) @@ -1349,20 +1351,19 @@ static int rk_pcie_really_probe(void *p) ret = rk_pcie_init_dma_trx(rk_pcie); if (ret) { - dev_err(dev, "failed to add dma extension\n"); + dev_err_probe(dev, ret, "failed to add dma extension\n"); goto deinit_irq_and_wq; } - dw_pcie_dbi_ro_wr_dis(pci); - - device_init_wakeup(dev, true); - - /* Enable async system PM for multiports SoC */ - device_enable_async_suspend(dev); - ret = rockchip_pcie_debugfs_init(rk_pcie); if (ret < 0) - dev_err(dev, "failed to setup debugfs: %d\n", ret); + dev_err_probe(dev, ret, "failed to setup debugfs\n"); + + dw_pcie_dbi_ro_wr_dis(pci); + + /* 7. framework misc settings */ + device_init_wakeup(dev, true); + device_enable_async_suspend(dev); /* Enable async system PM for multiports SoC */ return 0; @@ -1390,10 +1391,8 @@ static int rk_pcie_probe(struct platform_device *pdev) struct task_struct *tsk; tsk = kthread_run(rk_pcie_really_probe, pdev, "rk-pcie"); - if (IS_ERR(tsk)) { - dev_err(&pdev->dev, "start rk-pcie thread failed\n"); - return PTR_ERR(tsk); - } + if (IS_ERR(tsk)) + return dev_err_probe(&pdev->dev, PTR_ERR(tsk), "start rk-pcie thread failed\n"); return 0; } @@ -1605,8 +1604,7 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev) rk_pcie_fast_link_setup(rk_pcie); - /* Set PCIe RC mode */ - rk_pcie_set_mode(rk_pcie); + rk_pcie_set_rc_mode(rk_pcie); dw_pcie_setup_rc(&rk_pcie->pci->pp); From 0f7094037eff3940d4b6f6b1743a7d4a5a5e2b21 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Aug 2024 14:32:52 +0800 Subject: [PATCH 16/16] PCI: rockchip: dw: Remove forward definition of rk_pcie_{enable, disable}_power Signed-off-by: Shawn Lin Change-Id: I3e04e0ef5e320fcf6cc86e2923557e5dddedc4da --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 62 +++++++++---------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3f2beca93626..e2e05744a251 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -156,8 +156,6 @@ struct rk_pcie_of_data { }; #define to_rk_pcie(x) dev_get_drvdata((x)->dev) -static int rk_pcie_disable_power(struct rk_pcie *rk_pcie); -static int rk_pcie_enable_power(struct rk_pcie *rk_pcie); static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) { @@ -275,6 +273,36 @@ static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) #endif } +static int rk_pcie_enable_power(struct rk_pcie *rk_pcie) +{ + int ret = 0; + struct device *dev = rk_pcie->pci->dev; + + if (IS_ERR(rk_pcie->vpcie3v3)) + return ret; + + ret = regulator_enable(rk_pcie->vpcie3v3); + if (ret) + dev_err(dev, "fail to enable vpcie3v3 regulator\n"); + + return ret; +} + +static int rk_pcie_disable_power(struct rk_pcie *rk_pcie) +{ + int ret = 0; + struct device *dev = rk_pcie->pci->dev; + + if (IS_ERR(rk_pcie->vpcie3v3)) + return ret; + + ret = regulator_disable(rk_pcie->vpcie3v3); + if (ret) + dev_err(dev, "fail to disable vpcie3v3 regulator\n"); + + return ret; +} + static int rk_pcie_establish_link(struct dw_pcie *pci) { int retries, power; @@ -951,36 +979,6 @@ static int rk_pcie_init_irq_domain(struct rk_pcie *rockchip) return 0; } -static int rk_pcie_enable_power(struct rk_pcie *rk_pcie) -{ - int ret = 0; - struct device *dev = rk_pcie->pci->dev; - - if (IS_ERR(rk_pcie->vpcie3v3)) - return ret; - - ret = regulator_enable(rk_pcie->vpcie3v3); - if (ret) - dev_err(dev, "fail to enable vpcie3v3 regulator\n"); - - return ret; -} - -static int rk_pcie_disable_power(struct rk_pcie *rk_pcie) -{ - int ret = 0; - struct device *dev = rk_pcie->pci->dev; - - if (IS_ERR(rk_pcie->vpcie3v3)) - return ret; - - ret = regulator_disable(rk_pcie->vpcie3v3); - if (ret) - dev_err(dev, "fail to disable vpcie3v3 regulator\n"); - - return ret; -} - #define RAS_DES_EVENT(ss, v) \ do { \ dw_pcie_writel_dbi(pcie->pci, cap_base + 8, v); \